[linux-block.git] / drivers / misc / mei / pci-me.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
 * Intel Management Engine Interface (Intel MEI) Linux driver
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/sched.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(dev->dev);

	return pci_read_config_dword(pdev, where, val);
}

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg;
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;

	cfg = mei_me_get_cfg(ent->driver_data);
	if (!cfg)
		return -ENODEV;

	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pcim_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions and mapping IO device memory for mei driver */
	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto end;
	}

	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto end;
	}

	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(&pdev->dev, cfg, false);
	if (!dev) {
		err = -ENOMEM;
		goto end;
	}
	hw = to_me_hw(dev);
	hw->mem_addr = pcim_iomap_table(pdev)[0];
	hw->read_fws = mei_me_read_fws;

	pci_enable_msi(pdev);

	hw->irq = pdev->irq;

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto end;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	 * MEI requires to resume from runtime suspend mode
	 * in order to perform link reset flow upon system suspend.
	 */
	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);

	/*
	 * ME maps runtime suspend/resume to D0i states,
	 * hence we need to go around native PCI runtime service which
	 * eventually brings the device into D3cold/hot state,
	 * but the mei device cannot wake up from D3 unlike from D0i3.
	 * To get around the PCI device native runtime pm,
	 * ME uses runtime pm domain handlers which take precedence
	 * over the driver's pm handlers.
	 */
	mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev)) {
		pm_runtime_put_noidle(&pdev->dev);
		if (hw->d0i3_supported)
			pm_runtime_allow(&pdev->dev);
	}

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_shutdown - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_shutdown is called from the reboot notifier
 * it's a simplified version of remove so we go down
 * faster.
 */
static void mei_me_shutdown(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	dev_dbg(&pdev->dev, "shutdown\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);

	mei_deregister(dev);
}

#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_prepare(struct device *device)
{
	pm_runtime_resume(device);
	return 0;
}

static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	unsigned int irqflags;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}

static void mei_me_pci_complete(struct device *device)
{
	pm_runtime_suspend(device);
}
#else /* CONFIG_PM_SLEEP */

#define mei_me_pci_prepare NULL
#define mei_me_pci_complete NULL

#endif /* !CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct mei_device *dev;

	dev_dbg(device, "rpm: me: runtime_idle\n");

	dev = dev_get_drvdata(device);
	if (!dev)
		return -ENODEV;
	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct mei_device *dev;
	int ret;

	dev_dbg(device, "rpm: me: runtime suspend\n");

	dev = dev_get_drvdata(device);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct mei_device *dev;
	int ret;

	dev_dbg(device, "rpm: me: runtime resume\n");

	dev = dev_get_drvdata(device);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	.prepare = mei_me_pci_prepare,
	.complete = mei_me_pci_complete,
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_shutdown,
	.driver.pm = MEI_ME_PM_OPS,
	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fff0425	1	// SPDX-License-Identifier: GPL-2.0
2703d4b2	2	/*
95953618	3	* Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
2703d4b2	4	* Intel Management Engine Interface (Intel MEI) Linux driver
2703d4b2	5	*/
9fff0425	6
2703d4b2	7	#include <linux/module.h>
2703d4b2 TW	8	#include <linux/kernel.h>
2703d4b2 TW	9	#include <linux/device.h>
2703d4b2 TW	10	#include <linux/errno.h>
2703d4b2 TW	11	#include <linux/types.h>
2703d4b2	12	#include <linux/pci.h>
515a2f50	13	#include <linux/dma-mapping.h>
2703d4b2	14	#include <linux/sched.h>
2703d4b2	15	#include <linux/interrupt.h>
2703d4b2	16
989561de	17	#include <linux/pm_domain.h>
180ea05b TW	18	#include <linux/pm_runtime.h>
180ea05b TW	19
2703d4b2 TW	20	#include <linux/mei.h>
	21
	22	#include "mei_dev.h"
2703d4b2	23	#include "client.h"
6e4cd27a TW	24	#include "hw-me-regs.h"
6e4cd27a TW	25	#include "hw-me.h"
2703d4b2	26
2703d4b2	27	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	28	static const struct pci_device_id mei_me_pci_tbl[] = {
f5ac3c49 TW	29	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	30	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	31	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	32	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	33	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	34	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	35	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	36	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	37	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	38	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	39	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
	40
	41	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	42	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	43	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	44	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	45	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	46	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	48	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
	50
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
	55
f8204f0d AU	56	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
f8204f0d AU	57	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
f5ac3c49 TW	58	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
f5ac3c49 TW	59	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
f8204f0d AU	60	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
f76d77f5 TW	63	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
f76d77f5 TW	64	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
f5ac3c49	65	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
f76d77f5	66	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
f5ac3c49 TW	67	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
	69
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	71	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
2f79d3d1	72	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
f76d77f5 TW	73	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
	74	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
	75	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
f5ac3c49 TW	76
	77	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
	79
f7ee8ead TW	80	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
f7ee8ead TW	81
688cb678 TW	82	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
688cb678 TW	83
f5ac3c49 TW	84	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
f5ac3c49 TW	85	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
4afc339e	86	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
ac182e8a	87
1dbfe7f2	88	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
2f79d3d1	89	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
f76d77f5	90	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
2f79d3d1	91	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
f8f4aa68	92
4d86dfd3	93	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
2f79d3d1	94	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
82b29b9f	95	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
559e575a	96	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
2f79d3d1	97	{MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
4d86dfd3	98
efe814e9	99	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
75c10c5e	100	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
efe814e9	101
52f6efdf	102	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
8c289ea0	103	{MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
587f1740	104
0db4a15d TW	105	{MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
0db4a15d TW	106
52f6efdf	107	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
1be8624a AU	108	{MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
1be8624a AU	109
99397d33 AU	110	{MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
99397d33 AU	111
372726cb TW	112	{MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
372726cb TW	113
f7545efa	114	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
930c922a	115	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
0df74278	116	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
7bbbd084	117	{MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
f7545efa	118
3ed8c7d3 AU	119	{MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
3ed8c7d3 AU	120
0c4d6826 AU	121	{MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)},
0c4d6826 AU	122
2703d4b2 TW	123	/* required last entry */
	124	{0, }
	125	};
	126
b68301e9	127	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	128
bbd6d050	129	#ifdef CONFIG_PM
e13fa90c TW	130	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	131	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	132	#else
	133	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	134	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
bbd6d050	135	#endif /* CONFIG_PM */
e13fa90c	136
261e071a TW	137	static int mei_me_read_fws(const struct mei_device dev, int where, u32 val)
	138	{
	139	struct pci_dev *pdev = to_pci_dev(dev->dev);
	140
	141	return pci_read_config_dword(pdev, where, val);
	142	}
	143
2703d4b2	144	/**
ce23139c	145	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	146	*
2703d4b2	147	* @pdev: PCI device structure
c919951d	148	* @cfg: per generation config
2703d4b2	149	*
a8605ea2	150	* Return: true if ME Interface is valid, false otherwise
2703d4b2	151	*/
b68301e9	152	static bool mei_me_quirk_probe(struct pci_dev *pdev,
c919951d	153	const struct mei_cfg *cfg)
2703d4b2	154	{
c919951d TW	155	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	156	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	157	return false;
5e6533a6 TW	158	}
5e6533a6 TW	159
2703d4b2 TW	160	return true;
2703d4b2 TW	161	}
c919951d	162
2703d4b2	163	/**
ce23139c	164	* mei_me_probe - Device Initialization Routine
2703d4b2 TW	165	*
	166	* @pdev: PCI device structure
	167	* @ent: entry in kcs_pci_tbl
	168	*
a8605ea2	169	* Return: 0 on success, <0 on failure.
2703d4b2	170	*/
b68301e9	171	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2	172	{
f5ac3c49	173	const struct mei_cfg *cfg;
2703d4b2	174	struct mei_device *dev;
52c34561	175	struct mei_me_hw *hw;
1fa55b4e	176	unsigned int irqflags;
2703d4b2 TW	177	int err;
2703d4b2 TW	178
f5ac3c49 TW	179	cfg = mei_me_get_cfg(ent->driver_data);
	180	if (!cfg)
	181	return -ENODEV;
2703d4b2	182
c919951d TW	183	if (!mei_me_quirk_probe(pdev, cfg))
c919951d TW	184	return -ENODEV;
2703d4b2	185
2703d4b2	186	/* enable pci dev */
f8a09605	187	err = pcim_enable_device(pdev);
2703d4b2 TW	188	if (err) {
	189	dev_err(&pdev->dev, "failed to enable pci device.\n");
	190	goto end;
	191	}
	192	/* set PCI host mastering */
	193	pci_set_master(pdev);
f8a09605 TW	194	/* pci request regions and mapping IO device memory for mei driver */
f8a09605 TW	195	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
2703d4b2 TW	196	if (err) {
2703d4b2 TW	197	dev_err(&pdev->dev, "failed to get pci regions.\n");
f8a09605	198	goto end;
2703d4b2	199	}
3ecfb168	200
515a2f50	201	err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3ecfb168 TW	202	if (err) {
3ecfb168 TW	203	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
f8a09605	204	goto end;
3ecfb168 TW	205	}
3ecfb168 TW	206
2703d4b2	207	/* allocates and initializes the mei dev structure */
95953618	208	dev = mei_me_dev_init(&pdev->dev, cfg, false);
2703d4b2 TW	209	if (!dev) {
2703d4b2 TW	210	err = -ENOMEM;
f8a09605	211	goto end;
2703d4b2	212	}
52c34561	213	hw = to_me_hw(dev);
f8a09605	214	hw->mem_addr = pcim_iomap_table(pdev)[0];
261e071a	215	hw->read_fws = mei_me_read_fws;
f8a09605	216
2703d4b2 TW	217	pci_enable_msi(pdev);
2703d4b2 TW	218
fec874a8 BL	219	hw->irq = pdev->irq;
fec874a8 BL	220
2703d4b2	221	/* request and enable interrupt */
1fa55b4e AU	222	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	223
	224	err = request_threaded_irq(pdev->irq,
06ecd645 TW	225	mei_me_irq_quick_handler,
06ecd645 TW	226	mei_me_irq_thread_handler,
1fa55b4e	227	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	228	if (err) {
	229	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	230	pdev->irq);
f8a09605	231	goto end;
2703d4b2 TW	232	}
2703d4b2 TW	233
c4d589be	234	if (mei_start(dev)) {
2703d4b2 TW	235	dev_err(&pdev->dev, "init hw failure.\n");
	236	err = -ENODEV;
	237	goto release_irq;
	238	}
	239
180ea05b TW	240	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	241	pm_runtime_use_autosuspend(&pdev->dev);
	242
f3d8e878	243	err = mei_register(dev, &pdev->dev);
2703d4b2	244	if (err)
1f7e489a	245	goto stop;
2703d4b2	246
2703d4b2 TW	247	pci_set_drvdata(pdev, dev);
2703d4b2 TW	248
557909e1 AU	249	/*
	250	* MEI requires to resume from runtime suspend mode
	251	* in order to perform link reset flow upon system suspend.
	252	*/
e0751556	253	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
557909e1	254
e13fa90c	255	/*
b42dc063 AU	256	* ME maps runtime suspend/resume to D0i states,
	257	* hence we need to go around native PCI runtime service which
	258	* eventually brings the device into D3cold/hot state,
	259	* but the mei device cannot wake up from D3 unlike from D0i3.
	260	* To get around the PCI device native runtime pm,
	261	* ME uses runtime pm domain handlers which take precedence
	262	* over the driver's pm handlers.
	263	*/
	264	mei_me_set_pm_domain(dev);
e13fa90c	265
cc365dcf	266	if (mei_pg_is_enabled(dev)) {
180ea05b	267	pm_runtime_put_noidle(&pdev->dev);
cc365dcf TW	268	if (hw->d0i3_supported)
	269	pm_runtime_allow(&pdev->dev);
	270	}
180ea05b	271
c4e87b52	272	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	273
	274	return 0;
	275
1f7e489a AU	276	stop:
1f7e489a AU	277	mei_stop(dev);
2703d4b2	278	release_irq:
dc844b0d	279	mei_cancel_work(dev);
2703d4b2	280	mei_disable_interrupts(dev);
2703d4b2	281	free_irq(pdev->irq, dev);
2703d4b2	282	end:
2703d4b2 TW	283	dev_err(&pdev->dev, "initialization failed.\n");
	284	return err;
	285	}
	286
5c4c0106 TW	287	/**
	288	* mei_me_shutdown - Device Removal Routine
	289	*
	290	* @pdev: PCI device structure
	291	*
	292	* mei_me_shutdown is called from the reboot notifier
	293	* it's a simplified version of remove so we go down
	294	* faster.
	295	*/
	296	static void mei_me_shutdown(struct pci_dev *pdev)
	297	{
	298	struct mei_device *dev;
	299
	300	dev = pci_get_drvdata(pdev);
	301	if (!dev)
	302	return;
	303
	304	dev_dbg(&pdev->dev, "shutdown\n");
	305	mei_stop(dev);
	306
b42dc063	307	mei_me_unset_pm_domain(dev);
5c4c0106 TW	308
	309	mei_disable_interrupts(dev);
	310	free_irq(pdev->irq, dev);
	311	}
	312
2703d4b2	313	/**
ce23139c	314	* mei_me_remove - Device Removal Routine
2703d4b2 TW	315	*
	316	* @pdev: PCI device structure
	317	*
5c4c0106	318	* mei_me_remove is called by the PCI subsystem to alert the driver
2703d4b2 TW	319	* that it should release a PCI device.
2703d4b2 TW	320	*/
b68301e9	321	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	322	{
	323	struct mei_device *dev;
	324
2703d4b2 TW	325	dev = pci_get_drvdata(pdev);
	326	if (!dev)
	327	return;
	328
180ea05b TW	329	if (mei_pg_is_enabled(dev))
	330	pm_runtime_get_noresume(&pdev->dev);
	331
ed6f7ac1	332	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	333	mei_stop(dev);
2703d4b2	334
b42dc063	335	mei_me_unset_pm_domain(dev);
e13fa90c	336
2703d4b2 TW	337	mei_disable_interrupts(dev);
	338
	339	free_irq(pdev->irq, dev);
2703d4b2	340
30e53bb8	341	mei_deregister(dev);
2703d4b2	342	}
f8a09605	343
16833257	344	#ifdef CONFIG_PM_SLEEP
907deab2 AU	345	static int mei_me_pci_prepare(struct device *device)
	346	{
	347	pm_runtime_resume(device);
	348	return 0;
	349	}
	350
b68301e9	351	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	352	{
	353	struct pci_dev *pdev = to_pci_dev(device);
	354	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	355
	356	if (!dev)
	357	return -ENODEV;
2703d4b2	358
ed6f7ac1	359	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	360
7cb035d9 TW	361	mei_stop(dev);
	362
	363	mei_disable_interrupts(dev);
2703d4b2 TW	364
	365	free_irq(pdev->irq, dev);
	366	pci_disable_msi(pdev);
	367
7cb035d9	368	return 0;
2703d4b2 TW	369	}
2703d4b2 TW	370
b68301e9	371	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	372	{
	373	struct pci_dev *pdev = to_pci_dev(device);
	374	struct mei_device *dev;
1fa55b4e	375	unsigned int irqflags;
2703d4b2 TW	376	int err;
	377
	378	dev = pci_get_drvdata(pdev);
	379	if (!dev)
	380	return -ENODEV;
	381
	382	pci_enable_msi(pdev);
	383
1fa55b4e AU	384	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
1fa55b4e AU	385
2703d4b2	386	/* request and enable interrupt */
1fa55b4e	387	err = request_threaded_irq(pdev->irq,
06ecd645 TW	388	mei_me_irq_quick_handler,
06ecd645 TW	389	mei_me_irq_thread_handler,
1fa55b4e	390	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	391
	392	if (err) {
	393	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	394	pdev->irq);
	395	return err;
	396	}
	397
33ec0826 TW	398	err = mei_restart(dev);
	399	if (err)
	400	return err;
2703d4b2 TW	401
	402	/* Start timer if stopped in suspend */
	403	schedule_delayed_work(&dev->timer_work, HZ);
	404
33ec0826	405	return 0;
2703d4b2	406	}
907deab2 AU	407
	408	static void mei_me_pci_complete(struct device *device)
	409	{
	410	pm_runtime_suspend(device);
	411	}
	412	#else /* CONFIG_PM_SLEEP */
	413
	414	#define mei_me_pci_prepare NULL
	415	#define mei_me_pci_complete NULL
	416
	417	#endif /* !CONFIG_PM_SLEEP */
180ea05b	418
bbd6d050	419	#ifdef CONFIG_PM
180ea05b TW	420	static int mei_me_pm_runtime_idle(struct device *device)
180ea05b TW	421	{
180ea05b TW	422	struct mei_device *dev;
180ea05b TW	423
ab81f3f3	424	dev_dbg(device, "rpm: me: runtime_idle\n");
180ea05b	425
ab81f3f3	426	dev = dev_get_drvdata(device);
180ea05b TW	427	if (!dev)
	428	return -ENODEV;
	429	if (mei_write_is_idle(dev))
d5d83f8a	430	pm_runtime_autosuspend(device);
180ea05b TW	431
	432	return -EBUSY;
	433	}
	434
	435	static int mei_me_pm_runtime_suspend(struct device *device)
	436	{
180ea05b TW	437	struct mei_device *dev;
	438	int ret;
	439
ab81f3f3	440	dev_dbg(device, "rpm: me: runtime suspend\n");
180ea05b	441
ab81f3f3	442	dev = dev_get_drvdata(device);
180ea05b TW	443	if (!dev)
	444	return -ENODEV;
	445
	446	mutex_lock(&dev->device_lock);
	447
	448	if (mei_write_is_idle(dev))
2d1995fc	449	ret = mei_me_pg_enter_sync(dev);
180ea05b TW	450	else
	451	ret = -EAGAIN;
	452
	453	mutex_unlock(&dev->device_lock);
	454
ab81f3f3	455	dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
180ea05b	456
77537ad2 AU	457	if (ret && ret != -EAGAIN)
	458	schedule_work(&dev->reset_work);
	459
180ea05b TW	460	return ret;
	461	}
	462
	463	static int mei_me_pm_runtime_resume(struct device *device)
	464	{
180ea05b TW	465	struct mei_device *dev;
	466	int ret;
	467
ab81f3f3	468	dev_dbg(device, "rpm: me: runtime resume\n");
180ea05b	469
ab81f3f3	470	dev = dev_get_drvdata(device);
180ea05b TW	471	if (!dev)
	472	return -ENODEV;
	473
	474	mutex_lock(&dev->device_lock);
	475
2d1995fc	476	ret = mei_me_pg_exit_sync(dev);
180ea05b TW	477
	478	mutex_unlock(&dev->device_lock);
	479
ab81f3f3	480	dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
180ea05b	481
77537ad2 AU	482	if (ret)
	483	schedule_work(&dev->reset_work);
	484
180ea05b TW	485	return ret;
180ea05b TW	486	}
e13fa90c TW	487
e13fa90c TW	488	/**
7efceb55	489	* mei_me_set_pm_domain - fill and set pm domain structure for device
e13fa90c TW	490	*
	491	* @dev: mei_device
	492	*/
	493	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	494	{
d08b8fc0	495	struct pci_dev *pdev = to_pci_dev(dev->dev);
e13fa90c TW	496
	497	if (pdev->dev.bus && pdev->dev.bus->pm) {
	498	dev->pg_domain.ops = *pdev->dev.bus->pm;
	499
	500	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	501	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	502	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	503
989561de	504	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
e13fa90c TW	505	}
	506	}
	507
	508	/**
7efceb55	509	* mei_me_unset_pm_domain - clean pm domain structure for device
e13fa90c TW	510	*
	511	* @dev: mei_device
	512	*/
	513	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	514	{
	515	/* stop using pm callbacks if any */
989561de	516	dev_pm_domain_set(dev->dev, NULL);
e13fa90c	517	}
180ea05b	518
180ea05b	519	static const struct dev_pm_ops mei_me_pm_ops = {
907deab2 AU	520	.prepare = mei_me_pci_prepare,
907deab2 AU	521	.complete = mei_me_pci_complete,
180ea05b TW	522	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	523	mei_me_pci_resume)
	524	SET_RUNTIME_PM_OPS(
	525	mei_me_pm_runtime_suspend,
	526	mei_me_pm_runtime_resume,
	527	mei_me_pm_runtime_idle)
	528	};
16833257	529
b68301e9	530	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	531	#else
b68301e9	532	#define MEI_ME_PM_OPS NULL
180ea05b	533	#endif /* CONFIG_PM */
2703d4b2 TW	534	/*
	535	* PCI driver structure
	536	*/
b68301e9	537	static struct pci_driver mei_me_driver = {
2703d4b2	538	.name = KBUILD_MODNAME,
b68301e9 TW	539	.id_table = mei_me_pci_tbl,
	540	.probe = mei_me_probe,
	541	.remove = mei_me_remove,
5c4c0106	542	.shutdown = mei_me_shutdown,
b68301e9	543	.driver.pm = MEI_ME_PM_OPS,
67de6bf1	544	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
2703d4b2 TW	545	};
2703d4b2 TW	546
b68301e9	547	module_pci_driver(mei_me_driver);
2703d4b2 TW	548
	549	MODULE_AUTHOR("Intel Corporation");
	550	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	551	MODULE_LICENSE("GPL v2");