[linux-block.git] / drivers / misc / mei / pci-me.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
 * Intel Management Engine Interface (Intel MEI) Linux driver
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/uuid.h>
#include <linux/compat.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg;
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;

	cfg = mei_me_get_cfg(ent->driver_data);
	if (!cfg)
		return -ENODEV;

	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pcim_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions and mapping IO device memory for mei driver */
	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto end;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {

		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
		if (err)
			err = dma_set_coherent_mask(&pdev->dev,
						    DMA_BIT_MASK(32));
	}
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto end;
	}

	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(pdev, cfg);
	if (!dev) {
		err = -ENOMEM;
		goto end;
	}
	hw = to_me_hw(dev);
	hw->mem_addr = pcim_iomap_table(pdev)[0];

	pci_enable_msi(pdev);

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto end;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	 * MEI requires to resume from runtime suspend mode
	 * in order to perform link reset flow upon system suspend.
	 */
	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);

	/*
	 * ME maps runtime suspend/resume to D0i states,
	 * hence we need to go around native PCI runtime service which
	 * eventually brings the device into D3cold/hot state,
	 * but the mei device cannot wake up from D3 unlike from D0i3.
	 * To get around the PCI device native runtime pm,
	 * ME uses runtime pm domain handlers which take precedence
	 * over the driver's pm handlers.
	 */
	mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev)) {
		pm_runtime_put_noidle(&pdev->dev);
		if (hw->d0i3_supported)
			pm_runtime_allow(&pdev->dev);
	}

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_shutdown - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_shutdown is called from the reboot notifier
 * it's a simplified version of remove so we go down
 * faster.
 */
static void mei_me_shutdown(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	dev_dbg(&pdev->dev, "shutdown\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);

	mei_deregister(dev);
}

#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	unsigned int irqflags;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;

	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;
	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_shutdown,
	.driver.pm = MEI_ME_PM_OPS,
	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fff0425	1	// SPDX-License-Identifier: GPL-2.0
2703d4b2	2	/*
1e55b609	3	* Copyright (c) 2003-2019, Intel Corporation. All rights reserved.
2703d4b2	4	* Intel Management Engine Interface (Intel MEI) Linux driver
2703d4b2	5	*/
9fff0425	6
2703d4b2 TW	7	#include <linux/module.h>
	8	#include <linux/moduleparam.h>
	9	#include <linux/kernel.h>
	10	#include <linux/device.h>
	11	#include <linux/fs.h>
	12	#include <linux/errno.h>
	13	#include <linux/types.h>
	14	#include <linux/fcntl.h>
2703d4b2 TW	15	#include <linux/pci.h>
2703d4b2 TW	16	#include <linux/poll.h>
2703d4b2 TW	17	#include <linux/ioctl.h>
	18	#include <linux/cdev.h>
	19	#include <linux/sched.h>
	20	#include <linux/uuid.h>
	21	#include <linux/compat.h>
	22	#include <linux/jiffies.h>
	23	#include <linux/interrupt.h>
2703d4b2	24
989561de	25	#include <linux/pm_domain.h>
180ea05b TW	26	#include <linux/pm_runtime.h>
180ea05b TW	27
2703d4b2 TW	28	#include <linux/mei.h>
	29
	30	#include "mei_dev.h"
2703d4b2	31	#include "client.h"
6e4cd27a TW	32	#include "hw-me-regs.h"
6e4cd27a TW	33	#include "hw-me.h"
2703d4b2	34
2703d4b2	35	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	36	static const struct pci_device_id mei_me_pci_tbl[] = {
f5ac3c49 TW	37	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	38	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	39	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	40	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	41	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	42	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	43	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	44	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	45	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	46	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
	48
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	50	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	55	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	56	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	57	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
	58
	59	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	60	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
	63
	64	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
	65	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
	66	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	67	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
	69	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
	71	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
	72	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
	73	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	74	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
	75	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	76	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
	77
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	79	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	80	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
	81	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
173436ba	82	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
f5ac3c49 TW	83
	84	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	85	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
	86
f7ee8ead TW	87	{MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
f7ee8ead TW	88
688cb678 TW	89	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
688cb678 TW	90
f5ac3c49 TW	91	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
f5ac3c49 TW	92	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
ac182e8a	93
1dbfe7f2	94	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
2a4ac172	95	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
1dbfe7f2	96	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_CFG)},
2a4ac172	97	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
f8f4aa68	98
efe814e9 TW	99	{MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
efe814e9 TW	100
2703d4b2 TW	101	/* required last entry */
	102	{0, }
	103	};
	104
b68301e9	105	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	106
bbd6d050	107	#ifdef CONFIG_PM
e13fa90c TW	108	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	109	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	110	#else
	111	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	112	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
bbd6d050	113	#endif /* CONFIG_PM */
e13fa90c	114
2703d4b2	115	/**
ce23139c	116	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	117	*
2703d4b2	118	* @pdev: PCI device structure
c919951d	119	* @cfg: per generation config
2703d4b2	120	*
a8605ea2	121	* Return: true if ME Interface is valid, false otherwise
2703d4b2	122	*/
b68301e9	123	static bool mei_me_quirk_probe(struct pci_dev *pdev,
c919951d	124	const struct mei_cfg *cfg)
2703d4b2	125	{
c919951d TW	126	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	127	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	128	return false;
5e6533a6 TW	129	}
5e6533a6 TW	130
2703d4b2 TW	131	return true;
2703d4b2 TW	132	}
c919951d	133
2703d4b2	134	/**
ce23139c	135	* mei_me_probe - Device Initialization Routine
2703d4b2 TW	136	*
	137	* @pdev: PCI device structure
	138	* @ent: entry in kcs_pci_tbl
	139	*
a8605ea2	140	* Return: 0 on success, <0 on failure.
2703d4b2	141	*/
b68301e9	142	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2	143	{
f5ac3c49	144	const struct mei_cfg *cfg;
2703d4b2	145	struct mei_device *dev;
52c34561	146	struct mei_me_hw *hw;
1fa55b4e	147	unsigned int irqflags;
2703d4b2 TW	148	int err;
2703d4b2 TW	149
f5ac3c49 TW	150	cfg = mei_me_get_cfg(ent->driver_data);
	151	if (!cfg)
	152	return -ENODEV;
2703d4b2	153
c919951d TW	154	if (!mei_me_quirk_probe(pdev, cfg))
c919951d TW	155	return -ENODEV;
2703d4b2	156
2703d4b2	157	/* enable pci dev */
f8a09605	158	err = pcim_enable_device(pdev);
2703d4b2 TW	159	if (err) {
	160	dev_err(&pdev->dev, "failed to enable pci device.\n");
	161	goto end;
	162	}
	163	/* set PCI host mastering */
	164	pci_set_master(pdev);
f8a09605 TW	165	/* pci request regions and mapping IO device memory for mei driver */
f8a09605 TW	166	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
2703d4b2 TW	167	if (err) {
2703d4b2 TW	168	dev_err(&pdev->dev, "failed to get pci regions.\n");
f8a09605	169	goto end;
2703d4b2	170	}
3ecfb168 TW	171
	172	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) \|\|
	173	dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
	174
	175	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	176	if (err)
	177	err = dma_set_coherent_mask(&pdev->dev,
	178	DMA_BIT_MASK(32));
	179	}
	180	if (err) {
	181	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
f8a09605	182	goto end;
3ecfb168 TW	183	}
3ecfb168 TW	184
2703d4b2	185	/* allocates and initializes the mei dev structure */
8d929d48	186	dev = mei_me_dev_init(pdev, cfg);
2703d4b2 TW	187	if (!dev) {
2703d4b2 TW	188	err = -ENOMEM;
f8a09605	189	goto end;
2703d4b2	190	}
52c34561	191	hw = to_me_hw(dev);
f8a09605 TW	192	hw->mem_addr = pcim_iomap_table(pdev)[0];
f8a09605 TW	193
2703d4b2 TW	194	pci_enable_msi(pdev);
	195
	196	/* request and enable interrupt */
1fa55b4e AU	197	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	198
	199	err = request_threaded_irq(pdev->irq,
06ecd645 TW	200	mei_me_irq_quick_handler,
06ecd645 TW	201	mei_me_irq_thread_handler,
1fa55b4e	202	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	203	if (err) {
	204	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	205	pdev->irq);
f8a09605	206	goto end;
2703d4b2 TW	207	}
2703d4b2 TW	208
c4d589be	209	if (mei_start(dev)) {
2703d4b2 TW	210	dev_err(&pdev->dev, "init hw failure.\n");
	211	err = -ENODEV;
	212	goto release_irq;
	213	}
	214
180ea05b TW	215	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	216	pm_runtime_use_autosuspend(&pdev->dev);
	217
f3d8e878	218	err = mei_register(dev, &pdev->dev);
2703d4b2	219	if (err)
1f7e489a	220	goto stop;
2703d4b2	221
2703d4b2 TW	222	pci_set_drvdata(pdev, dev);
2703d4b2 TW	223
557909e1 AU	224	/*
	225	* MEI requires to resume from runtime suspend mode
	226	* in order to perform link reset flow upon system suspend.
	227	*/
c2eac4d3	228	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
557909e1	229
e13fa90c	230	/*
b42dc063 AU	231	* ME maps runtime suspend/resume to D0i states,
	232	* hence we need to go around native PCI runtime service which
	233	* eventually brings the device into D3cold/hot state,
	234	* but the mei device cannot wake up from D3 unlike from D0i3.
	235	* To get around the PCI device native runtime pm,
	236	* ME uses runtime pm domain handlers which take precedence
	237	* over the driver's pm handlers.
	238	*/
	239	mei_me_set_pm_domain(dev);
e13fa90c	240
cc365dcf	241	if (mei_pg_is_enabled(dev)) {
180ea05b	242	pm_runtime_put_noidle(&pdev->dev);
cc365dcf TW	243	if (hw->d0i3_supported)
	244	pm_runtime_allow(&pdev->dev);
	245	}
180ea05b	246
c4e87b52	247	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	248
	249	return 0;
	250
1f7e489a AU	251	stop:
1f7e489a AU	252	mei_stop(dev);
2703d4b2	253	release_irq:
dc844b0d	254	mei_cancel_work(dev);
2703d4b2	255	mei_disable_interrupts(dev);
2703d4b2	256	free_irq(pdev->irq, dev);
2703d4b2	257	end:
2703d4b2 TW	258	dev_err(&pdev->dev, "initialization failed.\n");
	259	return err;
	260	}
	261
5c4c0106 TW	262	/**
	263	* mei_me_shutdown - Device Removal Routine
	264	*
	265	* @pdev: PCI device structure
	266	*
	267	* mei_me_shutdown is called from the reboot notifier
	268	* it's a simplified version of remove so we go down
	269	* faster.
	270	*/
	271	static void mei_me_shutdown(struct pci_dev *pdev)
	272	{
	273	struct mei_device *dev;
	274
	275	dev = pci_get_drvdata(pdev);
	276	if (!dev)
	277	return;
	278
	279	dev_dbg(&pdev->dev, "shutdown\n");
	280	mei_stop(dev);
	281
b42dc063	282	mei_me_unset_pm_domain(dev);
5c4c0106 TW	283
	284	mei_disable_interrupts(dev);
	285	free_irq(pdev->irq, dev);
	286	}
	287
2703d4b2	288	/**
ce23139c	289	* mei_me_remove - Device Removal Routine
2703d4b2 TW	290	*
	291	* @pdev: PCI device structure
	292	*
5c4c0106	293	* mei_me_remove is called by the PCI subsystem to alert the driver
2703d4b2 TW	294	* that it should release a PCI device.
2703d4b2 TW	295	*/
b68301e9	296	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	297	{
	298	struct mei_device *dev;
	299
2703d4b2 TW	300	dev = pci_get_drvdata(pdev);
	301	if (!dev)
	302	return;
	303
180ea05b TW	304	if (mei_pg_is_enabled(dev))
	305	pm_runtime_get_noresume(&pdev->dev);
	306
ed6f7ac1	307	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	308	mei_stop(dev);
2703d4b2	309
b42dc063	310	mei_me_unset_pm_domain(dev);
e13fa90c	311
2703d4b2 TW	312	mei_disable_interrupts(dev);
	313
	314	free_irq(pdev->irq, dev);
2703d4b2	315
30e53bb8	316	mei_deregister(dev);
2703d4b2	317	}
f8a09605	318
16833257	319	#ifdef CONFIG_PM_SLEEP
b68301e9	320	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	321	{
	322	struct pci_dev *pdev = to_pci_dev(device);
	323	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	324
	325	if (!dev)
	326	return -ENODEV;
2703d4b2	327
ed6f7ac1	328	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	329
7cb035d9 TW	330	mei_stop(dev);
	331
	332	mei_disable_interrupts(dev);
2703d4b2 TW	333
	334	free_irq(pdev->irq, dev);
	335	pci_disable_msi(pdev);
	336
7cb035d9	337	return 0;
2703d4b2 TW	338	}
2703d4b2 TW	339
b68301e9	340	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	341	{
	342	struct pci_dev *pdev = to_pci_dev(device);
	343	struct mei_device *dev;
1fa55b4e	344	unsigned int irqflags;
2703d4b2 TW	345	int err;
	346
	347	dev = pci_get_drvdata(pdev);
	348	if (!dev)
	349	return -ENODEV;
	350
	351	pci_enable_msi(pdev);
	352
1fa55b4e AU	353	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
1fa55b4e AU	354
2703d4b2	355	/* request and enable interrupt */
1fa55b4e	356	err = request_threaded_irq(pdev->irq,
06ecd645 TW	357	mei_me_irq_quick_handler,
06ecd645 TW	358	mei_me_irq_thread_handler,
1fa55b4e	359	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	360
	361	if (err) {
	362	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	363	pdev->irq);
	364	return err;
	365	}
	366
33ec0826 TW	367	err = mei_restart(dev);
	368	if (err)
	369	return err;
2703d4b2 TW	370
	371	/* Start timer if stopped in suspend */
	372	schedule_delayed_work(&dev->timer_work, HZ);
	373
33ec0826	374	return 0;
2703d4b2	375	}
180ea05b TW	376	#endif /* CONFIG_PM_SLEEP */
180ea05b TW	377
bbd6d050	378	#ifdef CONFIG_PM
180ea05b TW	379	static int mei_me_pm_runtime_idle(struct device *device)
	380	{
	381	struct pci_dev *pdev = to_pci_dev(device);
	382	struct mei_device *dev;
	383
	384	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
	385
	386	dev = pci_get_drvdata(pdev);
	387	if (!dev)
	388	return -ENODEV;
	389	if (mei_write_is_idle(dev))
d5d83f8a	390	pm_runtime_autosuspend(device);
180ea05b TW	391
	392	return -EBUSY;
	393	}
	394
	395	static int mei_me_pm_runtime_suspend(struct device *device)
	396	{
	397	struct pci_dev *pdev = to_pci_dev(device);
	398	struct mei_device *dev;
	399	int ret;
	400
	401	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
	402
	403	dev = pci_get_drvdata(pdev);
	404	if (!dev)
	405	return -ENODEV;
	406
	407	mutex_lock(&dev->device_lock);
	408
	409	if (mei_write_is_idle(dev))
2d1995fc	410	ret = mei_me_pg_enter_sync(dev);
180ea05b TW	411	else
	412	ret = -EAGAIN;
	413
	414	mutex_unlock(&dev->device_lock);
	415
	416	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
	417
77537ad2 AU	418	if (ret && ret != -EAGAIN)
	419	schedule_work(&dev->reset_work);
	420
180ea05b TW	421	return ret;
	422	}
	423
	424	static int mei_me_pm_runtime_resume(struct device *device)
	425	{
	426	struct pci_dev *pdev = to_pci_dev(device);
	427	struct mei_device *dev;
	428	int ret;
	429
	430	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
	431
	432	dev = pci_get_drvdata(pdev);
	433	if (!dev)
	434	return -ENODEV;
	435
	436	mutex_lock(&dev->device_lock);
	437
2d1995fc	438	ret = mei_me_pg_exit_sync(dev);
180ea05b TW	439
	440	mutex_unlock(&dev->device_lock);
	441
	442	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
	443
77537ad2 AU	444	if (ret)
	445	schedule_work(&dev->reset_work);
	446
180ea05b TW	447	return ret;
180ea05b TW	448	}
e13fa90c TW	449
e13fa90c TW	450	/**
7efceb55	451	* mei_me_set_pm_domain - fill and set pm domain structure for device
e13fa90c TW	452	*
	453	* @dev: mei_device
	454	*/
	455	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	456	{
d08b8fc0	457	struct pci_dev *pdev = to_pci_dev(dev->dev);
e13fa90c TW	458
	459	if (pdev->dev.bus && pdev->dev.bus->pm) {
	460	dev->pg_domain.ops = *pdev->dev.bus->pm;
	461
	462	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	463	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	464	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	465
989561de	466	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
e13fa90c TW	467	}
	468	}
	469
	470	/**
7efceb55	471	* mei_me_unset_pm_domain - clean pm domain structure for device
e13fa90c TW	472	*
	473	* @dev: mei_device
	474	*/
	475	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	476	{
	477	/* stop using pm callbacks if any */
989561de	478	dev_pm_domain_set(dev->dev, NULL);
e13fa90c	479	}
180ea05b	480
180ea05b TW	481	static const struct dev_pm_ops mei_me_pm_ops = {
	482	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	483	mei_me_pci_resume)
	484	SET_RUNTIME_PM_OPS(
	485	mei_me_pm_runtime_suspend,
	486	mei_me_pm_runtime_resume,
	487	mei_me_pm_runtime_idle)
	488	};
16833257	489
b68301e9	490	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	491	#else
b68301e9	492	#define MEI_ME_PM_OPS NULL
180ea05b	493	#endif /* CONFIG_PM */
2703d4b2 TW	494	/*
	495	* PCI driver structure
	496	*/
b68301e9	497	static struct pci_driver mei_me_driver = {
2703d4b2	498	.name = KBUILD_MODNAME,
b68301e9 TW	499	.id_table = mei_me_pci_tbl,
	500	.probe = mei_me_probe,
	501	.remove = mei_me_remove,
5c4c0106	502	.shutdown = mei_me_shutdown,
b68301e9	503	.driver.pm = MEI_ME_PM_OPS,
67de6bf1	504	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
2703d4b2 TW	505	};
2703d4b2 TW	506
b68301e9	507	module_pci_driver(mei_me_driver);
2703d4b2 TW	508
	509	MODULE_AUTHOR("Intel Corporation");
	510	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	511	MODULE_LICENSE("GPL v2");