[linux-2.6-block.git] / drivers / misc / mei / pci-me.c

/*
 *
 * Intel Management Engine Interface (Intel MEI) Linux driver
 * Copyright (c) 2003-2012, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/uuid.h>
#include <linux/compat.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH8_CFG)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg;
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;

	cfg = mei_me_get_cfg(ent->driver_data);
	if (!cfg)
		return -ENODEV;

	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pcim_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions and mapping IO device memory for mei driver */
	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto end;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {

		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
		if (err)
			err = dma_set_coherent_mask(&pdev->dev,
						    DMA_BIT_MASK(32));
	}
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto end;
	}

	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(pdev, cfg);
	if (!dev) {
		err = -ENOMEM;
		goto end;
	}
	hw = to_me_hw(dev);
	hw->mem_addr = pcim_iomap_table(pdev)[0];

	pci_enable_msi(pdev);

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto end;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	 * MEI requires to resume from runtime suspend mode
	 * in order to perform link reset flow upon system suspend.
	 */
	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);

	/*
	 * ME maps runtime suspend/resume to D0i states,
	 * hence we need to go around native PCI runtime service which
	 * eventually brings the device into D3cold/hot state,
	 * but the mei device cannot wake up from D3 unlike from D0i3.
	 * To get around the PCI device native runtime pm,
	 * ME uses runtime pm domain handlers which take precedence
	 * over the driver's pm handlers.
	 */
	mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev)) {
		pm_runtime_put_noidle(&pdev->dev);
		if (hw->d0i3_supported)
			pm_runtime_allow(&pdev->dev);
	}

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_shutdown - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_shutdown is called from the reboot notifier
 * it's a simplified version of remove so we go down
 * faster.
 */
static void mei_me_shutdown(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	dev_dbg(&pdev->dev, "shutdown\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_me_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	mei_me_unset_pm_domain(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);

	mei_deregister(dev);
}

#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	unsigned int irqflags;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;

	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;
	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_shutdown,
	.driver.pm = MEI_ME_PM_OPS,
	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2703d4b2 TW	1	/*
	2	*
	3	* Intel Management Engine Interface (Intel MEI) Linux driver
	4	* Copyright (c) 2003-2012, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
2703d4b2 TW	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/fs.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/fcntl.h>
2703d4b2 TW	24	#include <linux/pci.h>
2703d4b2 TW	25	#include <linux/poll.h>
2703d4b2 TW	26	#include <linux/ioctl.h>
	27	#include <linux/cdev.h>
	28	#include <linux/sched.h>
	29	#include <linux/uuid.h>
	30	#include <linux/compat.h>
	31	#include <linux/jiffies.h>
	32	#include <linux/interrupt.h>
2703d4b2	33
989561de	34	#include <linux/pm_domain.h>
180ea05b TW	35	#include <linux/pm_runtime.h>
180ea05b TW	36
2703d4b2 TW	37	#include <linux/mei.h>
	38
	39	#include "mei_dev.h"
2703d4b2	40	#include "client.h"
6e4cd27a TW	41	#include "hw-me-regs.h"
6e4cd27a TW	42	#include "hw-me.h"
2703d4b2	43
2703d4b2	44	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	45	static const struct pci_device_id mei_me_pci_tbl[] = {
f5ac3c49 TW	46	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
	48	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
	50	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
	55	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
	56	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
	57
	58	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
	59	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
	60	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
	63	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
	64	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
	65	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
	66	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
	67
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
	69	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
	71	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
	72
	73	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
	74	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
	75	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
	76	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
	77	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
	79	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
	80	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
	81	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
	82	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
	83	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
	84	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
	85	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
	86
	87	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
	88	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
	89	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
	90	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
	91	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH8_CFG)},
	92
	93	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
	94	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
	95
688cb678 TW	96	{MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
688cb678 TW	97
f5ac3c49 TW	98	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
f5ac3c49 TW	99	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
ac182e8a	100
f8f4aa68	101	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH8_CFG)},
2a4ac172	102	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
f8f4aa68	103	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH8_CFG)},
2a4ac172	104	{MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
f8f4aa68	105
2703d4b2 TW	106	/* required last entry */
	107	{0, }
	108	};
	109
b68301e9	110	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	111
bbd6d050	112	#ifdef CONFIG_PM
e13fa90c TW	113	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	114	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	115	#else
	116	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	117	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
bbd6d050	118	#endif /* CONFIG_PM */
e13fa90c	119
2703d4b2	120	/**
ce23139c	121	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	122	*
2703d4b2	123	* @pdev: PCI device structure
c919951d	124	* @cfg: per generation config
2703d4b2	125	*
a8605ea2	126	* Return: true if ME Interface is valid, false otherwise
2703d4b2	127	*/
b68301e9	128	static bool mei_me_quirk_probe(struct pci_dev *pdev,
c919951d	129	const struct mei_cfg *cfg)
2703d4b2	130	{
c919951d TW	131	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	132	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	133	return false;
5e6533a6 TW	134	}
5e6533a6 TW	135
2703d4b2 TW	136	return true;
2703d4b2 TW	137	}
c919951d	138
2703d4b2	139	/**
ce23139c	140	* mei_me_probe - Device Initialization Routine
2703d4b2 TW	141	*
	142	* @pdev: PCI device structure
	143	* @ent: entry in kcs_pci_tbl
	144	*
a8605ea2	145	* Return: 0 on success, <0 on failure.
2703d4b2	146	*/
b68301e9	147	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2	148	{
f5ac3c49	149	const struct mei_cfg *cfg;
2703d4b2	150	struct mei_device *dev;
52c34561	151	struct mei_me_hw *hw;
1fa55b4e	152	unsigned int irqflags;
2703d4b2 TW	153	int err;
2703d4b2 TW	154
f5ac3c49 TW	155	cfg = mei_me_get_cfg(ent->driver_data);
	156	if (!cfg)
	157	return -ENODEV;
2703d4b2	158
c919951d TW	159	if (!mei_me_quirk_probe(pdev, cfg))
c919951d TW	160	return -ENODEV;
2703d4b2	161
2703d4b2	162	/* enable pci dev */
f8a09605	163	err = pcim_enable_device(pdev);
2703d4b2 TW	164	if (err) {
	165	dev_err(&pdev->dev, "failed to enable pci device.\n");
	166	goto end;
	167	}
	168	/* set PCI host mastering */
	169	pci_set_master(pdev);
f8a09605 TW	170	/* pci request regions and mapping IO device memory for mei driver */
f8a09605 TW	171	err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
2703d4b2 TW	172	if (err) {
2703d4b2 TW	173	dev_err(&pdev->dev, "failed to get pci regions.\n");
f8a09605	174	goto end;
2703d4b2	175	}
3ecfb168 TW	176
	177	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) \|\|
	178	dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
	179
	180	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	181	if (err)
	182	err = dma_set_coherent_mask(&pdev->dev,
	183	DMA_BIT_MASK(32));
	184	}
	185	if (err) {
	186	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
f8a09605	187	goto end;
3ecfb168 TW	188	}
3ecfb168 TW	189
2703d4b2	190	/* allocates and initializes the mei dev structure */
8d929d48	191	dev = mei_me_dev_init(pdev, cfg);
2703d4b2 TW	192	if (!dev) {
2703d4b2 TW	193	err = -ENOMEM;
f8a09605	194	goto end;
2703d4b2	195	}
52c34561	196	hw = to_me_hw(dev);
f8a09605 TW	197	hw->mem_addr = pcim_iomap_table(pdev)[0];
f8a09605 TW	198
2703d4b2 TW	199	pci_enable_msi(pdev);
	200
	201	/* request and enable interrupt */
1fa55b4e AU	202	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	203
	204	err = request_threaded_irq(pdev->irq,
06ecd645 TW	205	mei_me_irq_quick_handler,
06ecd645 TW	206	mei_me_irq_thread_handler,
1fa55b4e	207	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	208	if (err) {
	209	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	210	pdev->irq);
f8a09605	211	goto end;
2703d4b2 TW	212	}
2703d4b2 TW	213
c4d589be	214	if (mei_start(dev)) {
2703d4b2 TW	215	dev_err(&pdev->dev, "init hw failure.\n");
	216	err = -ENODEV;
	217	goto release_irq;
	218	}
	219
180ea05b TW	220	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	221	pm_runtime_use_autosuspend(&pdev->dev);
	222
f3d8e878	223	err = mei_register(dev, &pdev->dev);
2703d4b2	224	if (err)
1f7e489a	225	goto stop;
2703d4b2	226
2703d4b2 TW	227	pci_set_drvdata(pdev, dev);
2703d4b2 TW	228
557909e1 AU	229	/*
	230	* MEI requires to resume from runtime suspend mode
	231	* in order to perform link reset flow upon system suspend.
	232	*/
c2eac4d3	233	dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
557909e1	234
e13fa90c	235	/*
b42dc063 AU	236	* ME maps runtime suspend/resume to D0i states,
	237	* hence we need to go around native PCI runtime service which
	238	* eventually brings the device into D3cold/hot state,
	239	* but the mei device cannot wake up from D3 unlike from D0i3.
	240	* To get around the PCI device native runtime pm,
	241	* ME uses runtime pm domain handlers which take precedence
	242	* over the driver's pm handlers.
	243	*/
	244	mei_me_set_pm_domain(dev);
e13fa90c	245
cc365dcf	246	if (mei_pg_is_enabled(dev)) {
180ea05b	247	pm_runtime_put_noidle(&pdev->dev);
cc365dcf TW	248	if (hw->d0i3_supported)
	249	pm_runtime_allow(&pdev->dev);
	250	}
180ea05b	251
c4e87b52	252	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	253
	254	return 0;
	255
1f7e489a AU	256	stop:
1f7e489a AU	257	mei_stop(dev);
2703d4b2	258	release_irq:
dc844b0d	259	mei_cancel_work(dev);
2703d4b2	260	mei_disable_interrupts(dev);
2703d4b2	261	free_irq(pdev->irq, dev);
2703d4b2	262	end:
2703d4b2 TW	263	dev_err(&pdev->dev, "initialization failed.\n");
	264	return err;
	265	}
	266
5c4c0106 TW	267	/**
	268	* mei_me_shutdown - Device Removal Routine
	269	*
	270	* @pdev: PCI device structure
	271	*
	272	* mei_me_shutdown is called from the reboot notifier
	273	* it's a simplified version of remove so we go down
	274	* faster.
	275	*/
	276	static void mei_me_shutdown(struct pci_dev *pdev)
	277	{
	278	struct mei_device *dev;
	279
	280	dev = pci_get_drvdata(pdev);
	281	if (!dev)
	282	return;
	283
	284	dev_dbg(&pdev->dev, "shutdown\n");
	285	mei_stop(dev);
	286
b42dc063	287	mei_me_unset_pm_domain(dev);
5c4c0106 TW	288
	289	mei_disable_interrupts(dev);
	290	free_irq(pdev->irq, dev);
	291	}
	292
2703d4b2	293	/**
ce23139c	294	* mei_me_remove - Device Removal Routine
2703d4b2 TW	295	*
	296	* @pdev: PCI device structure
	297	*
5c4c0106	298	* mei_me_remove is called by the PCI subsystem to alert the driver
2703d4b2 TW	299	* that it should release a PCI device.
2703d4b2 TW	300	*/
b68301e9	301	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	302	{
	303	struct mei_device *dev;
	304
2703d4b2 TW	305	dev = pci_get_drvdata(pdev);
	306	if (!dev)
	307	return;
	308
180ea05b TW	309	if (mei_pg_is_enabled(dev))
	310	pm_runtime_get_noresume(&pdev->dev);
	311
ed6f7ac1	312	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	313	mei_stop(dev);
2703d4b2	314
b42dc063	315	mei_me_unset_pm_domain(dev);
e13fa90c	316
2703d4b2 TW	317	mei_disable_interrupts(dev);
	318
	319	free_irq(pdev->irq, dev);
2703d4b2	320
30e53bb8	321	mei_deregister(dev);
2703d4b2	322	}
f8a09605	323
16833257	324	#ifdef CONFIG_PM_SLEEP
b68301e9	325	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	326	{
	327	struct pci_dev *pdev = to_pci_dev(device);
	328	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	329
	330	if (!dev)
	331	return -ENODEV;
2703d4b2	332
ed6f7ac1	333	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	334
7cb035d9 TW	335	mei_stop(dev);
	336
	337	mei_disable_interrupts(dev);
2703d4b2 TW	338
	339	free_irq(pdev->irq, dev);
	340	pci_disable_msi(pdev);
	341
7cb035d9	342	return 0;
2703d4b2 TW	343	}
2703d4b2 TW	344
b68301e9	345	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	346	{
	347	struct pci_dev *pdev = to_pci_dev(device);
	348	struct mei_device *dev;
1fa55b4e	349	unsigned int irqflags;
2703d4b2 TW	350	int err;
	351
	352	dev = pci_get_drvdata(pdev);
	353	if (!dev)
	354	return -ENODEV;
	355
	356	pci_enable_msi(pdev);
	357
1fa55b4e AU	358	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
1fa55b4e AU	359
2703d4b2	360	/* request and enable interrupt */
1fa55b4e	361	err = request_threaded_irq(pdev->irq,
06ecd645 TW	362	mei_me_irq_quick_handler,
06ecd645 TW	363	mei_me_irq_thread_handler,
1fa55b4e	364	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	365
	366	if (err) {
	367	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	368	pdev->irq);
	369	return err;
	370	}
	371
33ec0826 TW	372	err = mei_restart(dev);
	373	if (err)
	374	return err;
2703d4b2 TW	375
	376	/* Start timer if stopped in suspend */
	377	schedule_delayed_work(&dev->timer_work, HZ);
	378
33ec0826	379	return 0;
2703d4b2	380	}
180ea05b TW	381	#endif /* CONFIG_PM_SLEEP */
180ea05b TW	382
bbd6d050	383	#ifdef CONFIG_PM
180ea05b TW	384	static int mei_me_pm_runtime_idle(struct device *device)
	385	{
	386	struct pci_dev *pdev = to_pci_dev(device);
	387	struct mei_device *dev;
	388
	389	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
	390
	391	dev = pci_get_drvdata(pdev);
	392	if (!dev)
	393	return -ENODEV;
	394	if (mei_write_is_idle(dev))
d5d83f8a	395	pm_runtime_autosuspend(device);
180ea05b TW	396
	397	return -EBUSY;
	398	}
	399
	400	static int mei_me_pm_runtime_suspend(struct device *device)
	401	{
	402	struct pci_dev *pdev = to_pci_dev(device);
	403	struct mei_device *dev;
	404	int ret;
	405
	406	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
	407
	408	dev = pci_get_drvdata(pdev);
	409	if (!dev)
	410	return -ENODEV;
	411
	412	mutex_lock(&dev->device_lock);
	413
	414	if (mei_write_is_idle(dev))
2d1995fc	415	ret = mei_me_pg_enter_sync(dev);
180ea05b TW	416	else
	417	ret = -EAGAIN;
	418
	419	mutex_unlock(&dev->device_lock);
	420
	421	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
	422
77537ad2 AU	423	if (ret && ret != -EAGAIN)
	424	schedule_work(&dev->reset_work);
	425
180ea05b TW	426	return ret;
	427	}
	428
	429	static int mei_me_pm_runtime_resume(struct device *device)
	430	{
	431	struct pci_dev *pdev = to_pci_dev(device);
	432	struct mei_device *dev;
	433	int ret;
	434
	435	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
	436
	437	dev = pci_get_drvdata(pdev);
	438	if (!dev)
	439	return -ENODEV;
	440
	441	mutex_lock(&dev->device_lock);
	442
2d1995fc	443	ret = mei_me_pg_exit_sync(dev);
180ea05b TW	444
	445	mutex_unlock(&dev->device_lock);
	446
	447	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
	448
77537ad2 AU	449	if (ret)
	450	schedule_work(&dev->reset_work);
	451
180ea05b TW	452	return ret;
180ea05b TW	453	}
e13fa90c TW	454
e13fa90c TW	455	/**
7efceb55	456	* mei_me_set_pm_domain - fill and set pm domain structure for device
e13fa90c TW	457	*
	458	* @dev: mei_device
	459	*/
	460	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	461	{
d08b8fc0	462	struct pci_dev *pdev = to_pci_dev(dev->dev);
e13fa90c TW	463
	464	if (pdev->dev.bus && pdev->dev.bus->pm) {
	465	dev->pg_domain.ops = *pdev->dev.bus->pm;
	466
	467	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	468	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	469	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	470
989561de	471	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
e13fa90c TW	472	}
	473	}
	474
	475	/**
7efceb55	476	* mei_me_unset_pm_domain - clean pm domain structure for device
e13fa90c TW	477	*
	478	* @dev: mei_device
	479	*/
	480	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	481	{
	482	/* stop using pm callbacks if any */
989561de	483	dev_pm_domain_set(dev->dev, NULL);
e13fa90c	484	}
180ea05b	485
180ea05b TW	486	static const struct dev_pm_ops mei_me_pm_ops = {
	487	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	488	mei_me_pci_resume)
	489	SET_RUNTIME_PM_OPS(
	490	mei_me_pm_runtime_suspend,
	491	mei_me_pm_runtime_resume,
	492	mei_me_pm_runtime_idle)
	493	};
16833257	494
b68301e9	495	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	496	#else
b68301e9	497	#define MEI_ME_PM_OPS NULL
180ea05b	498	#endif /* CONFIG_PM */
2703d4b2 TW	499	/*
	500	* PCI driver structure
	501	*/
b68301e9	502	static struct pci_driver mei_me_driver = {
2703d4b2	503	.name = KBUILD_MODNAME,
b68301e9 TW	504	.id_table = mei_me_pci_tbl,
	505	.probe = mei_me_probe,
	506	.remove = mei_me_remove,
5c4c0106	507	.shutdown = mei_me_shutdown,
b68301e9	508	.driver.pm = MEI_ME_PM_OPS,
67de6bf1	509	.driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
2703d4b2 TW	510	};
2703d4b2 TW	511
b68301e9	512	module_pci_driver(mei_me_driver);
2703d4b2 TW	513
	514	MODULE_AUTHOR("Intel Corporation");
	515	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	516	MODULE_LICENSE("GPL v2");