Commit | Line | Data |
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9fff0425 | 1 | // SPDX-License-Identifier: GPL-2.0 |
2703d4b2 | 2 | /* |
95953618 | 3 | * Copyright (c) 2003-2022, Intel Corporation. All rights reserved. |
2703d4b2 | 4 | * Intel Management Engine Interface (Intel MEI) Linux driver |
2703d4b2 | 5 | */ |
9fff0425 | 6 | |
2703d4b2 | 7 | #include <linux/module.h> |
2703d4b2 TW |
8 | #include <linux/kernel.h> |
9 | #include <linux/device.h> | |
2703d4b2 TW |
10 | #include <linux/errno.h> |
11 | #include <linux/types.h> | |
2703d4b2 | 12 | #include <linux/pci.h> |
515a2f50 | 13 | #include <linux/dma-mapping.h> |
2703d4b2 | 14 | #include <linux/sched.h> |
2703d4b2 | 15 | #include <linux/interrupt.h> |
2703d4b2 | 16 | |
989561de | 17 | #include <linux/pm_domain.h> |
180ea05b TW |
18 | #include <linux/pm_runtime.h> |
19 | ||
2703d4b2 TW |
20 | #include <linux/mei.h> |
21 | ||
22 | #include "mei_dev.h" | |
2703d4b2 | 23 | #include "client.h" |
6e4cd27a TW |
24 | #include "hw-me-regs.h" |
25 | #include "hw-me.h" | |
2703d4b2 | 26 | |
2703d4b2 | 27 | /* mei_pci_tbl - PCI Device ID Table */ |
a05f8f86 | 28 | static const struct pci_device_id mei_me_pci_tbl[] = { |
f5ac3c49 TW |
29 | {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)}, |
30 | {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)}, | |
31 | {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)}, | |
32 | {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)}, | |
33 | {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)}, | |
34 | {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)}, | |
35 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)}, | |
36 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)}, | |
37 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)}, | |
38 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)}, | |
39 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)}, | |
40 | ||
41 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)}, | |
42 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)}, | |
43 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)}, | |
44 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)}, | |
45 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)}, | |
46 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)}, | |
47 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)}, | |
48 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)}, | |
49 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)}, | |
50 | ||
51 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)}, | |
52 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)}, | |
53 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)}, | |
54 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)}, | |
55 | ||
f8204f0d AU |
56 | {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)}, |
57 | {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)}, | |
f5ac3c49 TW |
58 | {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)}, |
59 | {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)}, | |
f8204f0d AU |
60 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)}, |
61 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)}, | |
62 | {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)}, | |
f76d77f5 TW |
63 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)}, |
64 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)}, | |
f5ac3c49 | 65 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)}, |
f76d77f5 | 66 | {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)}, |
f5ac3c49 TW |
67 | {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)}, |
68 | {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)}, | |
69 | ||
70 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)}, | |
71 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)}, | |
2f79d3d1 | 72 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
f76d77f5 TW |
73 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)}, |
74 | {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)}, | |
75 | {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)}, | |
f5ac3c49 TW |
76 | |
77 | {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)}, | |
78 | {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)}, | |
79 | ||
f7ee8ead TW |
80 | {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)}, |
81 | ||
688cb678 TW |
82 | {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)}, |
83 | ||
f5ac3c49 TW |
84 | {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)}, |
85 | {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)}, | |
4afc339e | 86 | {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)}, |
ac182e8a | 87 | |
1dbfe7f2 | 88 | {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)}, |
2f79d3d1 | 89 | {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
f76d77f5 | 90 | {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)}, |
2f79d3d1 | 91 | {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)}, |
f8f4aa68 | 92 | |
4d86dfd3 | 93 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)}, |
2f79d3d1 | 94 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
82b29b9f | 95 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)}, |
559e575a | 96 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)}, |
2f79d3d1 | 97 | {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)}, |
4d86dfd3 | 98 | |
efe814e9 | 99 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)}, |
75c10c5e | 100 | {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)}, |
efe814e9 | 101 | |
52f6efdf | 102 | {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)}, |
8c289ea0 | 103 | {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)}, |
587f1740 | 104 | |
0db4a15d TW |
105 | {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)}, |
106 | ||
52f6efdf | 107 | {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)}, |
1be8624a AU |
108 | {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)}, |
109 | ||
99397d33 AU |
110 | {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)}, |
111 | ||
372726cb TW |
112 | {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)}, |
113 | ||
f7545efa | 114 | {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)}, |
930c922a | 115 | {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)}, |
0df74278 | 116 | {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)}, |
7bbbd084 | 117 | {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)}, |
f7545efa | 118 | |
0dc04112 | 119 | {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_SPS_CFG)}, |
3ed8c7d3 | 120 | |
0c4d6826 | 121 | {MEI_PCI_DEVICE(MEI_DEV_ID_MTL_M, MEI_ME_PCH15_CFG)}, |
7a9b9012 | 122 | {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_S, MEI_ME_PCH15_CFG)}, |
8436f258 | 123 | {MEI_PCI_DEVICE(MEI_DEV_ID_ARL_H, MEI_ME_PCH15_CFG)}, |
0c4d6826 | 124 | |
2703d4b2 TW |
125 | /* required last entry */ |
126 | {0, } | |
127 | }; | |
128 | ||
b68301e9 | 129 | MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl); |
2703d4b2 | 130 | |
bbd6d050 | 131 | #ifdef CONFIG_PM |
e13fa90c TW |
132 | static inline void mei_me_set_pm_domain(struct mei_device *dev); |
133 | static inline void mei_me_unset_pm_domain(struct mei_device *dev); | |
134 | #else | |
135 | static inline void mei_me_set_pm_domain(struct mei_device *dev) {} | |
136 | static inline void mei_me_unset_pm_domain(struct mei_device *dev) {} | |
bbd6d050 | 137 | #endif /* CONFIG_PM */ |
e13fa90c | 138 | |
261e071a TW |
139 | static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val) |
140 | { | |
141 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
142 | ||
143 | return pci_read_config_dword(pdev, where, val); | |
144 | } | |
145 | ||
2703d4b2 | 146 | /** |
ce23139c | 147 | * mei_me_quirk_probe - probe for devices that doesn't valid ME interface |
393b148f | 148 | * |
2703d4b2 | 149 | * @pdev: PCI device structure |
c919951d | 150 | * @cfg: per generation config |
2703d4b2 | 151 | * |
a8605ea2 | 152 | * Return: true if ME Interface is valid, false otherwise |
2703d4b2 | 153 | */ |
b68301e9 | 154 | static bool mei_me_quirk_probe(struct pci_dev *pdev, |
c919951d | 155 | const struct mei_cfg *cfg) |
2703d4b2 | 156 | { |
c919951d TW |
157 | if (cfg->quirk_probe && cfg->quirk_probe(pdev)) { |
158 | dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n"); | |
159 | return false; | |
5e6533a6 TW |
160 | } |
161 | ||
2703d4b2 TW |
162 | return true; |
163 | } | |
c919951d | 164 | |
2703d4b2 | 165 | /** |
ce23139c | 166 | * mei_me_probe - Device Initialization Routine |
2703d4b2 TW |
167 | * |
168 | * @pdev: PCI device structure | |
169 | * @ent: entry in kcs_pci_tbl | |
170 | * | |
a8605ea2 | 171 | * Return: 0 on success, <0 on failure. |
2703d4b2 | 172 | */ |
b68301e9 | 173 | static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
2703d4b2 | 174 | { |
f5ac3c49 | 175 | const struct mei_cfg *cfg; |
2703d4b2 | 176 | struct mei_device *dev; |
52c34561 | 177 | struct mei_me_hw *hw; |
1fa55b4e | 178 | unsigned int irqflags; |
2703d4b2 TW |
179 | int err; |
180 | ||
f5ac3c49 TW |
181 | cfg = mei_me_get_cfg(ent->driver_data); |
182 | if (!cfg) | |
183 | return -ENODEV; | |
2703d4b2 | 184 | |
c919951d TW |
185 | if (!mei_me_quirk_probe(pdev, cfg)) |
186 | return -ENODEV; | |
2703d4b2 | 187 | |
2703d4b2 | 188 | /* enable pci dev */ |
f8a09605 | 189 | err = pcim_enable_device(pdev); |
2703d4b2 TW |
190 | if (err) { |
191 | dev_err(&pdev->dev, "failed to enable pci device.\n"); | |
192 | goto end; | |
193 | } | |
194 | /* set PCI host mastering */ | |
195 | pci_set_master(pdev); | |
f8a09605 TW |
196 | /* pci request regions and mapping IO device memory for mei driver */ |
197 | err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME); | |
2703d4b2 TW |
198 | if (err) { |
199 | dev_err(&pdev->dev, "failed to get pci regions.\n"); | |
f8a09605 | 200 | goto end; |
2703d4b2 | 201 | } |
3ecfb168 | 202 | |
515a2f50 | 203 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
3ecfb168 TW |
204 | if (err) { |
205 | dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); | |
f8a09605 | 206 | goto end; |
3ecfb168 TW |
207 | } |
208 | ||
2703d4b2 | 209 | /* allocates and initializes the mei dev structure */ |
95953618 | 210 | dev = mei_me_dev_init(&pdev->dev, cfg, false); |
2703d4b2 TW |
211 | if (!dev) { |
212 | err = -ENOMEM; | |
f8a09605 | 213 | goto end; |
2703d4b2 | 214 | } |
52c34561 | 215 | hw = to_me_hw(dev); |
f8a09605 | 216 | hw->mem_addr = pcim_iomap_table(pdev)[0]; |
261e071a | 217 | hw->read_fws = mei_me_read_fws; |
f8a09605 | 218 | |
2703d4b2 TW |
219 | pci_enable_msi(pdev); |
220 | ||
fec874a8 BL |
221 | hw->irq = pdev->irq; |
222 | ||
2703d4b2 | 223 | /* request and enable interrupt */ |
1fa55b4e AU |
224 | irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; |
225 | ||
226 | err = request_threaded_irq(pdev->irq, | |
06ecd645 TW |
227 | mei_me_irq_quick_handler, |
228 | mei_me_irq_thread_handler, | |
1fa55b4e | 229 | irqflags, KBUILD_MODNAME, dev); |
2703d4b2 TW |
230 | if (err) { |
231 | dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n", | |
232 | pdev->irq); | |
f8a09605 | 233 | goto end; |
2703d4b2 TW |
234 | } |
235 | ||
c4d589be | 236 | if (mei_start(dev)) { |
2703d4b2 TW |
237 | dev_err(&pdev->dev, "init hw failure.\n"); |
238 | err = -ENODEV; | |
239 | goto release_irq; | |
240 | } | |
241 | ||
180ea05b TW |
242 | pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT); |
243 | pm_runtime_use_autosuspend(&pdev->dev); | |
244 | ||
f3d8e878 | 245 | err = mei_register(dev, &pdev->dev); |
2703d4b2 | 246 | if (err) |
1f7e489a | 247 | goto stop; |
2703d4b2 | 248 | |
2703d4b2 TW |
249 | pci_set_drvdata(pdev, dev); |
250 | ||
557909e1 AU |
251 | /* |
252 | * MEI requires to resume from runtime suspend mode | |
253 | * in order to perform link reset flow upon system suspend. | |
254 | */ | |
e0751556 | 255 | dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); |
557909e1 | 256 | |
e13fa90c | 257 | /* |
b42dc063 AU |
258 | * ME maps runtime suspend/resume to D0i states, |
259 | * hence we need to go around native PCI runtime service which | |
260 | * eventually brings the device into D3cold/hot state, | |
261 | * but the mei device cannot wake up from D3 unlike from D0i3. | |
262 | * To get around the PCI device native runtime pm, | |
263 | * ME uses runtime pm domain handlers which take precedence | |
264 | * over the driver's pm handlers. | |
265 | */ | |
266 | mei_me_set_pm_domain(dev); | |
e13fa90c | 267 | |
cc365dcf | 268 | if (mei_pg_is_enabled(dev)) { |
180ea05b | 269 | pm_runtime_put_noidle(&pdev->dev); |
cc365dcf TW |
270 | if (hw->d0i3_supported) |
271 | pm_runtime_allow(&pdev->dev); | |
272 | } | |
180ea05b | 273 | |
c4e87b52 | 274 | dev_dbg(&pdev->dev, "initialization successful.\n"); |
2703d4b2 TW |
275 | |
276 | return 0; | |
277 | ||
1f7e489a AU |
278 | stop: |
279 | mei_stop(dev); | |
2703d4b2 | 280 | release_irq: |
dc844b0d | 281 | mei_cancel_work(dev); |
2703d4b2 | 282 | mei_disable_interrupts(dev); |
2703d4b2 | 283 | free_irq(pdev->irq, dev); |
2703d4b2 | 284 | end: |
2703d4b2 TW |
285 | dev_err(&pdev->dev, "initialization failed.\n"); |
286 | return err; | |
287 | } | |
288 | ||
5c4c0106 TW |
289 | /** |
290 | * mei_me_shutdown - Device Removal Routine | |
291 | * | |
292 | * @pdev: PCI device structure | |
293 | * | |
294 | * mei_me_shutdown is called from the reboot notifier | |
295 | * it's a simplified version of remove so we go down | |
296 | * faster. | |
297 | */ | |
298 | static void mei_me_shutdown(struct pci_dev *pdev) | |
299 | { | |
e37db17d | 300 | struct mei_device *dev = pci_get_drvdata(pdev); |
5c4c0106 TW |
301 | |
302 | dev_dbg(&pdev->dev, "shutdown\n"); | |
303 | mei_stop(dev); | |
304 | ||
b42dc063 | 305 | mei_me_unset_pm_domain(dev); |
5c4c0106 TW |
306 | |
307 | mei_disable_interrupts(dev); | |
308 | free_irq(pdev->irq, dev); | |
309 | } | |
310 | ||
2703d4b2 | 311 | /** |
ce23139c | 312 | * mei_me_remove - Device Removal Routine |
2703d4b2 TW |
313 | * |
314 | * @pdev: PCI device structure | |
315 | * | |
5c4c0106 | 316 | * mei_me_remove is called by the PCI subsystem to alert the driver |
2703d4b2 TW |
317 | * that it should release a PCI device. |
318 | */ | |
b68301e9 | 319 | static void mei_me_remove(struct pci_dev *pdev) |
2703d4b2 | 320 | { |
e37db17d | 321 | struct mei_device *dev = pci_get_drvdata(pdev); |
2703d4b2 | 322 | |
180ea05b TW |
323 | if (mei_pg_is_enabled(dev)) |
324 | pm_runtime_get_noresume(&pdev->dev); | |
325 | ||
ed6f7ac1 | 326 | dev_dbg(&pdev->dev, "stop\n"); |
7cb035d9 | 327 | mei_stop(dev); |
2703d4b2 | 328 | |
b42dc063 | 329 | mei_me_unset_pm_domain(dev); |
e13fa90c | 330 | |
2703d4b2 TW |
331 | mei_disable_interrupts(dev); |
332 | ||
333 | free_irq(pdev->irq, dev); | |
2703d4b2 | 334 | |
30e53bb8 | 335 | mei_deregister(dev); |
2703d4b2 | 336 | } |
f8a09605 | 337 | |
16833257 | 338 | #ifdef CONFIG_PM_SLEEP |
907deab2 AU |
339 | static int mei_me_pci_prepare(struct device *device) |
340 | { | |
341 | pm_runtime_resume(device); | |
342 | return 0; | |
343 | } | |
344 | ||
b68301e9 | 345 | static int mei_me_pci_suspend(struct device *device) |
2703d4b2 TW |
346 | { |
347 | struct pci_dev *pdev = to_pci_dev(device); | |
348 | struct mei_device *dev = pci_get_drvdata(pdev); | |
2703d4b2 | 349 | |
ed6f7ac1 | 350 | dev_dbg(&pdev->dev, "suspend\n"); |
2703d4b2 | 351 | |
7cb035d9 TW |
352 | mei_stop(dev); |
353 | ||
354 | mei_disable_interrupts(dev); | |
2703d4b2 TW |
355 | |
356 | free_irq(pdev->irq, dev); | |
357 | pci_disable_msi(pdev); | |
358 | ||
7cb035d9 | 359 | return 0; |
2703d4b2 TW |
360 | } |
361 | ||
b68301e9 | 362 | static int mei_me_pci_resume(struct device *device) |
2703d4b2 TW |
363 | { |
364 | struct pci_dev *pdev = to_pci_dev(device); | |
e37db17d | 365 | struct mei_device *dev = pci_get_drvdata(pdev); |
1fa55b4e | 366 | unsigned int irqflags; |
2703d4b2 TW |
367 | int err; |
368 | ||
2703d4b2 TW |
369 | pci_enable_msi(pdev); |
370 | ||
1fa55b4e AU |
371 | irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED; |
372 | ||
2703d4b2 | 373 | /* request and enable interrupt */ |
1fa55b4e | 374 | err = request_threaded_irq(pdev->irq, |
06ecd645 TW |
375 | mei_me_irq_quick_handler, |
376 | mei_me_irq_thread_handler, | |
1fa55b4e | 377 | irqflags, KBUILD_MODNAME, dev); |
2703d4b2 TW |
378 | |
379 | if (err) { | |
380 | dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n", | |
381 | pdev->irq); | |
382 | return err; | |
383 | } | |
384 | ||
33ec0826 TW |
385 | err = mei_restart(dev); |
386 | if (err) | |
387 | return err; | |
2703d4b2 TW |
388 | |
389 | /* Start timer if stopped in suspend */ | |
390 | schedule_delayed_work(&dev->timer_work, HZ); | |
391 | ||
33ec0826 | 392 | return 0; |
2703d4b2 | 393 | } |
907deab2 AU |
394 | |
395 | static void mei_me_pci_complete(struct device *device) | |
396 | { | |
397 | pm_runtime_suspend(device); | |
398 | } | |
399 | #else /* CONFIG_PM_SLEEP */ | |
400 | ||
401 | #define mei_me_pci_prepare NULL | |
402 | #define mei_me_pci_complete NULL | |
403 | ||
404 | #endif /* !CONFIG_PM_SLEEP */ | |
180ea05b | 405 | |
bbd6d050 | 406 | #ifdef CONFIG_PM |
180ea05b TW |
407 | static int mei_me_pm_runtime_idle(struct device *device) |
408 | { | |
e37db17d | 409 | struct mei_device *dev = dev_get_drvdata(device); |
180ea05b | 410 | |
ab81f3f3 | 411 | dev_dbg(device, "rpm: me: runtime_idle\n"); |
180ea05b | 412 | |
180ea05b | 413 | if (mei_write_is_idle(dev)) |
d5d83f8a | 414 | pm_runtime_autosuspend(device); |
180ea05b TW |
415 | |
416 | return -EBUSY; | |
417 | } | |
418 | ||
419 | static int mei_me_pm_runtime_suspend(struct device *device) | |
420 | { | |
e37db17d | 421 | struct mei_device *dev = dev_get_drvdata(device); |
180ea05b TW |
422 | int ret; |
423 | ||
ab81f3f3 | 424 | dev_dbg(device, "rpm: me: runtime suspend\n"); |
180ea05b | 425 | |
180ea05b TW |
426 | mutex_lock(&dev->device_lock); |
427 | ||
428 | if (mei_write_is_idle(dev)) | |
2d1995fc | 429 | ret = mei_me_pg_enter_sync(dev); |
180ea05b TW |
430 | else |
431 | ret = -EAGAIN; | |
432 | ||
433 | mutex_unlock(&dev->device_lock); | |
434 | ||
ab81f3f3 | 435 | dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret); |
180ea05b | 436 | |
77537ad2 AU |
437 | if (ret && ret != -EAGAIN) |
438 | schedule_work(&dev->reset_work); | |
439 | ||
180ea05b TW |
440 | return ret; |
441 | } | |
442 | ||
443 | static int mei_me_pm_runtime_resume(struct device *device) | |
444 | { | |
e37db17d | 445 | struct mei_device *dev = dev_get_drvdata(device); |
180ea05b TW |
446 | int ret; |
447 | ||
ab81f3f3 | 448 | dev_dbg(device, "rpm: me: runtime resume\n"); |
180ea05b | 449 | |
180ea05b TW |
450 | mutex_lock(&dev->device_lock); |
451 | ||
2d1995fc | 452 | ret = mei_me_pg_exit_sync(dev); |
180ea05b TW |
453 | |
454 | mutex_unlock(&dev->device_lock); | |
455 | ||
ab81f3f3 | 456 | dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret); |
180ea05b | 457 | |
77537ad2 AU |
458 | if (ret) |
459 | schedule_work(&dev->reset_work); | |
460 | ||
180ea05b TW |
461 | return ret; |
462 | } | |
e13fa90c TW |
463 | |
464 | /** | |
7efceb55 | 465 | * mei_me_set_pm_domain - fill and set pm domain structure for device |
e13fa90c TW |
466 | * |
467 | * @dev: mei_device | |
468 | */ | |
469 | static inline void mei_me_set_pm_domain(struct mei_device *dev) | |
470 | { | |
d08b8fc0 | 471 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
e13fa90c TW |
472 | |
473 | if (pdev->dev.bus && pdev->dev.bus->pm) { | |
474 | dev->pg_domain.ops = *pdev->dev.bus->pm; | |
475 | ||
476 | dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend; | |
477 | dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume; | |
478 | dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle; | |
479 | ||
989561de | 480 | dev_pm_domain_set(&pdev->dev, &dev->pg_domain); |
e13fa90c TW |
481 | } |
482 | } | |
483 | ||
484 | /** | |
7efceb55 | 485 | * mei_me_unset_pm_domain - clean pm domain structure for device |
e13fa90c TW |
486 | * |
487 | * @dev: mei_device | |
488 | */ | |
489 | static inline void mei_me_unset_pm_domain(struct mei_device *dev) | |
490 | { | |
491 | /* stop using pm callbacks if any */ | |
989561de | 492 | dev_pm_domain_set(dev->dev, NULL); |
e13fa90c | 493 | } |
180ea05b | 494 | |
180ea05b | 495 | static const struct dev_pm_ops mei_me_pm_ops = { |
907deab2 AU |
496 | .prepare = mei_me_pci_prepare, |
497 | .complete = mei_me_pci_complete, | |
180ea05b TW |
498 | SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend, |
499 | mei_me_pci_resume) | |
500 | SET_RUNTIME_PM_OPS( | |
501 | mei_me_pm_runtime_suspend, | |
502 | mei_me_pm_runtime_resume, | |
503 | mei_me_pm_runtime_idle) | |
504 | }; | |
16833257 | 505 | |
b68301e9 | 506 | #define MEI_ME_PM_OPS (&mei_me_pm_ops) |
2703d4b2 | 507 | #else |
b68301e9 | 508 | #define MEI_ME_PM_OPS NULL |
180ea05b | 509 | #endif /* CONFIG_PM */ |
2703d4b2 TW |
510 | /* |
511 | * PCI driver structure | |
512 | */ | |
b68301e9 | 513 | static struct pci_driver mei_me_driver = { |
2703d4b2 | 514 | .name = KBUILD_MODNAME, |
b68301e9 TW |
515 | .id_table = mei_me_pci_tbl, |
516 | .probe = mei_me_probe, | |
517 | .remove = mei_me_remove, | |
5c4c0106 | 518 | .shutdown = mei_me_shutdown, |
b68301e9 | 519 | .driver.pm = MEI_ME_PM_OPS, |
67de6bf1 | 520 | .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS, |
2703d4b2 TW |
521 | }; |
522 | ||
b68301e9 | 523 | module_pci_driver(mei_me_driver); |
2703d4b2 TW |
524 | |
525 | MODULE_AUTHOR("Intel Corporation"); | |
526 | MODULE_DESCRIPTION("Intel(R) Management Engine Interface"); | |
527 | MODULE_LICENSE("GPL v2"); |