[linux-2.6-block.git] / drivers / misc / mei / pci-me.c

/*
 *
 * Intel Management Engine Interface (Intel MEI) Linux driver
 * Copyright (c) 2003-2012, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/pci.h>
#include <linux/poll.h>
#include <linux/ioctl.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/uuid.h>
#include <linux/compat.h>
#include <linux/jiffies.h>
#include <linux/interrupt.h>

#include <linux/pm_domain.h>
#include <linux/pm_runtime.h>

#include <linux/mei.h>

#include "mei_dev.h"
#include "client.h"
#include "hw-me-regs.h"
#include "hw-me.h"

/* mei_pci_tbl - PCI Device ID Table */
static const struct pci_device_id mei_me_pci_tbl[] = {
	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},

	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, mei_me_pch8_cfg)},
	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, mei_me_pch8_cfg)},

	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);

#ifdef CONFIG_PM
static inline void mei_me_set_pm_domain(struct mei_device *dev);
static inline void mei_me_unset_pm_domain(struct mei_device *dev);
#else
static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
#endif /* CONFIG_PM */

/**
 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 *
 * @pdev: PCI device structure
 * @cfg: per generation config
 *
 * Return: true if ME Interface is valid, false otherwise
 */
static bool mei_me_quirk_probe(struct pci_dev *pdev,
				const struct mei_cfg *cfg)
{
	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
		dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
		return false;
	}

	return true;
}

/**
 * mei_me_probe - Device Initialization Routine
 *
 * @pdev: PCI device structure
 * @ent: entry in kcs_pci_tbl
 *
 * Return: 0 on success, <0 on failure.
 */
static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct mei_cfg *cfg = (struct mei_cfg *)(ent->driver_data);
	struct mei_device *dev;
	struct mei_me_hw *hw;
	unsigned int irqflags;
	int err;


	if (!mei_me_quirk_probe(pdev, cfg))
		return -ENODEV;

	/* enable pci dev */
	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "failed to enable pci device.\n");
		goto end;
	}
	/* set PCI host mastering  */
	pci_set_master(pdev);
	/* pci request regions for mei driver */
	err = pci_request_regions(pdev, KBUILD_MODNAME);
	if (err) {
		dev_err(&pdev->dev, "failed to get pci regions.\n");
		goto disable_device;
	}

	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
	    dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {

		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
		if (err)
			err = dma_set_coherent_mask(&pdev->dev,
						    DMA_BIT_MASK(32));
	}
	if (err) {
		dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
		goto release_regions;
	}


	/* allocates and initializes the mei dev structure */
	dev = mei_me_dev_init(pdev, cfg);
	if (!dev) {
		err = -ENOMEM;
		goto release_regions;
	}
	hw = to_me_hw(dev);
	/* mapping  IO device memory */
	hw->mem_addr = pci_iomap(pdev, 0, 0);
	if (!hw->mem_addr) {
		dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
		err = -ENOMEM;
		goto free_device;
	}
	pci_enable_msi(pdev);

	 /* request and enable interrupt */
	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);
	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
		       pdev->irq);
		goto disable_msi;
	}

	if (mei_start(dev)) {
		dev_err(&pdev->dev, "init hw failure.\n");
		err = -ENODEV;
		goto release_irq;
	}

	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	pm_runtime_use_autosuspend(&pdev->dev);

	err = mei_register(dev, &pdev->dev);
	if (err)
		goto stop;

	pci_set_drvdata(pdev, dev);

	/*
	* For not wake-able HW runtime pm framework
	* can't be used on pci device level.
	* Use domain runtime pm callbacks instead.
	*/
	if (!pci_dev_run_wake(pdev))
		mei_me_set_pm_domain(dev);

	if (mei_pg_is_enabled(dev))
		pm_runtime_put_noidle(&pdev->dev);

	dev_dbg(&pdev->dev, "initialization successful.\n");

	return 0;

stop:
	mei_stop(dev);
release_irq:
	mei_cancel_work(dev);
	mei_disable_interrupts(dev);
	free_irq(pdev->irq, dev);
disable_msi:
	pci_disable_msi(pdev);
	pci_iounmap(pdev, hw->mem_addr);
free_device:
	kfree(dev);
release_regions:
	pci_release_regions(pdev);
disable_device:
	pci_disable_device(pdev);
end:
	dev_err(&pdev->dev, "initialization failed.\n");
	return err;
}

/**
 * mei_me_remove - Device Removal Routine
 *
 * @pdev: PCI device structure
 *
 * mei_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.
 */
static void mei_me_remove(struct pci_dev *pdev)
{
	struct mei_device *dev;
	struct mei_me_hw *hw;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return;

	if (mei_pg_is_enabled(dev))
		pm_runtime_get_noresume(&pdev->dev);

	hw = to_me_hw(dev);


	dev_dbg(&pdev->dev, "stop\n");
	mei_stop(dev);

	if (!pci_dev_run_wake(pdev))
		mei_me_unset_pm_domain(dev);

	/* disable interrupts */
	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	if (hw->mem_addr)
		pci_iounmap(pdev, hw->mem_addr);

	mei_deregister(dev);

	kfree(dev);

	pci_release_regions(pdev);
	pci_disable_device(pdev);


}
#ifdef CONFIG_PM_SLEEP
static int mei_me_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev = pci_get_drvdata(pdev);

	if (!dev)
		return -ENODEV;

	dev_dbg(&pdev->dev, "suspend\n");

	mei_stop(dev);

	mei_disable_interrupts(dev);

	free_irq(pdev->irq, dev);
	pci_disable_msi(pdev);

	return 0;
}

static int mei_me_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	unsigned int irqflags;
	int err;

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	pci_enable_msi(pdev);

	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;

	/* request and enable interrupt */
	err = request_threaded_irq(pdev->irq,
			mei_me_irq_quick_handler,
			mei_me_irq_thread_handler,
			irqflags, KBUILD_MODNAME, dev);

	if (err) {
		dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
				pdev->irq);
		return err;
	}

	err = mei_restart(dev);
	if (err)
		return err;

	/* Start timer if stopped in suspend */
	schedule_delayed_work(&dev->timer_work, HZ);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_PM
static int mei_me_pm_runtime_idle(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;

	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;
	if (mei_write_is_idle(dev))
		pm_runtime_autosuspend(device);

	return -EBUSY;
}

static int mei_me_pm_runtime_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	if (mei_write_is_idle(dev))
		ret = mei_me_pg_enter_sync(dev);
	else
		ret = -EAGAIN;

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);

	if (ret && ret != -EAGAIN)
		schedule_work(&dev->reset_work);

	return ret;
}

static int mei_me_pm_runtime_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct mei_device *dev;
	int ret;

	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");

	dev = pci_get_drvdata(pdev);
	if (!dev)
		return -ENODEV;

	mutex_lock(&dev->device_lock);

	ret = mei_me_pg_exit_sync(dev);

	mutex_unlock(&dev->device_lock);

	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);

	if (ret)
		schedule_work(&dev->reset_work);

	return ret;
}

/**
 * mei_me_set_pm_domain - fill and set pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_set_pm_domain(struct mei_device *dev)
{
	struct pci_dev *pdev  = to_pci_dev(dev->dev);

	if (pdev->dev.bus && pdev->dev.bus->pm) {
		dev->pg_domain.ops = *pdev->dev.bus->pm;

		dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
		dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
		dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;

		dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
	}
}

/**
 * mei_me_unset_pm_domain - clean pm domain structure for device
 *
 * @dev: mei_device
 */
static inline void mei_me_unset_pm_domain(struct mei_device *dev)
{
	/* stop using pm callbacks if any */
	dev_pm_domain_set(dev->dev, NULL);
}

static const struct dev_pm_ops mei_me_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
				mei_me_pci_resume)
	SET_RUNTIME_PM_OPS(
		mei_me_pm_runtime_suspend,
		mei_me_pm_runtime_resume,
		mei_me_pm_runtime_idle)
};

#define MEI_ME_PM_OPS	(&mei_me_pm_ops)
#else
#define MEI_ME_PM_OPS	NULL
#endif /* CONFIG_PM */
/*
 *  PCI driver structure
 */
static struct pci_driver mei_me_driver = {
	.name = KBUILD_MODNAME,
	.id_table = mei_me_pci_tbl,
	.probe = mei_me_probe,
	.remove = mei_me_remove,
	.shutdown = mei_me_remove,
	.driver.pm = MEI_ME_PM_OPS,
};

module_pci_driver(mei_me_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2703d4b2 TW	1	/*
	2	*
	3	* Intel Management Engine Interface (Intel MEI) Linux driver
	4	* Copyright (c) 2003-2012, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	*/
2703d4b2 TW	16	#include <linux/module.h>
	17	#include <linux/moduleparam.h>
	18	#include <linux/kernel.h>
	19	#include <linux/device.h>
	20	#include <linux/fs.h>
	21	#include <linux/errno.h>
	22	#include <linux/types.h>
	23	#include <linux/fcntl.h>
2703d4b2 TW	24	#include <linux/pci.h>
2703d4b2 TW	25	#include <linux/poll.h>
2703d4b2 TW	26	#include <linux/ioctl.h>
	27	#include <linux/cdev.h>
	28	#include <linux/sched.h>
	29	#include <linux/uuid.h>
	30	#include <linux/compat.h>
	31	#include <linux/jiffies.h>
	32	#include <linux/interrupt.h>
2703d4b2	33
989561de	34	#include <linux/pm_domain.h>
180ea05b TW	35	#include <linux/pm_runtime.h>
180ea05b TW	36
2703d4b2 TW	37	#include <linux/mei.h>
	38
	39	#include "mei_dev.h"
2703d4b2	40	#include "client.h"
6e4cd27a TW	41	#include "hw-me-regs.h"
6e4cd27a TW	42	#include "hw-me.h"
2703d4b2	43
2703d4b2	44	/* mei_pci_tbl - PCI Device ID Table */
a05f8f86	45	static const struct pci_device_id mei_me_pci_tbl[] = {
8d929d48 AU	46	{MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, mei_me_legacy_cfg)},
	47	{MEI_PCI_DEVICE(MEI_DEV_ID_82G35, mei_me_legacy_cfg)},
	48	{MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, mei_me_legacy_cfg)},
	49	{MEI_PCI_DEVICE(MEI_DEV_ID_82G965, mei_me_legacy_cfg)},
	50	{MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, mei_me_legacy_cfg)},
	51	{MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, mei_me_legacy_cfg)},
	52	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, mei_me_legacy_cfg)},
	53	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, mei_me_legacy_cfg)},
	54	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, mei_me_legacy_cfg)},
	55	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, mei_me_legacy_cfg)},
	56	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, mei_me_legacy_cfg)},
	57
	58	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, mei_me_legacy_cfg)},
	59	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, mei_me_legacy_cfg)},
	60	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, mei_me_legacy_cfg)},
	61	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, mei_me_legacy_cfg)},
	62	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, mei_me_legacy_cfg)},
	63	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, mei_me_legacy_cfg)},
	64	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, mei_me_legacy_cfg)},
	65	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, mei_me_legacy_cfg)},
	66	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, mei_me_legacy_cfg)},
	67	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, mei_me_ich_cfg)},
	68	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, mei_me_ich_cfg)},
	69	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, mei_me_ich_cfg)},
	70	{MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, mei_me_ich_cfg)},
	71
	72	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, mei_me_pch_cfg)},
	73	{MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, mei_me_pch_cfg)},
c919951d TW	74	{MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, mei_me_pch_cpt_pbg_cfg)},
c919951d TW	75	{MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, mei_me_pch_cpt_pbg_cfg)},
8d929d48 AU	76	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, mei_me_pch_cfg)},
	77	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, mei_me_pch_cfg)},
	78	{MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, mei_me_pch_cfg)},
edca5ea3 AU	79	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, mei_me_pch8_sps_cfg)},
	80	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, mei_me_pch8_sps_cfg)},
	81	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, mei_me_pch8_cfg)},
	82	{MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, mei_me_pch8_sps_cfg)},
	83	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, mei_me_pch8_cfg)},
	84	{MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, mei_me_pch8_cfg)},
2703d4b2	85
1625c7ec TW	86	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT, mei_me_pch8_cfg)},
1625c7ec TW	87	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, mei_me_pch8_cfg)},
8c57cac1 TW	88	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, mei_me_pch8_sps_cfg)},
8c57cac1 TW	89	{MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, mei_me_pch8_sps_cfg)},
9ff2007b	90	{MEI_PCI_DEVICE(MEI_DEV_ID_LBG, mei_me_pch8_cfg)},
1625c7ec	91
dd16f6cd TW	92	{MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, mei_me_pch8_cfg)},
	93	{MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, mei_me_pch8_cfg)},
	94
ac182e8a AU	95	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP, mei_me_pch8_cfg)},
	96	{MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, mei_me_pch8_cfg)},
	97
2703d4b2 TW	98	/* required last entry */
	99	{0, }
	100	};
	101
b68301e9	102	MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
2703d4b2	103
bbd6d050	104	#ifdef CONFIG_PM
e13fa90c TW	105	static inline void mei_me_set_pm_domain(struct mei_device *dev);
	106	static inline void mei_me_unset_pm_domain(struct mei_device *dev);
	107	#else
	108	static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
	109	static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
bbd6d050	110	#endif /* CONFIG_PM */
e13fa90c	111
2703d4b2	112	/**
ce23139c	113	* mei_me_quirk_probe - probe for devices that doesn't valid ME interface
393b148f	114	*
2703d4b2	115	* @pdev: PCI device structure
c919951d	116	* @cfg: per generation config
2703d4b2	117	*
a8605ea2	118	* Return: true if ME Interface is valid, false otherwise
2703d4b2	119	*/
b68301e9	120	static bool mei_me_quirk_probe(struct pci_dev *pdev,
c919951d	121	const struct mei_cfg *cfg)
2703d4b2	122	{
c919951d TW	123	if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
	124	dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
	125	return false;
5e6533a6 TW	126	}
5e6533a6 TW	127
2703d4b2 TW	128	return true;
2703d4b2 TW	129	}
c919951d	130
2703d4b2	131	/**
ce23139c	132	* mei_me_probe - Device Initialization Routine
2703d4b2 TW	133	*
	134	* @pdev: PCI device structure
	135	* @ent: entry in kcs_pci_tbl
	136	*
a8605ea2	137	* Return: 0 on success, <0 on failure.
2703d4b2	138	*/
b68301e9	139	static int mei_me_probe(struct pci_dev pdev, const struct pci_device_id ent)
2703d4b2	140	{
8d929d48	141	const struct mei_cfg cfg = (struct mei_cfg )(ent->driver_data);
2703d4b2	142	struct mei_device *dev;
52c34561	143	struct mei_me_hw *hw;
1fa55b4e	144	unsigned int irqflags;
2703d4b2 TW	145	int err;
2703d4b2 TW	146
2703d4b2	147
c919951d TW	148	if (!mei_me_quirk_probe(pdev, cfg))
c919951d TW	149	return -ENODEV;
2703d4b2	150
2703d4b2 TW	151	/* enable pci dev */
	152	err = pci_enable_device(pdev);
	153	if (err) {
	154	dev_err(&pdev->dev, "failed to enable pci device.\n");
	155	goto end;
	156	}
	157	/* set PCI host mastering */
	158	pci_set_master(pdev);
	159	/* pci request regions for mei driver */
	160	err = pci_request_regions(pdev, KBUILD_MODNAME);
	161	if (err) {
	162	dev_err(&pdev->dev, "failed to get pci regions.\n");
	163	goto disable_device;
	164	}
3ecfb168 TW	165
	166	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) \|\|
	167	dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
	168
	169	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
	170	if (err)
	171	err = dma_set_coherent_mask(&pdev->dev,
	172	DMA_BIT_MASK(32));
	173	}
	174	if (err) {
	175	dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
	176	goto release_regions;
	177	}
	178
	179
2703d4b2	180	/* allocates and initializes the mei dev structure */
8d929d48	181	dev = mei_me_dev_init(pdev, cfg);
2703d4b2 TW	182	if (!dev) {
	183	err = -ENOMEM;
	184	goto release_regions;
	185	}
52c34561	186	hw = to_me_hw(dev);
2703d4b2	187	/* mapping IO device memory */
52c34561 TW	188	hw->mem_addr = pci_iomap(pdev, 0, 0);
52c34561 TW	189	if (!hw->mem_addr) {
2703d4b2 TW	190	dev_err(&pdev->dev, "mapping I/O device memory failure.\n");
	191	err = -ENOMEM;
	192	goto free_device;
	193	}
	194	pci_enable_msi(pdev);
	195
	196	/* request and enable interrupt */
1fa55b4e AU	197	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
	198
	199	err = request_threaded_irq(pdev->irq,
06ecd645 TW	200	mei_me_irq_quick_handler,
06ecd645 TW	201	mei_me_irq_thread_handler,
1fa55b4e	202	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	203	if (err) {
	204	dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
	205	pdev->irq);
	206	goto disable_msi;
	207	}
	208
c4d589be	209	if (mei_start(dev)) {
2703d4b2 TW	210	dev_err(&pdev->dev, "init hw failure.\n");
	211	err = -ENODEV;
	212	goto release_irq;
	213	}
	214
180ea05b TW	215	pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
	216	pm_runtime_use_autosuspend(&pdev->dev);
	217
f3d8e878	218	err = mei_register(dev, &pdev->dev);
2703d4b2	219	if (err)
1f7e489a	220	goto stop;
2703d4b2	221
2703d4b2 TW	222	pci_set_drvdata(pdev, dev);
2703d4b2 TW	223
e13fa90c TW	224	/*
	225	* For not wake-able HW runtime pm framework
	226	* can't be used on pci device level.
	227	* Use domain runtime pm callbacks instead.
	228	*/
	229	if (!pci_dev_run_wake(pdev))
	230	mei_me_set_pm_domain(dev);
	231
180ea05b TW	232	if (mei_pg_is_enabled(dev))
	233	pm_runtime_put_noidle(&pdev->dev);
	234
c4e87b52	235	dev_dbg(&pdev->dev, "initialization successful.\n");
2703d4b2 TW	236
	237	return 0;
	238
1f7e489a AU	239	stop:
1f7e489a AU	240	mei_stop(dev);
2703d4b2	241	release_irq:
dc844b0d	242	mei_cancel_work(dev);
2703d4b2	243	mei_disable_interrupts(dev);
2703d4b2 TW	244	free_irq(pdev->irq, dev);
	245	disable_msi:
	246	pci_disable_msi(pdev);
52c34561	247	pci_iounmap(pdev, hw->mem_addr);
2703d4b2 TW	248	free_device:
	249	kfree(dev);
	250	release_regions:
	251	pci_release_regions(pdev);
	252	disable_device:
	253	pci_disable_device(pdev);
	254	end:
2703d4b2 TW	255	dev_err(&pdev->dev, "initialization failed.\n");
	256	return err;
	257	}
	258
	259	/**
ce23139c	260	* mei_me_remove - Device Removal Routine
2703d4b2 TW	261	*
	262	* @pdev: PCI device structure
	263	*
	264	* mei_remove is called by the PCI subsystem to alert the driver
	265	* that it should release a PCI device.
	266	*/
b68301e9	267	static void mei_me_remove(struct pci_dev *pdev)
2703d4b2 TW	268	{
2703d4b2 TW	269	struct mei_device *dev;
52c34561	270	struct mei_me_hw *hw;
2703d4b2	271
2703d4b2 TW	272	dev = pci_get_drvdata(pdev);
	273	if (!dev)
	274	return;
	275
180ea05b TW	276	if (mei_pg_is_enabled(dev))
	277	pm_runtime_get_noresume(&pdev->dev);
	278
52c34561 TW	279	hw = to_me_hw(dev);
52c34561 TW	280
2703d4b2	281
ed6f7ac1	282	dev_dbg(&pdev->dev, "stop\n");
7cb035d9	283	mei_stop(dev);
2703d4b2	284
e13fa90c TW	285	if (!pci_dev_run_wake(pdev))
	286	mei_me_unset_pm_domain(dev);
	287
2703d4b2 TW	288	/* disable interrupts */
	289	mei_disable_interrupts(dev);
	290
	291	free_irq(pdev->irq, dev);
	292	pci_disable_msi(pdev);
2703d4b2	293
52c34561 TW	294	if (hw->mem_addr)
52c34561 TW	295	pci_iounmap(pdev, hw->mem_addr);
2703d4b2	296
30e53bb8 TW	297	mei_deregister(dev);
30e53bb8 TW	298
2703d4b2 TW	299	kfree(dev);
	300
	301	pci_release_regions(pdev);
	302	pci_disable_device(pdev);
	303
2703d4b2 TW	304
2703d4b2 TW	305	}
16833257	306	#ifdef CONFIG_PM_SLEEP
b68301e9	307	static int mei_me_pci_suspend(struct device *device)
2703d4b2 TW	308	{
	309	struct pci_dev *pdev = to_pci_dev(device);
	310	struct mei_device *dev = pci_get_drvdata(pdev);
2703d4b2 TW	311
	312	if (!dev)
	313	return -ENODEV;
2703d4b2	314
ed6f7ac1	315	dev_dbg(&pdev->dev, "suspend\n");
2703d4b2	316
7cb035d9 TW	317	mei_stop(dev);
	318
	319	mei_disable_interrupts(dev);
2703d4b2 TW	320
	321	free_irq(pdev->irq, dev);
	322	pci_disable_msi(pdev);
	323
7cb035d9	324	return 0;
2703d4b2 TW	325	}
2703d4b2 TW	326
b68301e9	327	static int mei_me_pci_resume(struct device *device)
2703d4b2 TW	328	{
	329	struct pci_dev *pdev = to_pci_dev(device);
	330	struct mei_device *dev;
1fa55b4e	331	unsigned int irqflags;
2703d4b2 TW	332	int err;
	333
	334	dev = pci_get_drvdata(pdev);
	335	if (!dev)
	336	return -ENODEV;
	337
	338	pci_enable_msi(pdev);
	339
1fa55b4e AU	340	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
1fa55b4e AU	341
2703d4b2	342	/* request and enable interrupt */
1fa55b4e	343	err = request_threaded_irq(pdev->irq,
06ecd645 TW	344	mei_me_irq_quick_handler,
06ecd645 TW	345	mei_me_irq_thread_handler,
1fa55b4e	346	irqflags, KBUILD_MODNAME, dev);
2703d4b2 TW	347
	348	if (err) {
	349	dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
	350	pdev->irq);
	351	return err;
	352	}
	353
33ec0826 TW	354	err = mei_restart(dev);
	355	if (err)
	356	return err;
2703d4b2 TW	357
	358	/* Start timer if stopped in suspend */
	359	schedule_delayed_work(&dev->timer_work, HZ);
	360
33ec0826	361	return 0;
2703d4b2	362	}
180ea05b TW	363	#endif /* CONFIG_PM_SLEEP */
180ea05b TW	364
bbd6d050	365	#ifdef CONFIG_PM
180ea05b TW	366	static int mei_me_pm_runtime_idle(struct device *device)
	367	{
	368	struct pci_dev *pdev = to_pci_dev(device);
	369	struct mei_device *dev;
	370
	371	dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
	372
	373	dev = pci_get_drvdata(pdev);
	374	if (!dev)
	375	return -ENODEV;
	376	if (mei_write_is_idle(dev))
d5d83f8a	377	pm_runtime_autosuspend(device);
180ea05b TW	378
	379	return -EBUSY;
	380	}
	381
	382	static int mei_me_pm_runtime_suspend(struct device *device)
	383	{
	384	struct pci_dev *pdev = to_pci_dev(device);
	385	struct mei_device *dev;
	386	int ret;
	387
	388	dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
	389
	390	dev = pci_get_drvdata(pdev);
	391	if (!dev)
	392	return -ENODEV;
	393
	394	mutex_lock(&dev->device_lock);
	395
	396	if (mei_write_is_idle(dev))
2d1995fc	397	ret = mei_me_pg_enter_sync(dev);
180ea05b TW	398	else
	399	ret = -EAGAIN;
	400
	401	mutex_unlock(&dev->device_lock);
	402
	403	dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
	404
77537ad2 AU	405	if (ret && ret != -EAGAIN)
	406	schedule_work(&dev->reset_work);
	407
180ea05b TW	408	return ret;
	409	}
	410
	411	static int mei_me_pm_runtime_resume(struct device *device)
	412	{
	413	struct pci_dev *pdev = to_pci_dev(device);
	414	struct mei_device *dev;
	415	int ret;
	416
	417	dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
	418
	419	dev = pci_get_drvdata(pdev);
	420	if (!dev)
	421	return -ENODEV;
	422
	423	mutex_lock(&dev->device_lock);
	424
2d1995fc	425	ret = mei_me_pg_exit_sync(dev);
180ea05b TW	426
	427	mutex_unlock(&dev->device_lock);
	428
	429	dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
	430
77537ad2 AU	431	if (ret)
	432	schedule_work(&dev->reset_work);
	433
180ea05b TW	434	return ret;
180ea05b TW	435	}
e13fa90c TW	436
e13fa90c TW	437	/**
7efceb55	438	* mei_me_set_pm_domain - fill and set pm domain structure for device
e13fa90c TW	439	*
	440	* @dev: mei_device
	441	*/
	442	static inline void mei_me_set_pm_domain(struct mei_device *dev)
	443	{
d08b8fc0	444	struct pci_dev *pdev = to_pci_dev(dev->dev);
e13fa90c TW	445
	446	if (pdev->dev.bus && pdev->dev.bus->pm) {
	447	dev->pg_domain.ops = *pdev->dev.bus->pm;
	448
	449	dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
	450	dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
	451	dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
	452
989561de	453	dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
e13fa90c TW	454	}
	455	}
	456
	457	/**
7efceb55	458	* mei_me_unset_pm_domain - clean pm domain structure for device
e13fa90c TW	459	*
	460	* @dev: mei_device
	461	*/
	462	static inline void mei_me_unset_pm_domain(struct mei_device *dev)
	463	{
	464	/* stop using pm callbacks if any */
989561de	465	dev_pm_domain_set(dev->dev, NULL);
e13fa90c	466	}
180ea05b	467
180ea05b TW	468	static const struct dev_pm_ops mei_me_pm_ops = {
	469	SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
	470	mei_me_pci_resume)
	471	SET_RUNTIME_PM_OPS(
	472	mei_me_pm_runtime_suspend,
	473	mei_me_pm_runtime_resume,
	474	mei_me_pm_runtime_idle)
	475	};
16833257	476
b68301e9	477	#define MEI_ME_PM_OPS (&mei_me_pm_ops)
2703d4b2	478	#else
b68301e9	479	#define MEI_ME_PM_OPS NULL
180ea05b	480	#endif /* CONFIG_PM */
2703d4b2 TW	481	/*
	482	* PCI driver structure
	483	*/
b68301e9	484	static struct pci_driver mei_me_driver = {
2703d4b2	485	.name = KBUILD_MODNAME,
b68301e9 TW	486	.id_table = mei_me_pci_tbl,
	487	.probe = mei_me_probe,
	488	.remove = mei_me_remove,
	489	.shutdown = mei_me_remove,
	490	.driver.pm = MEI_ME_PM_OPS,
2703d4b2 TW	491	};
2703d4b2 TW	492
b68301e9	493	module_pci_driver(mei_me_driver);
2703d4b2 TW	494
	495	MODULE_AUTHOR("Intel Corporation");
	496	MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
	497	MODULE_LICENSE("GPL v2");