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266f6178 TW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
4 | * Copyright (c) 2013-2014, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #ifndef _MEI_HW_TXE_H_ | |
18 | #define _MEI_HW_TXE_H_ | |
19 | ||
4a22176a SR |
20 | #include <linux/irqreturn.h> |
21 | ||
266f6178 TW |
22 | #include "hw.h" |
23 | #include "hw-txe-regs.h" | |
24 | ||
cfe5ab85 AU |
25 | #define MEI_TXI_RPM_TIMEOUT 500 /* ms */ |
26 | ||
266f6178 TW |
27 | /* Flatten Hierarchy interrupt cause */ |
28 | #define TXE_INTR_READINESS_BIT 0 /* HISR_INT_0_STS */ | |
29 | #define TXE_INTR_READINESS HISR_INT_0_STS | |
30 | #define TXE_INTR_ALIVENESS_BIT 1 /* HISR_INT_1_STS */ | |
31 | #define TXE_INTR_ALIVENESS HISR_INT_1_STS | |
32 | #define TXE_INTR_OUT_DB_BIT 2 /* HISR_INT_2_STS */ | |
33 | #define TXE_INTR_OUT_DB HISR_INT_2_STS | |
34 | #define TXE_INTR_IN_READY_BIT 8 /* beyond HISR */ | |
35 | #define TXE_INTR_IN_READY BIT(8) | |
36 | ||
37 | /** | |
38 | * struct mei_txe_hw - txe hardware specifics | |
39 | * | |
964a2331 TW |
40 | * @mem_addr: SeC and BRIDGE bars |
41 | * @aliveness: aliveness (power gating) state of the hardware | |
42 | * @readiness: readiness state of the hardware | |
ce23139c | 43 | * @slots: number of empty slots |
964a2331 TW |
44 | * @wait_aliveness_resp: aliveness wait queue |
45 | * @intr_cause: translated interrupt cause | |
266f6178 TW |
46 | */ |
47 | struct mei_txe_hw { | |
48 | void __iomem *mem_addr[NUM_OF_MEM_BARS]; | |
49 | u32 aliveness; | |
50 | u32 readiness; | |
9d098192 | 51 | u32 slots; |
266f6178 | 52 | |
964a2331 | 53 | wait_queue_head_t wait_aliveness_resp; |
266f6178 TW |
54 | |
55 | unsigned long intr_cause; | |
56 | }; | |
57 | ||
58 | #define to_txe_hw(dev) (struct mei_txe_hw *)((dev)->hw) | |
59 | ||
60 | static inline struct mei_device *hw_txe_to_mei(struct mei_txe_hw *hw) | |
61 | { | |
62 | return container_of((void *)hw, struct mei_device, hw); | |
63 | } | |
64 | ||
4ad96db6 | 65 | struct mei_device *mei_txe_dev_init(struct pci_dev *pdev); |
266f6178 TW |
66 | |
67 | irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id); | |
68 | irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id); | |
69 | ||
70 | int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req); | |
71 | ||
72 | int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range); | |
73 | ||
74 | ||
75 | #endif /* _MEI_HW_TXE_H_ */ |