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32e2b59f TW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
4 | * Copyright (c) 2013-2014, Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
18 | #include <linux/jiffies.h> | |
fe292283 | 19 | #include <linux/ktime.h> |
32e2b59f TW |
20 | #include <linux/delay.h> |
21 | #include <linux/kthread.h> | |
4a8efd4a | 22 | #include <linux/interrupt.h> |
77537ad2 | 23 | #include <linux/pm_runtime.h> |
32e2b59f TW |
24 | |
25 | #include <linux/mei.h> | |
26 | ||
27 | #include "mei_dev.h" | |
28 | #include "hw-txe.h" | |
29 | #include "client.h" | |
30 | #include "hbm.h" | |
31 | ||
a96c5482 TW |
32 | #include "mei-trace.h" |
33 | ||
34 | ||
32e2b59f | 35 | /** |
ce23139c | 36 | * mei_txe_reg_read - Reads 32bit data from the txe device |
32e2b59f TW |
37 | * |
38 | * @base_addr: registers base address | |
39 | * @offset: register offset | |
40 | * | |
ce23139c | 41 | * Return: register value |
32e2b59f TW |
42 | */ |
43 | static inline u32 mei_txe_reg_read(void __iomem *base_addr, | |
44 | unsigned long offset) | |
45 | { | |
46 | return ioread32(base_addr + offset); | |
47 | } | |
48 | ||
49 | /** | |
ce23139c | 50 | * mei_txe_reg_write - Writes 32bit data to the txe device |
32e2b59f TW |
51 | * |
52 | * @base_addr: registers base address | |
53 | * @offset: register offset | |
54 | * @value: the value to write | |
55 | */ | |
56 | static inline void mei_txe_reg_write(void __iomem *base_addr, | |
57 | unsigned long offset, u32 value) | |
58 | { | |
59 | iowrite32(value, base_addr + offset); | |
60 | } | |
61 | ||
62 | /** | |
63 | * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR | |
64 | * | |
ce23139c | 65 | * @hw: the txe hardware structure |
32e2b59f TW |
66 | * @offset: register offset |
67 | * | |
68 | * Doesn't check for aliveness while Reads 32bit data from the SeC BAR | |
ce23139c AU |
69 | * |
70 | * Return: register value | |
32e2b59f TW |
71 | */ |
72 | static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw, | |
73 | unsigned long offset) | |
74 | { | |
75 | return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset); | |
76 | } | |
77 | ||
78 | /** | |
79 | * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR | |
80 | * | |
ce23139c | 81 | * @hw: the txe hardware structure |
32e2b59f TW |
82 | * @offset: register offset |
83 | * | |
84 | * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set | |
ce23139c AU |
85 | * |
86 | * Return: register value | |
32e2b59f TW |
87 | */ |
88 | static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw, | |
89 | unsigned long offset) | |
90 | { | |
91 | WARN(!hw->aliveness, "sec read: aliveness not asserted\n"); | |
92 | return mei_txe_sec_reg_read_silent(hw, offset); | |
93 | } | |
94 | /** | |
95 | * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR | |
96 | * doesn't check for aliveness | |
97 | * | |
a8605ea2 | 98 | * @hw: the txe hardware structure |
32e2b59f TW |
99 | * @offset: register offset |
100 | * @value: value to write | |
101 | * | |
102 | * Doesn't check for aliveness while writes 32bit data from to the SeC BAR | |
103 | */ | |
104 | static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw, | |
105 | unsigned long offset, u32 value) | |
106 | { | |
107 | mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value); | |
108 | } | |
109 | ||
110 | /** | |
111 | * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR | |
112 | * | |
a8605ea2 | 113 | * @hw: the txe hardware structure |
32e2b59f TW |
114 | * @offset: register offset |
115 | * @value: value to write | |
116 | * | |
117 | * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set | |
118 | */ | |
119 | static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw, | |
120 | unsigned long offset, u32 value) | |
121 | { | |
122 | WARN(!hw->aliveness, "sec write: aliveness not asserted\n"); | |
123 | mei_txe_sec_reg_write_silent(hw, offset, value); | |
124 | } | |
125 | /** | |
126 | * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR | |
127 | * | |
ce23139c | 128 | * @hw: the txe hardware structure |
32e2b59f TW |
129 | * @offset: offset from which to read the data |
130 | * | |
ce23139c | 131 | * Return: the byte read. |
32e2b59f TW |
132 | */ |
133 | static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw, | |
134 | unsigned long offset) | |
135 | { | |
136 | return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset); | |
137 | } | |
138 | ||
139 | /** | |
140 | * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR | |
141 | * | |
a8605ea2 | 142 | * @hw: the txe hardware structure |
32e2b59f TW |
143 | * @offset: offset from which to write the data |
144 | * @value: the byte to write | |
145 | */ | |
146 | static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw, | |
147 | unsigned long offset, u32 value) | |
148 | { | |
149 | mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value); | |
150 | } | |
151 | ||
152 | /** | |
153 | * mei_txe_aliveness_set - request for aliveness change | |
154 | * | |
155 | * @dev: the device structure | |
156 | * @req: requested aliveness value | |
157 | * | |
158 | * Request for aliveness change and returns true if the change is | |
159 | * really needed and false if aliveness is already | |
160 | * in the requested state | |
ce23139c AU |
161 | * |
162 | * Locking: called under "dev->device_lock" lock | |
163 | * | |
164 | * Return: true if request was send | |
32e2b59f TW |
165 | */ |
166 | static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req) | |
167 | { | |
168 | ||
169 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
170 | bool do_req = hw->aliveness != req; | |
171 | ||
2bf94cab | 172 | dev_dbg(dev->dev, "Aliveness current=%d request=%d\n", |
32e2b59f TW |
173 | hw->aliveness, req); |
174 | if (do_req) { | |
964a2331 | 175 | dev->pg_event = MEI_PG_EVENT_WAIT; |
32e2b59f TW |
176 | mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req); |
177 | } | |
178 | return do_req; | |
179 | } | |
180 | ||
181 | ||
182 | /** | |
183 | * mei_txe_aliveness_req_get - get aliveness requested register value | |
184 | * | |
185 | * @dev: the device structure | |
186 | * | |
187 | * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from | |
188 | * from HICR_HOST_ALIVENESS_REQ register value | |
ce23139c AU |
189 | * |
190 | * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value | |
32e2b59f TW |
191 | */ |
192 | static u32 mei_txe_aliveness_req_get(struct mei_device *dev) | |
193 | { | |
194 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
195 | u32 reg; | |
92db1555 | 196 | |
32e2b59f TW |
197 | reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG); |
198 | return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED; | |
199 | } | |
200 | ||
201 | /** | |
202 | * mei_txe_aliveness_get - get aliveness response register value | |
ce23139c | 203 | * |
32e2b59f TW |
204 | * @dev: the device structure |
205 | * | |
ce23139c AU |
206 | * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP |
207 | * register | |
32e2b59f TW |
208 | */ |
209 | static u32 mei_txe_aliveness_get(struct mei_device *dev) | |
210 | { | |
211 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
212 | u32 reg; | |
92db1555 | 213 | |
32e2b59f TW |
214 | reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG); |
215 | return reg & HICR_HOST_ALIVENESS_RESP_ACK; | |
216 | } | |
217 | ||
218 | /** | |
219 | * mei_txe_aliveness_poll - waits for aliveness to settle | |
220 | * | |
221 | * @dev: the device structure | |
222 | * @expected: expected aliveness value | |
223 | * | |
224 | * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set | |
a8605ea2 | 225 | * |
fe292283 | 226 | * Return: 0 if the expected value was received, -ETIME otherwise |
32e2b59f TW |
227 | */ |
228 | static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected) | |
229 | { | |
230 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
fe292283 | 231 | ktime_t stop, start; |
32e2b59f | 232 | |
fe292283 TW |
233 | start = ktime_get(); |
234 | stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT)); | |
32e2b59f TW |
235 | do { |
236 | hw->aliveness = mei_txe_aliveness_get(dev); | |
237 | if (hw->aliveness == expected) { | |
964a2331 | 238 | dev->pg_event = MEI_PG_EVENT_IDLE; |
fe292283 TW |
239 | dev_dbg(dev->dev, "aliveness settled after %lld usecs\n", |
240 | ktime_to_us(ktime_sub(ktime_get(), start))); | |
241 | return 0; | |
32e2b59f | 242 | } |
fe292283 TW |
243 | usleep_range(20, 50); |
244 | } while (ktime_before(ktime_get(), stop)); | |
32e2b59f | 245 | |
964a2331 | 246 | dev->pg_event = MEI_PG_EVENT_IDLE; |
2bf94cab | 247 | dev_err(dev->dev, "aliveness timed out\n"); |
32e2b59f TW |
248 | return -ETIME; |
249 | } | |
250 | ||
251 | /** | |
252 | * mei_txe_aliveness_wait - waits for aliveness to settle | |
253 | * | |
254 | * @dev: the device structure | |
255 | * @expected: expected aliveness value | |
256 | * | |
257 | * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set | |
a8605ea2 AU |
258 | * |
259 | * Return: 0 on success and < 0 otherwise | |
32e2b59f TW |
260 | */ |
261 | static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected) | |
262 | { | |
263 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
264 | const unsigned long timeout = | |
265 | msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT); | |
266 | long err; | |
267 | int ret; | |
268 | ||
269 | hw->aliveness = mei_txe_aliveness_get(dev); | |
270 | if (hw->aliveness == expected) | |
271 | return 0; | |
272 | ||
273 | mutex_unlock(&dev->device_lock); | |
964a2331 TW |
274 | err = wait_event_timeout(hw->wait_aliveness_resp, |
275 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
32e2b59f TW |
276 | mutex_lock(&dev->device_lock); |
277 | ||
278 | hw->aliveness = mei_txe_aliveness_get(dev); | |
279 | ret = hw->aliveness == expected ? 0 : -ETIME; | |
280 | ||
281 | if (ret) | |
2bf94cab | 282 | dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n", |
964a2331 | 283 | err, hw->aliveness, dev->pg_event); |
32e2b59f | 284 | else |
2bf94cab | 285 | dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n", |
964a2331 TW |
286 | jiffies_to_msecs(timeout - err), |
287 | hw->aliveness, dev->pg_event); | |
288 | ||
289 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
32e2b59f TW |
290 | return ret; |
291 | } | |
292 | ||
293 | /** | |
294 | * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete | |
295 | * | |
296 | * @dev: the device structure | |
ce23139c | 297 | * @req: requested aliveness value |
32e2b59f | 298 | * |
a8605ea2 | 299 | * Return: 0 on success and < 0 otherwise |
32e2b59f TW |
300 | */ |
301 | int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req) | |
302 | { | |
303 | if (mei_txe_aliveness_set(dev, req)) | |
304 | return mei_txe_aliveness_wait(dev, req); | |
305 | return 0; | |
306 | } | |
307 | ||
3dc196ea AU |
308 | /** |
309 | * mei_txe_pg_in_transition - is device now in pg transition | |
310 | * | |
311 | * @dev: the device structure | |
312 | * | |
313 | * Return: true if in pg transition, false otherwise | |
314 | */ | |
315 | static bool mei_txe_pg_in_transition(struct mei_device *dev) | |
316 | { | |
317 | return dev->pg_event == MEI_PG_EVENT_WAIT; | |
318 | } | |
319 | ||
ee7e5afd TW |
320 | /** |
321 | * mei_txe_pg_is_enabled - detect if PG is supported by HW | |
322 | * | |
323 | * @dev: the device structure | |
324 | * | |
a8605ea2 | 325 | * Return: true is pg supported, false otherwise |
ee7e5afd TW |
326 | */ |
327 | static bool mei_txe_pg_is_enabled(struct mei_device *dev) | |
328 | { | |
329 | return true; | |
330 | } | |
331 | ||
964a2331 TW |
332 | /** |
333 | * mei_txe_pg_state - translate aliveness register value | |
334 | * to the mei power gating state | |
335 | * | |
336 | * @dev: the device structure | |
337 | * | |
a8605ea2 | 338 | * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise |
964a2331 TW |
339 | */ |
340 | static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev) | |
341 | { | |
342 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 343 | |
964a2331 TW |
344 | return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON; |
345 | } | |
346 | ||
32e2b59f TW |
347 | /** |
348 | * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt | |
349 | * | |
350 | * @dev: the device structure | |
351 | */ | |
352 | static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev) | |
353 | { | |
354 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
355 | u32 hintmsk; | |
356 | /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */ | |
357 | hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG); | |
358 | hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY; | |
359 | mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk); | |
360 | } | |
361 | ||
362 | /** | |
a8605ea2 AU |
363 | * mei_txe_input_doorbell_set - sets bit 0 in |
364 | * SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL. | |
365 | * | |
366 | * @hw: the txe hardware structure | |
32e2b59f TW |
367 | */ |
368 | static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw) | |
369 | { | |
370 | /* Clear the interrupt cause */ | |
371 | clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause); | |
372 | mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1); | |
373 | } | |
374 | ||
375 | /** | |
376 | * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1 | |
377 | * | |
a8605ea2 | 378 | * @hw: the txe hardware structure |
32e2b59f TW |
379 | */ |
380 | static void mei_txe_output_ready_set(struct mei_txe_hw *hw) | |
381 | { | |
382 | mei_txe_br_reg_write(hw, | |
383 | SICR_SEC_IPC_OUTPUT_STATUS_REG, | |
384 | SEC_IPC_OUTPUT_STATUS_RDY); | |
385 | } | |
386 | ||
387 | /** | |
388 | * mei_txe_is_input_ready - check if TXE is ready for receiving data | |
389 | * | |
390 | * @dev: the device structure | |
ce23139c AU |
391 | * |
392 | * Return: true if INPUT STATUS READY bit is set | |
32e2b59f TW |
393 | */ |
394 | static bool mei_txe_is_input_ready(struct mei_device *dev) | |
395 | { | |
396 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
397 | u32 status; | |
92db1555 | 398 | |
32e2b59f TW |
399 | status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG); |
400 | return !!(SEC_IPC_INPUT_STATUS_RDY & status); | |
401 | } | |
402 | ||
403 | /** | |
404 | * mei_txe_intr_clear - clear all interrupts | |
405 | * | |
406 | * @dev: the device structure | |
407 | */ | |
408 | static inline void mei_txe_intr_clear(struct mei_device *dev) | |
409 | { | |
410 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 411 | |
32e2b59f TW |
412 | mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG, |
413 | SEC_IPC_HOST_INT_STATUS_PENDING); | |
414 | mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK); | |
415 | mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK); | |
416 | } | |
417 | ||
418 | /** | |
419 | * mei_txe_intr_disable - disable all interrupts | |
420 | * | |
421 | * @dev: the device structure | |
422 | */ | |
423 | static void mei_txe_intr_disable(struct mei_device *dev) | |
424 | { | |
425 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 426 | |
32e2b59f TW |
427 | mei_txe_br_reg_write(hw, HHIER_REG, 0); |
428 | mei_txe_br_reg_write(hw, HIER_REG, 0); | |
429 | } | |
430 | /** | |
3908be6f | 431 | * mei_txe_intr_enable - enable all interrupts |
32e2b59f TW |
432 | * |
433 | * @dev: the device structure | |
434 | */ | |
435 | static void mei_txe_intr_enable(struct mei_device *dev) | |
436 | { | |
437 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 438 | |
32e2b59f TW |
439 | mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK); |
440 | mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK); | |
441 | } | |
442 | ||
4a8efd4a TW |
443 | /** |
444 | * mei_txe_synchronize_irq - wait for pending IRQ handlers | |
445 | * | |
446 | * @dev: the device structure | |
447 | */ | |
448 | static void mei_txe_synchronize_irq(struct mei_device *dev) | |
449 | { | |
450 | struct pci_dev *pdev = to_pci_dev(dev->dev); | |
451 | ||
452 | synchronize_irq(pdev->irq); | |
453 | } | |
454 | ||
32e2b59f TW |
455 | /** |
456 | * mei_txe_pending_interrupts - check if there are pending interrupts | |
457 | * only Aliveness, Input ready, and output doorbell are of relevance | |
458 | * | |
459 | * @dev: the device structure | |
460 | * | |
461 | * Checks if there are pending interrupts | |
462 | * only Aliveness, Readiness, Input ready, and Output doorbell are relevant | |
ce23139c AU |
463 | * |
464 | * Return: true if there are pending interrupts | |
32e2b59f TW |
465 | */ |
466 | static bool mei_txe_pending_interrupts(struct mei_device *dev) | |
467 | { | |
468 | ||
469 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
470 | bool ret = (hw->intr_cause & (TXE_INTR_READINESS | | |
471 | TXE_INTR_ALIVENESS | | |
472 | TXE_INTR_IN_READY | | |
473 | TXE_INTR_OUT_DB)); | |
474 | ||
475 | if (ret) { | |
2bf94cab | 476 | dev_dbg(dev->dev, |
32e2b59f TW |
477 | "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n", |
478 | !!(hw->intr_cause & TXE_INTR_IN_READY), | |
479 | !!(hw->intr_cause & TXE_INTR_READINESS), | |
480 | !!(hw->intr_cause & TXE_INTR_ALIVENESS), | |
481 | !!(hw->intr_cause & TXE_INTR_OUT_DB)); | |
482 | } | |
483 | return ret; | |
484 | } | |
485 | ||
486 | /** | |
487 | * mei_txe_input_payload_write - write a dword to the host buffer | |
488 | * at offset idx | |
489 | * | |
490 | * @dev: the device structure | |
491 | * @idx: index in the host buffer | |
492 | * @value: value | |
493 | */ | |
494 | static void mei_txe_input_payload_write(struct mei_device *dev, | |
495 | unsigned long idx, u32 value) | |
496 | { | |
497 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 498 | |
32e2b59f TW |
499 | mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG + |
500 | (idx * sizeof(u32)), value); | |
501 | } | |
502 | ||
503 | /** | |
504 | * mei_txe_out_data_read - read dword from the device buffer | |
505 | * at offset idx | |
506 | * | |
507 | * @dev: the device structure | |
508 | * @idx: index in the device buffer | |
509 | * | |
a8605ea2 | 510 | * Return: register value at index |
32e2b59f TW |
511 | */ |
512 | static u32 mei_txe_out_data_read(const struct mei_device *dev, | |
513 | unsigned long idx) | |
514 | { | |
515 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 516 | |
32e2b59f TW |
517 | return mei_txe_br_reg_read(hw, |
518 | BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32))); | |
519 | } | |
520 | ||
521 | /* Readiness */ | |
522 | ||
523 | /** | |
ce23139c | 524 | * mei_txe_readiness_set_host_rdy - set host readiness bit |
32e2b59f TW |
525 | * |
526 | * @dev: the device structure | |
527 | */ | |
528 | static void mei_txe_readiness_set_host_rdy(struct mei_device *dev) | |
529 | { | |
530 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 531 | |
32e2b59f TW |
532 | mei_txe_br_reg_write(hw, |
533 | SICR_HOST_IPC_READINESS_REQ_REG, | |
534 | SICR_HOST_IPC_READINESS_HOST_RDY); | |
535 | } | |
536 | ||
537 | /** | |
ce23139c | 538 | * mei_txe_readiness_clear - clear host readiness bit |
32e2b59f TW |
539 | * |
540 | * @dev: the device structure | |
541 | */ | |
542 | static void mei_txe_readiness_clear(struct mei_device *dev) | |
543 | { | |
544 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 545 | |
32e2b59f TW |
546 | mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG, |
547 | SICR_HOST_IPC_READINESS_RDY_CLR); | |
548 | } | |
549 | /** | |
550 | * mei_txe_readiness_get - Reads and returns | |
551 | * the HICR_SEC_IPC_READINESS register value | |
552 | * | |
553 | * @dev: the device structure | |
a8605ea2 AU |
554 | * |
555 | * Return: the HICR_SEC_IPC_READINESS register value | |
32e2b59f TW |
556 | */ |
557 | static u32 mei_txe_readiness_get(struct mei_device *dev) | |
558 | { | |
559 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 560 | |
32e2b59f TW |
561 | return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); |
562 | } | |
563 | ||
564 | ||
565 | /** | |
566 | * mei_txe_readiness_is_sec_rdy - check readiness | |
567 | * for HICR_SEC_IPC_READINESS_SEC_RDY | |
568 | * | |
ce23139c AU |
569 | * @readiness: cached readiness state |
570 | * | |
571 | * Return: true if readiness bit is set | |
32e2b59f TW |
572 | */ |
573 | static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness) | |
574 | { | |
575 | return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY); | |
576 | } | |
577 | ||
578 | /** | |
579 | * mei_txe_hw_is_ready - check if the hw is ready | |
580 | * | |
581 | * @dev: the device structure | |
ce23139c AU |
582 | * |
583 | * Return: true if sec is ready | |
32e2b59f TW |
584 | */ |
585 | static bool mei_txe_hw_is_ready(struct mei_device *dev) | |
586 | { | |
587 | u32 readiness = mei_txe_readiness_get(dev); | |
92db1555 | 588 | |
32e2b59f TW |
589 | return mei_txe_readiness_is_sec_rdy(readiness); |
590 | } | |
591 | ||
592 | /** | |
593 | * mei_txe_host_is_ready - check if the host is ready | |
594 | * | |
595 | * @dev: the device structure | |
ce23139c AU |
596 | * |
597 | * Return: true if host is ready | |
32e2b59f TW |
598 | */ |
599 | static inline bool mei_txe_host_is_ready(struct mei_device *dev) | |
600 | { | |
601 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
602 | u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG); | |
92db1555 | 603 | |
32e2b59f TW |
604 | return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY); |
605 | } | |
606 | ||
607 | /** | |
608 | * mei_txe_readiness_wait - wait till readiness settles | |
609 | * | |
610 | * @dev: the device structure | |
611 | * | |
a8605ea2 | 612 | * Return: 0 on success and -ETIME on timeout |
32e2b59f TW |
613 | */ |
614 | static int mei_txe_readiness_wait(struct mei_device *dev) | |
615 | { | |
616 | if (mei_txe_hw_is_ready(dev)) | |
617 | return 0; | |
618 | ||
619 | mutex_unlock(&dev->device_lock); | |
620 | wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready, | |
621 | msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT)); | |
622 | mutex_lock(&dev->device_lock); | |
623 | if (!dev->recvd_hw_ready) { | |
2bf94cab | 624 | dev_err(dev->dev, "wait for readiness failed\n"); |
32e2b59f TW |
625 | return -ETIME; |
626 | } | |
627 | ||
628 | dev->recvd_hw_ready = false; | |
629 | return 0; | |
630 | } | |
631 | ||
480bd3c4 | 632 | static const struct mei_fw_status mei_txe_fw_sts = { |
4ad96db6 TW |
633 | .count = 2, |
634 | .status[0] = PCI_CFG_TXE_FW_STS0, | |
635 | .status[1] = PCI_CFG_TXE_FW_STS1 | |
636 | }; | |
1bd30b6a TW |
637 | |
638 | /** | |
639 | * mei_txe_fw_status - read fw status register from pci config space | |
640 | * | |
641 | * @dev: mei device | |
642 | * @fw_status: fw status register values | |
ce23139c AU |
643 | * |
644 | * Return: 0 on success, error otherwise | |
1bd30b6a TW |
645 | */ |
646 | static int mei_txe_fw_status(struct mei_device *dev, | |
647 | struct mei_fw_status *fw_status) | |
648 | { | |
4ad96db6 | 649 | const struct mei_fw_status *fw_src = &mei_txe_fw_sts; |
1bd30b6a TW |
650 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
651 | int ret; | |
652 | int i; | |
653 | ||
654 | if (!fw_status) | |
655 | return -EINVAL; | |
656 | ||
657 | fw_status->count = fw_src->count; | |
658 | for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { | |
a96c5482 TW |
659 | ret = pci_read_config_dword(pdev, fw_src->status[i], |
660 | &fw_status->status[i]); | |
661 | trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X", | |
662 | fw_src->status[i], | |
663 | fw_status->status[i]); | |
1bd30b6a TW |
664 | if (ret) |
665 | return ret; | |
666 | } | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
32e2b59f TW |
671 | /** |
672 | * mei_txe_hw_config - configure hardware at the start of the devices | |
673 | * | |
674 | * @dev: the device structure | |
675 | * | |
676 | * Configure hardware at the start of the device should be done only | |
677 | * once at the device probe time | |
678 | */ | |
679 | static void mei_txe_hw_config(struct mei_device *dev) | |
680 | { | |
681 | ||
682 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 | 683 | |
32e2b59f TW |
684 | /* Doesn't change in runtime */ |
685 | dev->hbuf_depth = PAYLOAD_SIZE / 4; | |
686 | ||
687 | hw->aliveness = mei_txe_aliveness_get(dev); | |
688 | hw->readiness = mei_txe_readiness_get(dev); | |
689 | ||
2bf94cab | 690 | dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n", |
32e2b59f TW |
691 | hw->aliveness, hw->readiness); |
692 | } | |
693 | ||
694 | ||
695 | /** | |
696 | * mei_txe_write - writes a message to device. | |
697 | * | |
698 | * @dev: the device structure | |
699 | * @header: header of message | |
700 | * @buf: message buffer will be written | |
a8605ea2 | 701 | * |
ce23139c | 702 | * Return: 0 if success, <0 - otherwise. |
32e2b59f TW |
703 | */ |
704 | ||
705 | static int mei_txe_write(struct mei_device *dev, | |
4b9960d0 TW |
706 | struct mei_msg_hdr *header, |
707 | const unsigned char *buf) | |
32e2b59f TW |
708 | { |
709 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
710 | unsigned long rem; | |
711 | unsigned long length; | |
9d098192 | 712 | int slots = dev->hbuf_depth; |
32e2b59f | 713 | u32 *reg_buf = (u32 *)buf; |
9d098192 | 714 | u32 dw_cnt; |
32e2b59f TW |
715 | int i; |
716 | ||
717 | if (WARN_ON(!header || !buf)) | |
718 | return -EINVAL; | |
719 | ||
720 | length = header->length; | |
721 | ||
2bf94cab | 722 | dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); |
32e2b59f | 723 | |
9d098192 TW |
724 | dw_cnt = mei_data2slots(length); |
725 | if (dw_cnt > slots) | |
726 | return -EMSGSIZE; | |
32e2b59f TW |
727 | |
728 | if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n")) | |
729 | return -EAGAIN; | |
730 | ||
731 | /* Enable Input Ready Interrupt. */ | |
732 | mei_txe_input_ready_interrupt_enable(dev); | |
733 | ||
734 | if (!mei_txe_is_input_ready(dev)) { | |
edca5ea3 | 735 | char fw_sts_str[MEI_FW_STATUS_STR_SZ]; |
92db1555 | 736 | |
edca5ea3 AU |
737 | mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ); |
738 | dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str); | |
32e2b59f TW |
739 | return -EAGAIN; |
740 | } | |
741 | ||
742 | mei_txe_input_payload_write(dev, 0, *((u32 *)header)); | |
743 | ||
744 | for (i = 0; i < length / 4; i++) | |
745 | mei_txe_input_payload_write(dev, i + 1, reg_buf[i]); | |
746 | ||
747 | rem = length & 0x3; | |
748 | if (rem > 0) { | |
749 | u32 reg = 0; | |
92db1555 | 750 | |
32e2b59f TW |
751 | memcpy(®, &buf[length - rem], rem); |
752 | mei_txe_input_payload_write(dev, i + 1, reg); | |
753 | } | |
754 | ||
9d098192 TW |
755 | /* after each write the whole buffer is consumed */ |
756 | hw->slots = 0; | |
757 | ||
32e2b59f TW |
758 | /* Set Input-Doorbell */ |
759 | mei_txe_input_doorbell_set(hw); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | /** | |
765 | * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer | |
766 | * | |
767 | * @dev: the device structure | |
768 | * | |
ce23139c | 769 | * Return: the PAYLOAD_SIZE - 4 |
32e2b59f TW |
770 | */ |
771 | static size_t mei_txe_hbuf_max_len(const struct mei_device *dev) | |
772 | { | |
773 | return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr); | |
774 | } | |
775 | ||
776 | /** | |
777 | * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer | |
778 | * | |
779 | * @dev: the device structure | |
780 | * | |
a8605ea2 | 781 | * Return: always hbuf_depth |
32e2b59f TW |
782 | */ |
783 | static int mei_txe_hbuf_empty_slots(struct mei_device *dev) | |
784 | { | |
9d098192 | 785 | struct mei_txe_hw *hw = to_txe_hw(dev); |
92db1555 | 786 | |
9d098192 | 787 | return hw->slots; |
32e2b59f TW |
788 | } |
789 | ||
790 | /** | |
791 | * mei_txe_count_full_read_slots - mimics the me device circular buffer | |
792 | * | |
793 | * @dev: the device structure | |
794 | * | |
a8605ea2 | 795 | * Return: always buffer size in dwords count |
32e2b59f TW |
796 | */ |
797 | static int mei_txe_count_full_read_slots(struct mei_device *dev) | |
798 | { | |
799 | /* read buffers has static size */ | |
800 | return PAYLOAD_SIZE / 4; | |
801 | } | |
802 | ||
803 | /** | |
804 | * mei_txe_read_hdr - read message header which is always in 4 first bytes | |
805 | * | |
806 | * @dev: the device structure | |
807 | * | |
a8605ea2 | 808 | * Return: mei message header |
32e2b59f TW |
809 | */ |
810 | ||
811 | static u32 mei_txe_read_hdr(const struct mei_device *dev) | |
812 | { | |
813 | return mei_txe_out_data_read(dev, 0); | |
814 | } | |
815 | /** | |
816 | * mei_txe_read - reads a message from the txe device. | |
817 | * | |
818 | * @dev: the device structure | |
819 | * @buf: message buffer will be written | |
820 | * @len: message size will be read | |
821 | * | |
a8605ea2 | 822 | * Return: -EINVAL on error wrong argument and 0 on success |
32e2b59f TW |
823 | */ |
824 | static int mei_txe_read(struct mei_device *dev, | |
825 | unsigned char *buf, unsigned long len) | |
826 | { | |
827 | ||
828 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
92db1555 TW |
829 | u32 *reg_buf, reg; |
830 | u32 rem; | |
32e2b59f | 831 | u32 i; |
32e2b59f TW |
832 | |
833 | if (WARN_ON(!buf || !len)) | |
834 | return -EINVAL; | |
835 | ||
92db1555 TW |
836 | reg_buf = (u32 *)buf; |
837 | rem = len & 0x3; | |
838 | ||
2bf94cab | 839 | dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n", |
32e2b59f TW |
840 | len, mei_txe_out_data_read(dev, 0)); |
841 | ||
842 | for (i = 0; i < len / 4; i++) { | |
843 | /* skip header: index starts from 1 */ | |
92db1555 | 844 | reg = mei_txe_out_data_read(dev, i + 1); |
2bf94cab | 845 | dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg); |
32e2b59f TW |
846 | *reg_buf++ = reg; |
847 | } | |
848 | ||
849 | if (rem) { | |
92db1555 | 850 | reg = mei_txe_out_data_read(dev, i + 1); |
32e2b59f TW |
851 | memcpy(reg_buf, ®, rem); |
852 | } | |
853 | ||
854 | mei_txe_output_ready_set(hw); | |
855 | return 0; | |
856 | } | |
857 | ||
858 | /** | |
859 | * mei_txe_hw_reset - resets host and fw. | |
860 | * | |
861 | * @dev: the device structure | |
862 | * @intr_enable: if interrupt should be enabled after reset. | |
863 | * | |
a8605ea2 | 864 | * Return: 0 on success and < 0 in case of error |
32e2b59f TW |
865 | */ |
866 | static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable) | |
867 | { | |
868 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
869 | ||
870 | u32 aliveness_req; | |
871 | /* | |
872 | * read input doorbell to ensure consistency between Bridge and SeC | |
873 | * return value might be garbage return | |
874 | */ | |
875 | (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG); | |
876 | ||
877 | aliveness_req = mei_txe_aliveness_req_get(dev); | |
878 | hw->aliveness = mei_txe_aliveness_get(dev); | |
879 | ||
880 | /* Disable interrupts in this stage we will poll */ | |
881 | mei_txe_intr_disable(dev); | |
882 | ||
883 | /* | |
884 | * If Aliveness Request and Aliveness Response are not equal then | |
885 | * wait for them to be equal | |
886 | * Since we might have interrupts disabled - poll for it | |
887 | */ | |
888 | if (aliveness_req != hw->aliveness) | |
889 | if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) { | |
2bf94cab | 890 | dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n"); |
32e2b59f TW |
891 | return -EIO; |
892 | } | |
893 | ||
894 | /* | |
895 | * If Aliveness Request and Aliveness Response are set then clear them | |
896 | */ | |
897 | if (aliveness_req) { | |
898 | mei_txe_aliveness_set(dev, 0); | |
899 | if (mei_txe_aliveness_poll(dev, 0) < 0) { | |
2bf94cab | 900 | dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); |
32e2b59f TW |
901 | return -EIO; |
902 | } | |
903 | } | |
904 | ||
905 | /* | |
0a01e974 | 906 | * Set readiness RDY_CLR bit |
32e2b59f TW |
907 | */ |
908 | mei_txe_readiness_clear(dev); | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
913 | /** | |
914 | * mei_txe_hw_start - start the hardware after reset | |
915 | * | |
916 | * @dev: the device structure | |
917 | * | |
ce23139c | 918 | * Return: 0 on success an error code otherwise |
32e2b59f TW |
919 | */ |
920 | static int mei_txe_hw_start(struct mei_device *dev) | |
921 | { | |
922 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
923 | int ret; | |
924 | ||
925 | u32 hisr; | |
926 | ||
927 | /* bring back interrupts */ | |
928 | mei_txe_intr_enable(dev); | |
929 | ||
930 | ret = mei_txe_readiness_wait(dev); | |
931 | if (ret < 0) { | |
0a01e974 | 932 | dev_err(dev->dev, "waiting for readiness failed\n"); |
32e2b59f TW |
933 | return ret; |
934 | } | |
935 | ||
936 | /* | |
937 | * If HISR.INT2_STS interrupt status bit is set then clear it. | |
938 | */ | |
939 | hisr = mei_txe_br_reg_read(hw, HISR_REG); | |
940 | if (hisr & HISR_INT_2_STS) | |
941 | mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS); | |
942 | ||
943 | /* Clear the interrupt cause of OutputDoorbell */ | |
944 | clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause); | |
945 | ||
946 | ret = mei_txe_aliveness_set_sync(dev, 1); | |
947 | if (ret < 0) { | |
2bf94cab | 948 | dev_err(dev->dev, "wait for aliveness failed ... bailing out\n"); |
32e2b59f TW |
949 | return ret; |
950 | } | |
951 | ||
77537ad2 AU |
952 | pm_runtime_set_active(dev->dev); |
953 | ||
32e2b59f TW |
954 | /* enable input ready interrupts: |
955 | * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK | |
956 | */ | |
957 | mei_txe_input_ready_interrupt_enable(dev); | |
958 | ||
959 | ||
960 | /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */ | |
961 | mei_txe_output_ready_set(hw); | |
962 | ||
963 | /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY | |
964 | */ | |
965 | mei_txe_readiness_set_host_rdy(dev); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
970 | /** | |
971 | * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into | |
972 | * single bit mask and acknowledge the interrupts | |
973 | * | |
974 | * @dev: the device structure | |
975 | * @do_ack: acknowledge interrupts | |
ce23139c AU |
976 | * |
977 | * Return: true if found interrupts to process. | |
32e2b59f TW |
978 | */ |
979 | static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack) | |
980 | { | |
981 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
982 | u32 hisr; | |
983 | u32 hhisr; | |
984 | u32 ipc_isr; | |
985 | u32 aliveness; | |
986 | bool generated; | |
987 | ||
988 | /* read interrupt registers */ | |
989 | hhisr = mei_txe_br_reg_read(hw, HHISR_REG); | |
990 | generated = (hhisr & IPC_HHIER_MSK); | |
991 | if (!generated) | |
992 | goto out; | |
993 | ||
994 | hisr = mei_txe_br_reg_read(hw, HISR_REG); | |
995 | ||
996 | aliveness = mei_txe_aliveness_get(dev); | |
43605e29 | 997 | if (hhisr & IPC_HHIER_SEC && aliveness) { |
32e2b59f TW |
998 | ipc_isr = mei_txe_sec_reg_read_silent(hw, |
999 | SEC_IPC_HOST_INT_STATUS_REG); | |
43605e29 | 1000 | } else { |
32e2b59f | 1001 | ipc_isr = 0; |
43605e29 AU |
1002 | hhisr &= ~IPC_HHIER_SEC; |
1003 | } | |
32e2b59f TW |
1004 | |
1005 | generated = generated || | |
1006 | (hisr & HISR_INT_STS_MSK) || | |
1007 | (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING); | |
1008 | ||
1009 | if (generated && do_ack) { | |
1010 | /* Save the interrupt causes */ | |
1011 | hw->intr_cause |= hisr & HISR_INT_STS_MSK; | |
1012 | if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY) | |
1013 | hw->intr_cause |= TXE_INTR_IN_READY; | |
1014 | ||
1015 | ||
1016 | mei_txe_intr_disable(dev); | |
1017 | /* Clear the interrupts in hierarchy: | |
1018 | * IPC and Bridge, than the High Level */ | |
1019 | mei_txe_sec_reg_write_silent(hw, | |
1020 | SEC_IPC_HOST_INT_STATUS_REG, ipc_isr); | |
1021 | mei_txe_br_reg_write(hw, HISR_REG, hisr); | |
1022 | mei_txe_br_reg_write(hw, HHISR_REG, hhisr); | |
1023 | } | |
1024 | ||
1025 | out: | |
1026 | return generated; | |
1027 | } | |
1028 | ||
1029 | /** | |
1030 | * mei_txe_irq_quick_handler - The ISR of the MEI device | |
1031 | * | |
1032 | * @irq: The irq number | |
1033 | * @dev_id: pointer to the device structure | |
1034 | * | |
a8605ea2 AU |
1035 | * Return: IRQ_WAKE_THREAD if interrupt is designed for the device |
1036 | * IRQ_NONE otherwise | |
32e2b59f TW |
1037 | */ |
1038 | irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id) | |
1039 | { | |
1040 | struct mei_device *dev = dev_id; | |
1041 | ||
1042 | if (mei_txe_check_and_ack_intrs(dev, true)) | |
1043 | return IRQ_WAKE_THREAD; | |
1044 | return IRQ_NONE; | |
1045 | } | |
1046 | ||
1047 | ||
1048 | /** | |
1049 | * mei_txe_irq_thread_handler - txe interrupt thread | |
1050 | * | |
1051 | * @irq: The irq number | |
1052 | * @dev_id: pointer to the device structure | |
1053 | * | |
a8605ea2 | 1054 | * Return: IRQ_HANDLED |
32e2b59f TW |
1055 | */ |
1056 | irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id) | |
1057 | { | |
1058 | struct mei_device *dev = (struct mei_device *) dev_id; | |
1059 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
1060 | struct mei_cl_cb complete_list; | |
1061 | s32 slots; | |
1062 | int rets = 0; | |
1063 | ||
2bf94cab | 1064 | dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n", |
32e2b59f TW |
1065 | mei_txe_br_reg_read(hw, HHISR_REG), |
1066 | mei_txe_br_reg_read(hw, HISR_REG), | |
1067 | mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG)); | |
1068 | ||
1069 | ||
1070 | /* initialize our complete list */ | |
1071 | mutex_lock(&dev->device_lock); | |
1072 | mei_io_list_init(&complete_list); | |
1073 | ||
d08b8fc0 | 1074 | if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) |
32e2b59f TW |
1075 | mei_txe_check_and_ack_intrs(dev, true); |
1076 | ||
1077 | /* show irq events */ | |
1078 | mei_txe_pending_interrupts(dev); | |
1079 | ||
1080 | hw->aliveness = mei_txe_aliveness_get(dev); | |
1081 | hw->readiness = mei_txe_readiness_get(dev); | |
1082 | ||
1083 | /* Readiness: | |
1084 | * Detection of TXE driver going through reset | |
1085 | * or TXE driver resetting the HECI interface. | |
1086 | */ | |
1087 | if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) { | |
2bf94cab | 1088 | dev_dbg(dev->dev, "Readiness Interrupt was received...\n"); |
32e2b59f TW |
1089 | |
1090 | /* Check if SeC is going through reset */ | |
1091 | if (mei_txe_readiness_is_sec_rdy(hw->readiness)) { | |
2bf94cab | 1092 | dev_dbg(dev->dev, "we need to start the dev.\n"); |
32e2b59f TW |
1093 | dev->recvd_hw_ready = true; |
1094 | } else { | |
1095 | dev->recvd_hw_ready = false; | |
1096 | if (dev->dev_state != MEI_DEV_RESETTING) { | |
1097 | ||
2bf94cab | 1098 | dev_warn(dev->dev, "FW not ready: resetting.\n"); |
32e2b59f TW |
1099 | schedule_work(&dev->reset_work); |
1100 | goto end; | |
1101 | ||
1102 | } | |
1103 | } | |
1104 | wake_up(&dev->wait_hw_ready); | |
1105 | } | |
1106 | ||
1107 | /************************************************************/ | |
1108 | /* Check interrupt cause: | |
1109 | * Aliveness: Detection of SeC acknowledge of host request that | |
1110 | * it remain alive or host cancellation of that request. | |
1111 | */ | |
1112 | ||
1113 | if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) { | |
1114 | /* Clear the interrupt cause */ | |
2bf94cab | 1115 | dev_dbg(dev->dev, |
32e2b59f | 1116 | "Aliveness Interrupt: Status: %d\n", hw->aliveness); |
964a2331 TW |
1117 | dev->pg_event = MEI_PG_EVENT_RECEIVED; |
1118 | if (waitqueue_active(&hw->wait_aliveness_resp)) | |
1119 | wake_up(&hw->wait_aliveness_resp); | |
32e2b59f TW |
1120 | } |
1121 | ||
1122 | ||
1123 | /* Output Doorbell: | |
1124 | * Detection of SeC having sent output to host | |
1125 | */ | |
1126 | slots = mei_count_full_read_slots(dev); | |
1127 | if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) { | |
1128 | /* Read from TXE */ | |
1129 | rets = mei_irq_read_handler(dev, &complete_list, &slots); | |
1130 | if (rets && dev->dev_state != MEI_DEV_RESETTING) { | |
2bf94cab | 1131 | dev_err(dev->dev, |
32e2b59f TW |
1132 | "mei_irq_read_handler ret = %d.\n", rets); |
1133 | ||
1134 | schedule_work(&dev->reset_work); | |
1135 | goto end; | |
1136 | } | |
1137 | } | |
1138 | /* Input Ready: Detection if host can write to SeC */ | |
9d098192 | 1139 | if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) { |
32e2b59f | 1140 | dev->hbuf_is_ready = true; |
9d098192 TW |
1141 | hw->slots = dev->hbuf_depth; |
1142 | } | |
32e2b59f TW |
1143 | |
1144 | if (hw->aliveness && dev->hbuf_is_ready) { | |
6aae48ff TW |
1145 | /* get the real register value */ |
1146 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
32e2b59f | 1147 | rets = mei_irq_write_handler(dev, &complete_list); |
6aae48ff | 1148 | if (rets && rets != -EMSGSIZE) |
2bf94cab | 1149 | dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n", |
6aae48ff TW |
1150 | rets); |
1151 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
32e2b59f TW |
1152 | } |
1153 | ||
32e2b59f TW |
1154 | mei_irq_compl_handler(dev, &complete_list); |
1155 | ||
1156 | end: | |
2bf94cab | 1157 | dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); |
32e2b59f TW |
1158 | |
1159 | mutex_unlock(&dev->device_lock); | |
1160 | ||
1161 | mei_enable_interrupts(dev); | |
1162 | return IRQ_HANDLED; | |
1163 | } | |
1164 | ||
1165 | static const struct mei_hw_ops mei_txe_hw_ops = { | |
1166 | ||
1167 | .host_is_ready = mei_txe_host_is_ready, | |
1168 | ||
1bd30b6a | 1169 | .fw_status = mei_txe_fw_status, |
964a2331 TW |
1170 | .pg_state = mei_txe_pg_state, |
1171 | ||
32e2b59f TW |
1172 | .hw_is_ready = mei_txe_hw_is_ready, |
1173 | .hw_reset = mei_txe_hw_reset, | |
1174 | .hw_config = mei_txe_hw_config, | |
1175 | .hw_start = mei_txe_hw_start, | |
1176 | ||
3dc196ea | 1177 | .pg_in_transition = mei_txe_pg_in_transition, |
ee7e5afd TW |
1178 | .pg_is_enabled = mei_txe_pg_is_enabled, |
1179 | ||
32e2b59f TW |
1180 | .intr_clear = mei_txe_intr_clear, |
1181 | .intr_enable = mei_txe_intr_enable, | |
1182 | .intr_disable = mei_txe_intr_disable, | |
4a8efd4a | 1183 | .synchronize_irq = mei_txe_synchronize_irq, |
32e2b59f TW |
1184 | |
1185 | .hbuf_free_slots = mei_txe_hbuf_empty_slots, | |
1186 | .hbuf_is_ready = mei_txe_is_input_ready, | |
1187 | .hbuf_max_len = mei_txe_hbuf_max_len, | |
1188 | ||
1189 | .write = mei_txe_write, | |
1190 | ||
1191 | .rdbuf_full_slots = mei_txe_count_full_read_slots, | |
1192 | .read_hdr = mei_txe_read_hdr, | |
1193 | ||
1194 | .read = mei_txe_read, | |
1195 | ||
1196 | }; | |
1197 | ||
1198 | /** | |
1199 | * mei_txe_dev_init - allocates and initializes txe hardware specific structure | |
1200 | * | |
ce23139c | 1201 | * @pdev: pci device |
32e2b59f | 1202 | * |
ce23139c | 1203 | * Return: struct mei_device * on success or NULL |
32e2b59f | 1204 | */ |
4ad96db6 | 1205 | struct mei_device *mei_txe_dev_init(struct pci_dev *pdev) |
32e2b59f TW |
1206 | { |
1207 | struct mei_device *dev; | |
1208 | struct mei_txe_hw *hw; | |
1209 | ||
1210 | dev = kzalloc(sizeof(struct mei_device) + | |
1211 | sizeof(struct mei_txe_hw), GFP_KERNEL); | |
1212 | if (!dev) | |
1213 | return NULL; | |
1214 | ||
3a7e9b6c | 1215 | mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops); |
32e2b59f TW |
1216 | |
1217 | hw = to_txe_hw(dev); | |
1218 | ||
964a2331 | 1219 | init_waitqueue_head(&hw->wait_aliveness_resp); |
32e2b59f | 1220 | |
32e2b59f TW |
1221 | return dev; |
1222 | } | |
1223 | ||
1224 | /** | |
1225 | * mei_txe_setup_satt2 - SATT2 configuration for DMA support. | |
1226 | * | |
1227 | * @dev: the device structure | |
1228 | * @addr: physical address start of the range | |
1229 | * @range: physical range size | |
ce23139c AU |
1230 | * |
1231 | * Return: 0 on success an error code otherwise | |
32e2b59f TW |
1232 | */ |
1233 | int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range) | |
1234 | { | |
1235 | struct mei_txe_hw *hw = to_txe_hw(dev); | |
1236 | ||
1237 | u32 lo32 = lower_32_bits(addr); | |
1238 | u32 hi32 = upper_32_bits(addr); | |
1239 | u32 ctrl; | |
1240 | ||
1241 | /* SATT is limited to 36 Bits */ | |
1242 | if (hi32 & ~0xF) | |
1243 | return -EINVAL; | |
1244 | ||
1245 | /* SATT has to be 16Byte aligned */ | |
1246 | if (lo32 & 0xF) | |
1247 | return -EINVAL; | |
1248 | ||
1249 | /* SATT range has to be 4Bytes aligned */ | |
1250 | if (range & 0x4) | |
1251 | return -EINVAL; | |
1252 | ||
1253 | /* SATT is limited to 32 MB range*/ | |
1254 | if (range > SATT_RANGE_MAX) | |
1255 | return -EINVAL; | |
1256 | ||
1257 | ctrl = SATT2_CTRL_VALID_MSK; | |
1258 | ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT; | |
1259 | ||
1260 | mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range); | |
1261 | mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32); | |
1262 | mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl); | |
2bf94cab | 1263 | dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n", |
32e2b59f TW |
1264 | range, lo32, ctrl); |
1265 | ||
1266 | return 0; | |
1267 | } |