Commit | Line | Data |
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9dc64d6a | 1 | /* |
66ef5ea9 | 2 | * |
9dc64d6a TW |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver |
4 | * Copyright (c) 2003-2012, Intel Corporation. | |
66ef5ea9 | 5 | * |
9dc64d6a TW |
6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
66ef5ea9 | 9 | * |
9dc64d6a TW |
10 | * This program is distributed in the hope it will be useful, but WITHOUT |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
66ef5ea9 | 14 | * |
66ef5ea9 | 15 | */ |
66ef5ea9 | 16 | |
66ef5ea9 | 17 | |
66ef5ea9 | 18 | |
9dc64d6a TW |
19 | #ifndef _MEI_INTERFACE_H_ |
20 | #define _MEI_INTERFACE_H_ | |
66ef5ea9 | 21 | |
81ec5502 | 22 | #include <linux/irqreturn.h> |
4ad96db6 TW |
23 | #include <linux/pci.h> |
24 | #include <linux/mei.h> | |
25 | ||
9dc64d6a | 26 | #include "mei_dev.h" |
52c34561 | 27 | #include "client.h" |
66ef5ea9 | 28 | |
4ad96db6 TW |
29 | /* |
30 | * mei_cfg - mei device configuration | |
31 | * | |
32 | * @fw_status: FW status | |
33 | * @quirk_probe: device exclusion quirk | |
34 | */ | |
35 | struct mei_cfg { | |
36 | const struct mei_fw_status fw_status; | |
37 | bool (*quirk_probe)(struct pci_dev *pdev); | |
38 | }; | |
39 | ||
40 | ||
41 | #define MEI_PCI_DEVICE(dev, cfg) \ | |
42 | .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ | |
43 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ | |
44 | .driver_data = (kernel_ulong_t)&(cfg) | |
45 | ||
46 | ||
180ea05b TW |
47 | #define MEI_ME_RPM_TIMEOUT 500 /* ms */ |
48 | ||
4ad96db6 | 49 | /** |
ce23139c AU |
50 | * struct mei_me_hw - me hw specific data |
51 | * | |
4ad96db6 | 52 | * @cfg: per device generation config and ops |
bb9f4d26 AU |
53 | * @mem_addr: io memory address |
54 | * @pg_state: power gating state | |
55 | * @d0i3_supported: di03 support | |
4ad96db6 | 56 | */ |
52c34561 | 57 | struct mei_me_hw { |
4ad96db6 | 58 | const struct mei_cfg *cfg; |
52c34561 | 59 | void __iomem *mem_addr; |
ba9cdd0e | 60 | enum mei_pg_state pg_state; |
bb9f4d26 | 61 | bool d0i3_supported; |
52c34561 | 62 | }; |
66ef5ea9 | 63 | |
52c34561 TW |
64 | #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) |
65 | ||
8d929d48 AU |
66 | extern const struct mei_cfg mei_me_legacy_cfg; |
67 | extern const struct mei_cfg mei_me_ich_cfg; | |
68 | extern const struct mei_cfg mei_me_pch_cfg; | |
c919951d | 69 | extern const struct mei_cfg mei_me_pch_cpt_pbg_cfg; |
edca5ea3 AU |
70 | extern const struct mei_cfg mei_me_pch8_cfg; |
71 | extern const struct mei_cfg mei_me_pch8_sps_cfg; | |
8d929d48 AU |
72 | |
73 | struct mei_device *mei_me_dev_init(struct pci_dev *pdev, | |
74 | const struct mei_cfg *cfg); | |
66ef5ea9 | 75 | |
2d1995fc AU |
76 | int mei_me_pg_enter_sync(struct mei_device *dev); |
77 | int mei_me_pg_exit_sync(struct mei_device *dev); | |
ba9cdd0e | 78 | |
06ecd645 TW |
79 | irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); |
80 | irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); | |
81 | ||
9dc64d6a | 82 | #endif /* _MEI_INTERFACE_H_ */ |