Commit | Line | Data |
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3ce72726 OW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
733ba91c | 4 | * Copyright (c) 2003-2012, Intel Corporation. |
3ce72726 OW |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
06ecd645 TW |
18 | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/interrupt.h> | |
47a73801 TW |
21 | |
22 | #include "mei_dev.h" | |
06ecd645 TW |
23 | #include "hbm.h" |
24 | ||
6e4cd27a TW |
25 | #include "hw-me.h" |
26 | #include "hw-me-regs.h" | |
06ecd645 | 27 | |
3a65dd4e | 28 | /** |
b68301e9 | 29 | * mei_me_reg_read - Reads 32bit data from the mei device |
3a65dd4e | 30 | * |
a8605ea2 | 31 | * @hw: the me hardware structure |
3a65dd4e TW |
32 | * @offset: offset from which to read the data |
33 | * | |
a8605ea2 | 34 | * Return: register value (u32) |
3a65dd4e | 35 | */ |
b68301e9 | 36 | static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, |
3a65dd4e TW |
37 | unsigned long offset) |
38 | { | |
52c34561 | 39 | return ioread32(hw->mem_addr + offset); |
3a65dd4e TW |
40 | } |
41 | ||
42 | ||
43 | /** | |
b68301e9 | 44 | * mei_me_reg_write - Writes 32bit data to the mei device |
3a65dd4e | 45 | * |
a8605ea2 | 46 | * @hw: the me hardware structure |
3a65dd4e TW |
47 | * @offset: offset from which to write the data |
48 | * @value: register value to write (u32) | |
49 | */ | |
b68301e9 | 50 | static inline void mei_me_reg_write(const struct mei_me_hw *hw, |
3a65dd4e TW |
51 | unsigned long offset, u32 value) |
52 | { | |
52c34561 | 53 | iowrite32(value, hw->mem_addr + offset); |
3a65dd4e | 54 | } |
3ce72726 | 55 | |
3a65dd4e | 56 | /** |
b68301e9 | 57 | * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer |
d025284d | 58 | * read window register |
3a65dd4e TW |
59 | * |
60 | * @dev: the device structure | |
61 | * | |
a8605ea2 | 62 | * Return: ME_CB_RW register value (u32) |
3a65dd4e | 63 | */ |
827eef51 | 64 | static u32 mei_me_mecbrw_read(const struct mei_device *dev) |
3a65dd4e | 65 | { |
b68301e9 | 66 | return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); |
3a65dd4e TW |
67 | } |
68 | /** | |
b68301e9 | 69 | * mei_me_mecsr_read - Reads 32bit data from the ME CSR |
3a65dd4e | 70 | * |
a8605ea2 | 71 | * @hw: the me hardware structure |
3a65dd4e | 72 | * |
a8605ea2 | 73 | * Return: ME_CSR_HA register value (u32) |
3a65dd4e | 74 | */ |
b68301e9 | 75 | static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw) |
3a65dd4e | 76 | { |
b68301e9 | 77 | return mei_me_reg_read(hw, ME_CSR_HA); |
3a65dd4e | 78 | } |
3ce72726 OW |
79 | |
80 | /** | |
d025284d TW |
81 | * mei_hcsr_read - Reads 32bit data from the host CSR |
82 | * | |
a8605ea2 | 83 | * @hw: the me hardware structure |
d025284d | 84 | * |
a8605ea2 | 85 | * Return: H_CSR register value (u32) |
d025284d | 86 | */ |
52c34561 | 87 | static inline u32 mei_hcsr_read(const struct mei_me_hw *hw) |
d025284d | 88 | { |
b68301e9 | 89 | return mei_me_reg_read(hw, H_CSR); |
d025284d TW |
90 | } |
91 | ||
92 | /** | |
93 | * mei_hcsr_set - writes H_CSR register to the mei device, | |
3ce72726 OW |
94 | * and ignores the H_IS bit for it is write-one-to-zero. |
95 | * | |
a8605ea2 | 96 | * @hw: the me hardware structure |
3ce72726 | 97 | */ |
52c34561 | 98 | static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr) |
3ce72726 | 99 | { |
88eb99f2 | 100 | hcsr &= ~H_IS; |
b68301e9 | 101 | mei_me_reg_write(hw, H_CSR, hcsr); |
3ce72726 OW |
102 | } |
103 | ||
1bd30b6a TW |
104 | /** |
105 | * mei_me_fw_status - read fw status register from pci config space | |
106 | * | |
107 | * @dev: mei device | |
108 | * @fw_status: fw status register values | |
109 | */ | |
110 | static int mei_me_fw_status(struct mei_device *dev, | |
111 | struct mei_fw_status *fw_status) | |
112 | { | |
1bd30b6a | 113 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
4ad96db6 TW |
114 | struct mei_me_hw *hw = to_me_hw(dev); |
115 | const struct mei_fw_status *fw_src = &hw->cfg->fw_status; | |
1bd30b6a TW |
116 | int ret; |
117 | int i; | |
118 | ||
119 | if (!fw_status) | |
120 | return -EINVAL; | |
121 | ||
122 | fw_status->count = fw_src->count; | |
123 | for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { | |
124 | ret = pci_read_config_dword(pdev, | |
125 | fw_src->status[i], &fw_status->status[i]); | |
126 | if (ret) | |
127 | return ret; | |
128 | } | |
129 | ||
130 | return 0; | |
131 | } | |
e7e0c231 TW |
132 | |
133 | /** | |
393b148f | 134 | * mei_me_hw_config - configure hw dependent settings |
e7e0c231 TW |
135 | * |
136 | * @dev: mei device | |
137 | */ | |
827eef51 | 138 | static void mei_me_hw_config(struct mei_device *dev) |
e7e0c231 | 139 | { |
ba9cdd0e | 140 | struct mei_me_hw *hw = to_me_hw(dev); |
52c34561 | 141 | u32 hcsr = mei_hcsr_read(to_me_hw(dev)); |
e7e0c231 TW |
142 | /* Doesn't change in runtime */ |
143 | dev->hbuf_depth = (hcsr & H_CBD) >> 24; | |
ba9cdd0e TW |
144 | |
145 | hw->pg_state = MEI_PG_OFF; | |
e7e0c231 | 146 | } |
964a2331 TW |
147 | |
148 | /** | |
149 | * mei_me_pg_state - translate internal pg state | |
150 | * to the mei power gating state | |
151 | * | |
152 | * @hw - me hardware | |
153 | * returns: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise | |
154 | */ | |
155 | static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) | |
156 | { | |
ba9cdd0e | 157 | struct mei_me_hw *hw = to_me_hw(dev); |
92db1555 | 158 | |
ba9cdd0e | 159 | return hw->pg_state; |
964a2331 TW |
160 | } |
161 | ||
3ce72726 | 162 | /** |
d025284d | 163 | * mei_clear_interrupts - clear and stop interrupts |
3a65dd4e TW |
164 | * |
165 | * @dev: the device structure | |
166 | */ | |
827eef51 | 167 | static void mei_me_intr_clear(struct mei_device *dev) |
3a65dd4e | 168 | { |
52c34561 TW |
169 | struct mei_me_hw *hw = to_me_hw(dev); |
170 | u32 hcsr = mei_hcsr_read(hw); | |
92db1555 | 171 | |
9ea73ddd | 172 | if ((hcsr & H_IS) == H_IS) |
b68301e9 | 173 | mei_me_reg_write(hw, H_CSR, hcsr); |
3a65dd4e | 174 | } |
3a65dd4e | 175 | /** |
827eef51 | 176 | * mei_me_intr_enable - enables mei device interrupts |
3ce72726 OW |
177 | * |
178 | * @dev: the device structure | |
179 | */ | |
827eef51 | 180 | static void mei_me_intr_enable(struct mei_device *dev) |
3ce72726 | 181 | { |
52c34561 TW |
182 | struct mei_me_hw *hw = to_me_hw(dev); |
183 | u32 hcsr = mei_hcsr_read(hw); | |
92db1555 | 184 | |
9ea73ddd | 185 | hcsr |= H_IE; |
52c34561 | 186 | mei_hcsr_set(hw, hcsr); |
3ce72726 OW |
187 | } |
188 | ||
189 | /** | |
3a65dd4e | 190 | * mei_disable_interrupts - disables mei device interrupts |
3ce72726 OW |
191 | * |
192 | * @dev: the device structure | |
193 | */ | |
827eef51 | 194 | static void mei_me_intr_disable(struct mei_device *dev) |
3ce72726 | 195 | { |
52c34561 TW |
196 | struct mei_me_hw *hw = to_me_hw(dev); |
197 | u32 hcsr = mei_hcsr_read(hw); | |
92db1555 | 198 | |
9ea73ddd | 199 | hcsr &= ~H_IE; |
52c34561 | 200 | mei_hcsr_set(hw, hcsr); |
3ce72726 OW |
201 | } |
202 | ||
68f8ea18 TW |
203 | /** |
204 | * mei_me_hw_reset_release - release device from the reset | |
205 | * | |
206 | * @dev: the device structure | |
207 | */ | |
208 | static void mei_me_hw_reset_release(struct mei_device *dev) | |
209 | { | |
210 | struct mei_me_hw *hw = to_me_hw(dev); | |
211 | u32 hcsr = mei_hcsr_read(hw); | |
212 | ||
213 | hcsr |= H_IG; | |
214 | hcsr &= ~H_RST; | |
215 | mei_hcsr_set(hw, hcsr); | |
b04ada92 TW |
216 | |
217 | /* complete this write before we set host ready on another CPU */ | |
218 | mmiowb(); | |
68f8ea18 | 219 | } |
adfba322 | 220 | /** |
827eef51 | 221 | * mei_me_hw_reset - resets fw via mei csr register. |
adfba322 TW |
222 | * |
223 | * @dev: the device structure | |
393b148f | 224 | * @intr_enable: if interrupt should be enabled after reset. |
adfba322 | 225 | */ |
c20c68d5 | 226 | static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) |
adfba322 | 227 | { |
52c34561 TW |
228 | struct mei_me_hw *hw = to_me_hw(dev); |
229 | u32 hcsr = mei_hcsr_read(hw); | |
adfba322 | 230 | |
ff96066e | 231 | hcsr |= H_RST | H_IG | H_IS; |
adfba322 TW |
232 | |
233 | if (intr_enable) | |
234 | hcsr |= H_IE; | |
235 | else | |
ff96066e | 236 | hcsr &= ~H_IE; |
adfba322 | 237 | |
07cd7be3 | 238 | dev->recvd_hw_ready = false; |
ff96066e | 239 | mei_me_reg_write(hw, H_CSR, hcsr); |
adfba322 | 240 | |
c40765d9 TW |
241 | /* |
242 | * Host reads the H_CSR once to ensure that the | |
243 | * posted write to H_CSR completes. | |
244 | */ | |
245 | hcsr = mei_hcsr_read(hw); | |
246 | ||
247 | if ((hcsr & H_RST) == 0) | |
2bf94cab | 248 | dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); |
c40765d9 TW |
249 | |
250 | if ((hcsr & H_RDY) == H_RDY) | |
2bf94cab | 251 | dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); |
c40765d9 | 252 | |
33ec0826 | 253 | if (intr_enable == false) |
68f8ea18 | 254 | mei_me_hw_reset_release(dev); |
adfba322 | 255 | |
c20c68d5 | 256 | return 0; |
adfba322 TW |
257 | } |
258 | ||
115ba28c | 259 | /** |
827eef51 | 260 | * mei_me_host_set_ready - enable device |
115ba28c TW |
261 | * |
262 | * @dev - mei device | |
263 | * returns bool | |
264 | */ | |
265 | ||
827eef51 | 266 | static void mei_me_host_set_ready(struct mei_device *dev) |
115ba28c | 267 | { |
52c34561 | 268 | struct mei_me_hw *hw = to_me_hw(dev); |
92db1555 | 269 | |
b04ada92 | 270 | hw->host_hw_state = mei_hcsr_read(hw); |
52c34561 TW |
271 | hw->host_hw_state |= H_IE | H_IG | H_RDY; |
272 | mei_hcsr_set(hw, hw->host_hw_state); | |
115ba28c TW |
273 | } |
274 | /** | |
827eef51 | 275 | * mei_me_host_is_ready - check whether the host has turned ready |
115ba28c | 276 | * |
a8605ea2 AU |
277 | * @dev: mei device |
278 | * Return: bool | |
115ba28c | 279 | */ |
827eef51 | 280 | static bool mei_me_host_is_ready(struct mei_device *dev) |
115ba28c | 281 | { |
52c34561 | 282 | struct mei_me_hw *hw = to_me_hw(dev); |
92db1555 | 283 | |
52c34561 TW |
284 | hw->host_hw_state = mei_hcsr_read(hw); |
285 | return (hw->host_hw_state & H_RDY) == H_RDY; | |
115ba28c TW |
286 | } |
287 | ||
288 | /** | |
827eef51 | 289 | * mei_me_hw_is_ready - check whether the me(hw) has turned ready |
115ba28c | 290 | * |
a8605ea2 AU |
291 | * @dev: mei device |
292 | * Return: bool | |
115ba28c | 293 | */ |
827eef51 | 294 | static bool mei_me_hw_is_ready(struct mei_device *dev) |
115ba28c | 295 | { |
52c34561 | 296 | struct mei_me_hw *hw = to_me_hw(dev); |
92db1555 | 297 | |
b68301e9 | 298 | hw->me_hw_state = mei_me_mecsr_read(hw); |
52c34561 | 299 | return (hw->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA; |
115ba28c | 300 | } |
3a65dd4e | 301 | |
aafae7ec TW |
302 | static int mei_me_hw_ready_wait(struct mei_device *dev) |
303 | { | |
aafae7ec | 304 | mutex_unlock(&dev->device_lock); |
2c2b93ec | 305 | wait_event_timeout(dev->wait_hw_ready, |
dab9bf41 | 306 | dev->recvd_hw_ready, |
7d93e58d | 307 | mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); |
aafae7ec | 308 | mutex_lock(&dev->device_lock); |
2c2b93ec | 309 | if (!dev->recvd_hw_ready) { |
2bf94cab | 310 | dev_err(dev->dev, "wait hw ready failed\n"); |
2c2b93ec | 311 | return -ETIME; |
aafae7ec TW |
312 | } |
313 | ||
314 | dev->recvd_hw_ready = false; | |
315 | return 0; | |
316 | } | |
317 | ||
318 | static int mei_me_hw_start(struct mei_device *dev) | |
319 | { | |
320 | int ret = mei_me_hw_ready_wait(dev); | |
92db1555 | 321 | |
aafae7ec TW |
322 | if (ret) |
323 | return ret; | |
2bf94cab | 324 | dev_dbg(dev->dev, "hw is ready\n"); |
aafae7ec TW |
325 | |
326 | mei_me_host_set_ready(dev); | |
327 | return ret; | |
328 | } | |
329 | ||
330 | ||
3ce72726 | 331 | /** |
726917f0 | 332 | * mei_hbuf_filled_slots - gets number of device filled buffer slots |
3ce72726 | 333 | * |
7353f85c | 334 | * @dev: the device structure |
3ce72726 | 335 | * |
a8605ea2 | 336 | * Return: number of filled slots |
3ce72726 | 337 | */ |
726917f0 | 338 | static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) |
3ce72726 | 339 | { |
52c34561 | 340 | struct mei_me_hw *hw = to_me_hw(dev); |
3ce72726 OW |
341 | char read_ptr, write_ptr; |
342 | ||
52c34561 | 343 | hw->host_hw_state = mei_hcsr_read(hw); |
726917f0 | 344 | |
52c34561 TW |
345 | read_ptr = (char) ((hw->host_hw_state & H_CBRP) >> 8); |
346 | write_ptr = (char) ((hw->host_hw_state & H_CBWP) >> 16); | |
3ce72726 OW |
347 | |
348 | return (unsigned char) (write_ptr - read_ptr); | |
349 | } | |
350 | ||
351 | /** | |
393b148f | 352 | * mei_me_hbuf_is_empty - checks if host buffer is empty. |
3ce72726 OW |
353 | * |
354 | * @dev: the device structure | |
355 | * | |
a8605ea2 | 356 | * Return: true if empty, false - otherwise. |
3ce72726 | 357 | */ |
827eef51 | 358 | static bool mei_me_hbuf_is_empty(struct mei_device *dev) |
3ce72726 | 359 | { |
726917f0 | 360 | return mei_hbuf_filled_slots(dev) == 0; |
3ce72726 OW |
361 | } |
362 | ||
363 | /** | |
827eef51 | 364 | * mei_me_hbuf_empty_slots - counts write empty slots. |
3ce72726 OW |
365 | * |
366 | * @dev: the device structure | |
367 | * | |
a8605ea2 | 368 | * Return: -EOVERFLOW if overflow, otherwise empty slots count |
3ce72726 | 369 | */ |
827eef51 | 370 | static int mei_me_hbuf_empty_slots(struct mei_device *dev) |
3ce72726 | 371 | { |
24aadc80 | 372 | unsigned char filled_slots, empty_slots; |
3ce72726 | 373 | |
726917f0 | 374 | filled_slots = mei_hbuf_filled_slots(dev); |
24aadc80 | 375 | empty_slots = dev->hbuf_depth - filled_slots; |
3ce72726 OW |
376 | |
377 | /* check for overflow */ | |
24aadc80 | 378 | if (filled_slots > dev->hbuf_depth) |
3ce72726 OW |
379 | return -EOVERFLOW; |
380 | ||
381 | return empty_slots; | |
382 | } | |
383 | ||
827eef51 TW |
384 | static size_t mei_me_hbuf_max_len(const struct mei_device *dev) |
385 | { | |
386 | return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); | |
387 | } | |
388 | ||
389 | ||
3ce72726 | 390 | /** |
7ca96aa2 | 391 | * mei_me_write_message - writes a message to mei device. |
3ce72726 OW |
392 | * |
393 | * @dev: the device structure | |
7353f85c | 394 | * @header: mei HECI header of message |
438763f3 | 395 | * @buf: message payload will be written |
3ce72726 | 396 | * |
a8605ea2 | 397 | * Return: -EIO if write has failed |
3ce72726 | 398 | */ |
827eef51 TW |
399 | static int mei_me_write_message(struct mei_device *dev, |
400 | struct mei_msg_hdr *header, | |
401 | unsigned char *buf) | |
3ce72726 | 402 | { |
52c34561 | 403 | struct mei_me_hw *hw = to_me_hw(dev); |
c8c8d080 | 404 | unsigned long rem; |
438763f3 | 405 | unsigned long length = header->length; |
169d1338 | 406 | u32 *reg_buf = (u32 *)buf; |
88eb99f2 | 407 | u32 hcsr; |
c8c8d080 | 408 | u32 dw_cnt; |
169d1338 TW |
409 | int i; |
410 | int empty_slots; | |
3ce72726 | 411 | |
2bf94cab | 412 | dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); |
3ce72726 | 413 | |
726917f0 | 414 | empty_slots = mei_hbuf_empty_slots(dev); |
2bf94cab | 415 | dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); |
3ce72726 | 416 | |
7bdf72d3 | 417 | dw_cnt = mei_data2slots(length); |
169d1338 | 418 | if (empty_slots < 0 || dw_cnt > empty_slots) |
9d098192 | 419 | return -EMSGSIZE; |
3ce72726 | 420 | |
b68301e9 | 421 | mei_me_reg_write(hw, H_CB_WW, *((u32 *) header)); |
3ce72726 | 422 | |
169d1338 | 423 | for (i = 0; i < length / 4; i++) |
b68301e9 | 424 | mei_me_reg_write(hw, H_CB_WW, reg_buf[i]); |
3ce72726 | 425 | |
169d1338 TW |
426 | rem = length & 0x3; |
427 | if (rem > 0) { | |
428 | u32 reg = 0; | |
92db1555 | 429 | |
169d1338 | 430 | memcpy(®, &buf[length - rem], rem); |
b68301e9 | 431 | mei_me_reg_write(hw, H_CB_WW, reg); |
3ce72726 OW |
432 | } |
433 | ||
52c34561 TW |
434 | hcsr = mei_hcsr_read(hw) | H_IG; |
435 | mei_hcsr_set(hw, hcsr); | |
827eef51 | 436 | if (!mei_me_hw_is_ready(dev)) |
1ccb7b62 | 437 | return -EIO; |
3ce72726 | 438 | |
1ccb7b62 | 439 | return 0; |
3ce72726 OW |
440 | } |
441 | ||
442 | /** | |
827eef51 | 443 | * mei_me_count_full_read_slots - counts read full slots. |
3ce72726 OW |
444 | * |
445 | * @dev: the device structure | |
446 | * | |
a8605ea2 | 447 | * Return: -EOVERFLOW if overflow, otherwise filled slots count |
3ce72726 | 448 | */ |
827eef51 | 449 | static int mei_me_count_full_read_slots(struct mei_device *dev) |
3ce72726 | 450 | { |
52c34561 | 451 | struct mei_me_hw *hw = to_me_hw(dev); |
3ce72726 OW |
452 | char read_ptr, write_ptr; |
453 | unsigned char buffer_depth, filled_slots; | |
454 | ||
b68301e9 | 455 | hw->me_hw_state = mei_me_mecsr_read(hw); |
52c34561 TW |
456 | buffer_depth = (unsigned char)((hw->me_hw_state & ME_CBD_HRA) >> 24); |
457 | read_ptr = (char) ((hw->me_hw_state & ME_CBRP_HRA) >> 8); | |
458 | write_ptr = (char) ((hw->me_hw_state & ME_CBWP_HRA) >> 16); | |
3ce72726 OW |
459 | filled_slots = (unsigned char) (write_ptr - read_ptr); |
460 | ||
461 | /* check for overflow */ | |
462 | if (filled_slots > buffer_depth) | |
463 | return -EOVERFLOW; | |
464 | ||
2bf94cab | 465 | dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); |
3ce72726 OW |
466 | return (int)filled_slots; |
467 | } | |
468 | ||
469 | /** | |
827eef51 | 470 | * mei_me_read_slots - reads a message from mei device. |
3ce72726 OW |
471 | * |
472 | * @dev: the device structure | |
473 | * @buffer: message buffer will be written | |
474 | * @buffer_length: message size will be read | |
475 | */ | |
827eef51 | 476 | static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, |
edf1eed4 | 477 | unsigned long buffer_length) |
3ce72726 | 478 | { |
52c34561 | 479 | struct mei_me_hw *hw = to_me_hw(dev); |
edf1eed4 | 480 | u32 *reg_buf = (u32 *)buffer; |
88eb99f2 | 481 | u32 hcsr; |
3ce72726 | 482 | |
edf1eed4 | 483 | for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32)) |
827eef51 | 484 | *reg_buf++ = mei_me_mecbrw_read(dev); |
3ce72726 OW |
485 | |
486 | if (buffer_length > 0) { | |
827eef51 | 487 | u32 reg = mei_me_mecbrw_read(dev); |
92db1555 | 488 | |
edf1eed4 | 489 | memcpy(reg_buf, ®, buffer_length); |
3ce72726 OW |
490 | } |
491 | ||
52c34561 TW |
492 | hcsr = mei_hcsr_read(hw) | H_IG; |
493 | mei_hcsr_set(hw, hcsr); | |
827eef51 | 494 | return 0; |
3ce72726 OW |
495 | } |
496 | ||
b16c3571 | 497 | /** |
152de90d | 498 | * mei_me_pg_enter - write pg enter register |
b16c3571 TW |
499 | * |
500 | * @dev: the device structure | |
501 | */ | |
502 | static void mei_me_pg_enter(struct mei_device *dev) | |
503 | { | |
504 | struct mei_me_hw *hw = to_me_hw(dev); | |
505 | u32 reg = mei_me_reg_read(hw, H_HPG_CSR); | |
92db1555 | 506 | |
b16c3571 TW |
507 | reg |= H_HPG_CSR_PGI; |
508 | mei_me_reg_write(hw, H_HPG_CSR, reg); | |
509 | } | |
510 | ||
511 | /** | |
152de90d | 512 | * mei_me_pg_exit - write pg exit register |
b16c3571 TW |
513 | * |
514 | * @dev: the device structure | |
515 | */ | |
516 | static void mei_me_pg_exit(struct mei_device *dev) | |
517 | { | |
518 | struct mei_me_hw *hw = to_me_hw(dev); | |
519 | u32 reg = mei_me_reg_read(hw, H_HPG_CSR); | |
520 | ||
521 | WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); | |
522 | ||
523 | reg |= H_HPG_CSR_PGIHEXR; | |
524 | mei_me_reg_write(hw, H_HPG_CSR, reg); | |
525 | } | |
526 | ||
ba9cdd0e TW |
527 | /** |
528 | * mei_me_pg_set_sync - perform pg entry procedure | |
529 | * | |
530 | * @dev: the device structure | |
531 | * | |
a8605ea2 | 532 | * Return: 0 on success an error code otherwise |
ba9cdd0e TW |
533 | */ |
534 | int mei_me_pg_set_sync(struct mei_device *dev) | |
535 | { | |
536 | struct mei_me_hw *hw = to_me_hw(dev); | |
537 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); | |
538 | int ret; | |
539 | ||
540 | dev->pg_event = MEI_PG_EVENT_WAIT; | |
541 | ||
542 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); | |
543 | if (ret) | |
544 | return ret; | |
545 | ||
546 | mutex_unlock(&dev->device_lock); | |
547 | wait_event_timeout(dev->wait_pg, | |
548 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
549 | mutex_lock(&dev->device_lock); | |
550 | ||
551 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { | |
552 | mei_me_pg_enter(dev); | |
553 | ret = 0; | |
554 | } else { | |
555 | ret = -ETIME; | |
556 | } | |
557 | ||
558 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
559 | hw->pg_state = MEI_PG_ON; | |
560 | ||
561 | return ret; | |
562 | } | |
563 | ||
564 | /** | |
565 | * mei_me_pg_unset_sync - perform pg exit procedure | |
566 | * | |
567 | * @dev: the device structure | |
568 | * | |
a8605ea2 | 569 | * Return: 0 on success an error code otherwise |
ba9cdd0e TW |
570 | */ |
571 | int mei_me_pg_unset_sync(struct mei_device *dev) | |
572 | { | |
573 | struct mei_me_hw *hw = to_me_hw(dev); | |
574 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); | |
575 | int ret; | |
576 | ||
577 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) | |
578 | goto reply; | |
579 | ||
580 | dev->pg_event = MEI_PG_EVENT_WAIT; | |
581 | ||
582 | mei_me_pg_exit(dev); | |
583 | ||
584 | mutex_unlock(&dev->device_lock); | |
585 | wait_event_timeout(dev->wait_pg, | |
586 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
587 | mutex_lock(&dev->device_lock); | |
588 | ||
589 | reply: | |
590 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) | |
591 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); | |
592 | else | |
593 | ret = -ETIME; | |
594 | ||
595 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
596 | hw->pg_state = MEI_PG_OFF; | |
597 | ||
598 | return ret; | |
599 | } | |
600 | ||
ee7e5afd TW |
601 | /** |
602 | * mei_me_pg_is_enabled - detect if PG is supported by HW | |
603 | * | |
604 | * @dev: the device structure | |
605 | * | |
a8605ea2 | 606 | * Return: true is pg supported, false otherwise |
ee7e5afd TW |
607 | */ |
608 | static bool mei_me_pg_is_enabled(struct mei_device *dev) | |
609 | { | |
610 | struct mei_me_hw *hw = to_me_hw(dev); | |
611 | u32 reg = mei_me_reg_read(hw, ME_CSR_HA); | |
612 | ||
613 | if ((reg & ME_PGIC_HRA) == 0) | |
614 | goto notsupported; | |
615 | ||
bae1cc7d | 616 | if (!dev->hbm_f_pg_supported) |
ee7e5afd TW |
617 | goto notsupported; |
618 | ||
619 | return true; | |
620 | ||
621 | notsupported: | |
2bf94cab | 622 | dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n", |
ee7e5afd TW |
623 | !!(reg & ME_PGIC_HRA), |
624 | dev->version.major_version, | |
625 | dev->version.minor_version, | |
626 | HBM_MAJOR_VERSION_PGI, | |
627 | HBM_MINOR_VERSION_PGI); | |
628 | ||
629 | return false; | |
630 | } | |
631 | ||
06ecd645 TW |
632 | /** |
633 | * mei_me_irq_quick_handler - The ISR of the MEI device | |
634 | * | |
635 | * @irq: The irq number | |
636 | * @dev_id: pointer to the device structure | |
637 | * | |
a8605ea2 | 638 | * Return: irqreturn_t |
06ecd645 TW |
639 | */ |
640 | ||
641 | irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) | |
642 | { | |
643 | struct mei_device *dev = (struct mei_device *) dev_id; | |
644 | struct mei_me_hw *hw = to_me_hw(dev); | |
645 | u32 csr_reg = mei_hcsr_read(hw); | |
646 | ||
647 | if ((csr_reg & H_IS) != H_IS) | |
648 | return IRQ_NONE; | |
649 | ||
650 | /* clear H_IS bit in H_CSR */ | |
b68301e9 | 651 | mei_me_reg_write(hw, H_CSR, csr_reg); |
06ecd645 TW |
652 | |
653 | return IRQ_WAKE_THREAD; | |
654 | } | |
655 | ||
656 | /** | |
657 | * mei_me_irq_thread_handler - function called after ISR to handle the interrupt | |
658 | * processing. | |
659 | * | |
660 | * @irq: The irq number | |
661 | * @dev_id: pointer to the device structure | |
662 | * | |
a8605ea2 | 663 | * Return: irqreturn_t |
06ecd645 TW |
664 | * |
665 | */ | |
666 | irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) | |
667 | { | |
668 | struct mei_device *dev = (struct mei_device *) dev_id; | |
669 | struct mei_cl_cb complete_list; | |
06ecd645 | 670 | s32 slots; |
544f9460 | 671 | int rets = 0; |
06ecd645 | 672 | |
2bf94cab | 673 | dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); |
06ecd645 TW |
674 | /* initialize our complete list */ |
675 | mutex_lock(&dev->device_lock); | |
676 | mei_io_list_init(&complete_list); | |
677 | ||
678 | /* Ack the interrupt here | |
679 | * In case of MSI we don't go through the quick handler */ | |
d08b8fc0 | 680 | if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) |
06ecd645 TW |
681 | mei_clear_interrupts(dev); |
682 | ||
683 | /* check if ME wants a reset */ | |
33ec0826 | 684 | if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { |
2bf94cab | 685 | dev_warn(dev->dev, "FW not ready: resetting.\n"); |
544f9460 TW |
686 | schedule_work(&dev->reset_work); |
687 | goto end; | |
06ecd645 TW |
688 | } |
689 | ||
690 | /* check if we need to start the dev */ | |
691 | if (!mei_host_is_ready(dev)) { | |
692 | if (mei_hw_is_ready(dev)) { | |
b04ada92 | 693 | mei_me_hw_reset_release(dev); |
2bf94cab | 694 | dev_dbg(dev->dev, "we need to start the dev.\n"); |
06ecd645 | 695 | |
aafae7ec | 696 | dev->recvd_hw_ready = true; |
2c2b93ec | 697 | wake_up(&dev->wait_hw_ready); |
06ecd645 | 698 | } else { |
2bf94cab | 699 | dev_dbg(dev->dev, "Spurious Interrupt\n"); |
06ecd645 | 700 | } |
544f9460 | 701 | goto end; |
06ecd645 TW |
702 | } |
703 | /* check slots available for reading */ | |
704 | slots = mei_count_full_read_slots(dev); | |
705 | while (slots > 0) { | |
2bf94cab | 706 | dev_dbg(dev->dev, "slots to read = %08x\n", slots); |
06ecd645 | 707 | rets = mei_irq_read_handler(dev, &complete_list, &slots); |
b1b94b5d TW |
708 | /* There is a race between ME write and interrupt delivery: |
709 | * Not all data is always available immediately after the | |
710 | * interrupt, so try to read again on the next interrupt. | |
711 | */ | |
712 | if (rets == -ENODATA) | |
713 | break; | |
714 | ||
33ec0826 | 715 | if (rets && dev->dev_state != MEI_DEV_RESETTING) { |
2bf94cab | 716 | dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", |
b1b94b5d | 717 | rets); |
544f9460 | 718 | schedule_work(&dev->reset_work); |
06ecd645 | 719 | goto end; |
544f9460 | 720 | } |
06ecd645 | 721 | } |
544f9460 | 722 | |
6aae48ff TW |
723 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); |
724 | ||
ba9cdd0e TW |
725 | /* |
726 | * During PG handshake only allowed write is the replay to the | |
727 | * PG exit message, so block calling write function | |
728 | * if the pg state is not idle | |
729 | */ | |
730 | if (dev->pg_event == MEI_PG_EVENT_IDLE) { | |
731 | rets = mei_irq_write_handler(dev, &complete_list); | |
732 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
733 | } | |
06ecd645 | 734 | |
4c6e22b8 | 735 | mei_irq_compl_handler(dev, &complete_list); |
06ecd645 | 736 | |
544f9460 | 737 | end: |
2bf94cab | 738 | dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); |
544f9460 | 739 | mutex_unlock(&dev->device_lock); |
06ecd645 TW |
740 | return IRQ_HANDLED; |
741 | } | |
04dd3661 | 742 | |
827eef51 TW |
743 | static const struct mei_hw_ops mei_me_hw_ops = { |
744 | ||
1bd30b6a | 745 | .fw_status = mei_me_fw_status, |
964a2331 TW |
746 | .pg_state = mei_me_pg_state, |
747 | ||
827eef51 TW |
748 | .host_is_ready = mei_me_host_is_ready, |
749 | ||
750 | .hw_is_ready = mei_me_hw_is_ready, | |
751 | .hw_reset = mei_me_hw_reset, | |
aafae7ec TW |
752 | .hw_config = mei_me_hw_config, |
753 | .hw_start = mei_me_hw_start, | |
827eef51 | 754 | |
ee7e5afd TW |
755 | .pg_is_enabled = mei_me_pg_is_enabled, |
756 | ||
827eef51 TW |
757 | .intr_clear = mei_me_intr_clear, |
758 | .intr_enable = mei_me_intr_enable, | |
759 | .intr_disable = mei_me_intr_disable, | |
760 | ||
761 | .hbuf_free_slots = mei_me_hbuf_empty_slots, | |
762 | .hbuf_is_ready = mei_me_hbuf_is_empty, | |
763 | .hbuf_max_len = mei_me_hbuf_max_len, | |
764 | ||
765 | .write = mei_me_write_message, | |
766 | ||
767 | .rdbuf_full_slots = mei_me_count_full_read_slots, | |
768 | .read_hdr = mei_me_mecbrw_read, | |
769 | .read = mei_me_read_slots | |
770 | }; | |
771 | ||
c919951d TW |
772 | static bool mei_me_fw_type_nm(struct pci_dev *pdev) |
773 | { | |
774 | u32 reg; | |
92db1555 | 775 | |
c919951d TW |
776 | pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); |
777 | /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ | |
778 | return (reg & 0x600) == 0x200; | |
779 | } | |
780 | ||
781 | #define MEI_CFG_FW_NM \ | |
782 | .quirk_probe = mei_me_fw_type_nm | |
783 | ||
784 | static bool mei_me_fw_type_sps(struct pci_dev *pdev) | |
785 | { | |
786 | u32 reg; | |
787 | /* Read ME FW Status check for SPS Firmware */ | |
788 | pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); | |
789 | /* if bits [19:16] = 15, running SPS Firmware */ | |
790 | return (reg & 0xf0000) == 0xf0000; | |
791 | } | |
792 | ||
793 | #define MEI_CFG_FW_SPS \ | |
794 | .quirk_probe = mei_me_fw_type_sps | |
795 | ||
796 | ||
8d929d48 AU |
797 | #define MEI_CFG_LEGACY_HFS \ |
798 | .fw_status.count = 0 | |
799 | ||
800 | #define MEI_CFG_ICH_HFS \ | |
801 | .fw_status.count = 1, \ | |
802 | .fw_status.status[0] = PCI_CFG_HFS_1 | |
803 | ||
804 | #define MEI_CFG_PCH_HFS \ | |
805 | .fw_status.count = 2, \ | |
806 | .fw_status.status[0] = PCI_CFG_HFS_1, \ | |
807 | .fw_status.status[1] = PCI_CFG_HFS_2 | |
808 | ||
809 | ||
810 | /* ICH Legacy devices */ | |
811 | const struct mei_cfg mei_me_legacy_cfg = { | |
812 | MEI_CFG_LEGACY_HFS, | |
813 | }; | |
814 | ||
815 | /* ICH devices */ | |
816 | const struct mei_cfg mei_me_ich_cfg = { | |
817 | MEI_CFG_ICH_HFS, | |
818 | }; | |
819 | ||
820 | /* PCH devices */ | |
821 | const struct mei_cfg mei_me_pch_cfg = { | |
822 | MEI_CFG_PCH_HFS, | |
823 | }; | |
824 | ||
c919951d TW |
825 | |
826 | /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ | |
827 | const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { | |
828 | MEI_CFG_PCH_HFS, | |
829 | MEI_CFG_FW_NM, | |
830 | }; | |
831 | ||
832 | /* PCH Lynx Point with quirk for SPS Firmware exclusion */ | |
833 | const struct mei_cfg mei_me_lpt_cfg = { | |
834 | MEI_CFG_PCH_HFS, | |
835 | MEI_CFG_FW_SPS, | |
836 | }; | |
837 | ||
52c34561 | 838 | /** |
393b148f | 839 | * mei_me_dev_init - allocates and initializes the mei device structure |
52c34561 TW |
840 | * |
841 | * @pdev: The pci device structure | |
8d929d48 | 842 | * @cfg: per device generation config |
52c34561 | 843 | * |
a8605ea2 | 844 | * Return: The mei_device_device pointer on success, NULL on failure. |
52c34561 | 845 | */ |
8d929d48 AU |
846 | struct mei_device *mei_me_dev_init(struct pci_dev *pdev, |
847 | const struct mei_cfg *cfg) | |
52c34561 TW |
848 | { |
849 | struct mei_device *dev; | |
4ad96db6 | 850 | struct mei_me_hw *hw; |
52c34561 TW |
851 | |
852 | dev = kzalloc(sizeof(struct mei_device) + | |
853 | sizeof(struct mei_me_hw), GFP_KERNEL); | |
854 | if (!dev) | |
855 | return NULL; | |
4ad96db6 | 856 | hw = to_me_hw(dev); |
52c34561 | 857 | |
3a7e9b6c | 858 | mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); |
4ad96db6 | 859 | hw->cfg = cfg; |
52c34561 TW |
860 | return dev; |
861 | } | |
06ecd645 | 862 |