Commit | Line | Data |
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3ce72726 OW |
1 | /* |
2 | * | |
3 | * Intel Management Engine Interface (Intel MEI) Linux driver | |
733ba91c | 4 | * Copyright (c) 2003-2012, Intel Corporation. |
3ce72726 OW |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
06ecd645 TW |
18 | |
19 | #include <linux/kthread.h> | |
20 | #include <linux/interrupt.h> | |
47a73801 TW |
21 | |
22 | #include "mei_dev.h" | |
06ecd645 TW |
23 | #include "hbm.h" |
24 | ||
6e4cd27a TW |
25 | #include "hw-me.h" |
26 | #include "hw-me-regs.h" | |
06ecd645 | 27 | |
3a65dd4e | 28 | /** |
b68301e9 | 29 | * mei_me_reg_read - Reads 32bit data from the mei device |
3a65dd4e | 30 | * |
a8605ea2 | 31 | * @hw: the me hardware structure |
3a65dd4e TW |
32 | * @offset: offset from which to read the data |
33 | * | |
a8605ea2 | 34 | * Return: register value (u32) |
3a65dd4e | 35 | */ |
b68301e9 | 36 | static inline u32 mei_me_reg_read(const struct mei_me_hw *hw, |
3a65dd4e TW |
37 | unsigned long offset) |
38 | { | |
52c34561 | 39 | return ioread32(hw->mem_addr + offset); |
3a65dd4e TW |
40 | } |
41 | ||
42 | ||
43 | /** | |
b68301e9 | 44 | * mei_me_reg_write - Writes 32bit data to the mei device |
3a65dd4e | 45 | * |
a8605ea2 | 46 | * @hw: the me hardware structure |
3a65dd4e TW |
47 | * @offset: offset from which to write the data |
48 | * @value: register value to write (u32) | |
49 | */ | |
b68301e9 | 50 | static inline void mei_me_reg_write(const struct mei_me_hw *hw, |
3a65dd4e TW |
51 | unsigned long offset, u32 value) |
52 | { | |
52c34561 | 53 | iowrite32(value, hw->mem_addr + offset); |
3a65dd4e | 54 | } |
3ce72726 | 55 | |
3a65dd4e | 56 | /** |
b68301e9 | 57 | * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer |
d025284d | 58 | * read window register |
3a65dd4e TW |
59 | * |
60 | * @dev: the device structure | |
61 | * | |
a8605ea2 | 62 | * Return: ME_CB_RW register value (u32) |
3a65dd4e | 63 | */ |
827eef51 | 64 | static u32 mei_me_mecbrw_read(const struct mei_device *dev) |
3a65dd4e | 65 | { |
b68301e9 | 66 | return mei_me_reg_read(to_me_hw(dev), ME_CB_RW); |
3a65dd4e TW |
67 | } |
68 | /** | |
b68301e9 | 69 | * mei_me_mecsr_read - Reads 32bit data from the ME CSR |
3a65dd4e | 70 | * |
a8605ea2 | 71 | * @hw: the me hardware structure |
3a65dd4e | 72 | * |
a8605ea2 | 73 | * Return: ME_CSR_HA register value (u32) |
3a65dd4e | 74 | */ |
b68301e9 | 75 | static inline u32 mei_me_mecsr_read(const struct mei_me_hw *hw) |
3a65dd4e | 76 | { |
b68301e9 | 77 | return mei_me_reg_read(hw, ME_CSR_HA); |
3a65dd4e | 78 | } |
3ce72726 OW |
79 | |
80 | /** | |
d025284d TW |
81 | * mei_hcsr_read - Reads 32bit data from the host CSR |
82 | * | |
a8605ea2 | 83 | * @hw: the me hardware structure |
d025284d | 84 | * |
a8605ea2 | 85 | * Return: H_CSR register value (u32) |
d025284d | 86 | */ |
52c34561 | 87 | static inline u32 mei_hcsr_read(const struct mei_me_hw *hw) |
d025284d | 88 | { |
b68301e9 | 89 | return mei_me_reg_read(hw, H_CSR); |
d025284d TW |
90 | } |
91 | ||
92 | /** | |
93 | * mei_hcsr_set - writes H_CSR register to the mei device, | |
3ce72726 OW |
94 | * and ignores the H_IS bit for it is write-one-to-zero. |
95 | * | |
a8605ea2 | 96 | * @hw: the me hardware structure |
ce23139c | 97 | * @hcsr: new register value |
3ce72726 | 98 | */ |
52c34561 | 99 | static inline void mei_hcsr_set(struct mei_me_hw *hw, u32 hcsr) |
3ce72726 | 100 | { |
88eb99f2 | 101 | hcsr &= ~H_IS; |
b68301e9 | 102 | mei_me_reg_write(hw, H_CSR, hcsr); |
3ce72726 OW |
103 | } |
104 | ||
1bd30b6a TW |
105 | /** |
106 | * mei_me_fw_status - read fw status register from pci config space | |
107 | * | |
108 | * @dev: mei device | |
109 | * @fw_status: fw status register values | |
ce23139c AU |
110 | * |
111 | * Return: 0 on success, error otherwise | |
1bd30b6a TW |
112 | */ |
113 | static int mei_me_fw_status(struct mei_device *dev, | |
114 | struct mei_fw_status *fw_status) | |
115 | { | |
1bd30b6a | 116 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
4ad96db6 TW |
117 | struct mei_me_hw *hw = to_me_hw(dev); |
118 | const struct mei_fw_status *fw_src = &hw->cfg->fw_status; | |
1bd30b6a TW |
119 | int ret; |
120 | int i; | |
121 | ||
122 | if (!fw_status) | |
123 | return -EINVAL; | |
124 | ||
125 | fw_status->count = fw_src->count; | |
126 | for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) { | |
127 | ret = pci_read_config_dword(pdev, | |
128 | fw_src->status[i], &fw_status->status[i]); | |
129 | if (ret) | |
130 | return ret; | |
131 | } | |
132 | ||
133 | return 0; | |
134 | } | |
e7e0c231 TW |
135 | |
136 | /** | |
393b148f | 137 | * mei_me_hw_config - configure hw dependent settings |
e7e0c231 TW |
138 | * |
139 | * @dev: mei device | |
140 | */ | |
827eef51 | 141 | static void mei_me_hw_config(struct mei_device *dev) |
e7e0c231 | 142 | { |
ba9cdd0e | 143 | struct mei_me_hw *hw = to_me_hw(dev); |
52c34561 | 144 | u32 hcsr = mei_hcsr_read(to_me_hw(dev)); |
e7e0c231 TW |
145 | /* Doesn't change in runtime */ |
146 | dev->hbuf_depth = (hcsr & H_CBD) >> 24; | |
ba9cdd0e TW |
147 | |
148 | hw->pg_state = MEI_PG_OFF; | |
e7e0c231 | 149 | } |
964a2331 TW |
150 | |
151 | /** | |
152 | * mei_me_pg_state - translate internal pg state | |
153 | * to the mei power gating state | |
154 | * | |
ce23139c AU |
155 | * @dev: mei device |
156 | * | |
157 | * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise | |
964a2331 TW |
158 | */ |
159 | static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev) | |
160 | { | |
ba9cdd0e | 161 | struct mei_me_hw *hw = to_me_hw(dev); |
92db1555 | 162 | |
ba9cdd0e | 163 | return hw->pg_state; |
964a2331 TW |
164 | } |
165 | ||
3ce72726 | 166 | /** |
ce23139c | 167 | * mei_me_intr_clear - clear and stop interrupts |
3a65dd4e TW |
168 | * |
169 | * @dev: the device structure | |
170 | */ | |
827eef51 | 171 | static void mei_me_intr_clear(struct mei_device *dev) |
3a65dd4e | 172 | { |
52c34561 TW |
173 | struct mei_me_hw *hw = to_me_hw(dev); |
174 | u32 hcsr = mei_hcsr_read(hw); | |
92db1555 | 175 | |
9ea73ddd | 176 | if ((hcsr & H_IS) == H_IS) |
b68301e9 | 177 | mei_me_reg_write(hw, H_CSR, hcsr); |
3a65dd4e | 178 | } |
3a65dd4e | 179 | /** |
827eef51 | 180 | * mei_me_intr_enable - enables mei device interrupts |
3ce72726 OW |
181 | * |
182 | * @dev: the device structure | |
183 | */ | |
827eef51 | 184 | static void mei_me_intr_enable(struct mei_device *dev) |
3ce72726 | 185 | { |
52c34561 TW |
186 | struct mei_me_hw *hw = to_me_hw(dev); |
187 | u32 hcsr = mei_hcsr_read(hw); | |
92db1555 | 188 | |
9ea73ddd | 189 | hcsr |= H_IE; |
52c34561 | 190 | mei_hcsr_set(hw, hcsr); |
3ce72726 OW |
191 | } |
192 | ||
193 | /** | |
ce23139c | 194 | * mei_me_intr_disable - disables mei device interrupts |
3ce72726 OW |
195 | * |
196 | * @dev: the device structure | |
197 | */ | |
827eef51 | 198 | static void mei_me_intr_disable(struct mei_device *dev) |
3ce72726 | 199 | { |
52c34561 TW |
200 | struct mei_me_hw *hw = to_me_hw(dev); |
201 | u32 hcsr = mei_hcsr_read(hw); | |
92db1555 | 202 | |
9ea73ddd | 203 | hcsr &= ~H_IE; |
52c34561 | 204 | mei_hcsr_set(hw, hcsr); |
3ce72726 OW |
205 | } |
206 | ||
68f8ea18 TW |
207 | /** |
208 | * mei_me_hw_reset_release - release device from the reset | |
209 | * | |
210 | * @dev: the device structure | |
211 | */ | |
212 | static void mei_me_hw_reset_release(struct mei_device *dev) | |
213 | { | |
214 | struct mei_me_hw *hw = to_me_hw(dev); | |
215 | u32 hcsr = mei_hcsr_read(hw); | |
216 | ||
217 | hcsr |= H_IG; | |
218 | hcsr &= ~H_RST; | |
219 | mei_hcsr_set(hw, hcsr); | |
b04ada92 TW |
220 | |
221 | /* complete this write before we set host ready on another CPU */ | |
222 | mmiowb(); | |
68f8ea18 | 223 | } |
adfba322 | 224 | /** |
827eef51 | 225 | * mei_me_hw_reset - resets fw via mei csr register. |
adfba322 TW |
226 | * |
227 | * @dev: the device structure | |
393b148f | 228 | * @intr_enable: if interrupt should be enabled after reset. |
ce23139c AU |
229 | * |
230 | * Return: always 0 | |
adfba322 | 231 | */ |
c20c68d5 | 232 | static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable) |
adfba322 | 233 | { |
52c34561 TW |
234 | struct mei_me_hw *hw = to_me_hw(dev); |
235 | u32 hcsr = mei_hcsr_read(hw); | |
adfba322 | 236 | |
b13a65ef AU |
237 | /* H_RST may be found lit before reset is started, |
238 | * for example if preceding reset flow hasn't completed. | |
239 | * In that case asserting H_RST will be ignored, therefore | |
240 | * we need to clean H_RST bit to start a successful reset sequence. | |
241 | */ | |
242 | if ((hcsr & H_RST) == H_RST) { | |
243 | dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr); | |
244 | hcsr &= ~H_RST; | |
1ab1e79b | 245 | mei_hcsr_set(hw, hcsr); |
b13a65ef AU |
246 | hcsr = mei_hcsr_read(hw); |
247 | } | |
248 | ||
ff96066e | 249 | hcsr |= H_RST | H_IG | H_IS; |
adfba322 TW |
250 | |
251 | if (intr_enable) | |
252 | hcsr |= H_IE; | |
253 | else | |
ff96066e | 254 | hcsr &= ~H_IE; |
adfba322 | 255 | |
07cd7be3 | 256 | dev->recvd_hw_ready = false; |
ff96066e | 257 | mei_me_reg_write(hw, H_CSR, hcsr); |
adfba322 | 258 | |
c40765d9 TW |
259 | /* |
260 | * Host reads the H_CSR once to ensure that the | |
261 | * posted write to H_CSR completes. | |
262 | */ | |
263 | hcsr = mei_hcsr_read(hw); | |
264 | ||
265 | if ((hcsr & H_RST) == 0) | |
2bf94cab | 266 | dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr); |
c40765d9 TW |
267 | |
268 | if ((hcsr & H_RDY) == H_RDY) | |
2bf94cab | 269 | dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr); |
c40765d9 | 270 | |
33ec0826 | 271 | if (intr_enable == false) |
68f8ea18 | 272 | mei_me_hw_reset_release(dev); |
adfba322 | 273 | |
c20c68d5 | 274 | return 0; |
adfba322 TW |
275 | } |
276 | ||
115ba28c | 277 | /** |
827eef51 | 278 | * mei_me_host_set_ready - enable device |
115ba28c | 279 | * |
ce23139c | 280 | * @dev: mei device |
115ba28c | 281 | */ |
827eef51 | 282 | static void mei_me_host_set_ready(struct mei_device *dev) |
115ba28c | 283 | { |
52c34561 | 284 | struct mei_me_hw *hw = to_me_hw(dev); |
18caeb70 | 285 | u32 hcsr = mei_hcsr_read(hw); |
92db1555 | 286 | |
18caeb70 TW |
287 | hcsr |= H_IE | H_IG | H_RDY; |
288 | mei_hcsr_set(hw, hcsr); | |
115ba28c | 289 | } |
ce23139c | 290 | |
115ba28c | 291 | /** |
827eef51 | 292 | * mei_me_host_is_ready - check whether the host has turned ready |
115ba28c | 293 | * |
a8605ea2 AU |
294 | * @dev: mei device |
295 | * Return: bool | |
115ba28c | 296 | */ |
827eef51 | 297 | static bool mei_me_host_is_ready(struct mei_device *dev) |
115ba28c | 298 | { |
52c34561 | 299 | struct mei_me_hw *hw = to_me_hw(dev); |
18caeb70 | 300 | u32 hcsr = mei_hcsr_read(hw); |
92db1555 | 301 | |
18caeb70 | 302 | return (hcsr & H_RDY) == H_RDY; |
115ba28c TW |
303 | } |
304 | ||
305 | /** | |
827eef51 | 306 | * mei_me_hw_is_ready - check whether the me(hw) has turned ready |
115ba28c | 307 | * |
a8605ea2 AU |
308 | * @dev: mei device |
309 | * Return: bool | |
115ba28c | 310 | */ |
827eef51 | 311 | static bool mei_me_hw_is_ready(struct mei_device *dev) |
115ba28c | 312 | { |
52c34561 | 313 | struct mei_me_hw *hw = to_me_hw(dev); |
18caeb70 | 314 | u32 mecsr = mei_me_mecsr_read(hw); |
92db1555 | 315 | |
18caeb70 | 316 | return (mecsr & ME_RDY_HRA) == ME_RDY_HRA; |
115ba28c | 317 | } |
3a65dd4e | 318 | |
ce23139c AU |
319 | /** |
320 | * mei_me_hw_ready_wait - wait until the me(hw) has turned ready | |
321 | * or timeout is reached | |
322 | * | |
323 | * @dev: mei device | |
324 | * Return: 0 on success, error otherwise | |
325 | */ | |
aafae7ec TW |
326 | static int mei_me_hw_ready_wait(struct mei_device *dev) |
327 | { | |
aafae7ec | 328 | mutex_unlock(&dev->device_lock); |
2c2b93ec | 329 | wait_event_timeout(dev->wait_hw_ready, |
dab9bf41 | 330 | dev->recvd_hw_ready, |
7d93e58d | 331 | mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT)); |
aafae7ec | 332 | mutex_lock(&dev->device_lock); |
2c2b93ec | 333 | if (!dev->recvd_hw_ready) { |
2bf94cab | 334 | dev_err(dev->dev, "wait hw ready failed\n"); |
2c2b93ec | 335 | return -ETIME; |
aafae7ec TW |
336 | } |
337 | ||
338 | dev->recvd_hw_ready = false; | |
339 | return 0; | |
340 | } | |
341 | ||
ce23139c AU |
342 | /** |
343 | * mei_me_hw_start - hw start routine | |
344 | * | |
345 | * @dev: mei device | |
346 | * Return: 0 on success, error otherwise | |
347 | */ | |
aafae7ec TW |
348 | static int mei_me_hw_start(struct mei_device *dev) |
349 | { | |
350 | int ret = mei_me_hw_ready_wait(dev); | |
92db1555 | 351 | |
aafae7ec TW |
352 | if (ret) |
353 | return ret; | |
2bf94cab | 354 | dev_dbg(dev->dev, "hw is ready\n"); |
aafae7ec TW |
355 | |
356 | mei_me_host_set_ready(dev); | |
357 | return ret; | |
358 | } | |
359 | ||
360 | ||
3ce72726 | 361 | /** |
726917f0 | 362 | * mei_hbuf_filled_slots - gets number of device filled buffer slots |
3ce72726 | 363 | * |
7353f85c | 364 | * @dev: the device structure |
3ce72726 | 365 | * |
a8605ea2 | 366 | * Return: number of filled slots |
3ce72726 | 367 | */ |
726917f0 | 368 | static unsigned char mei_hbuf_filled_slots(struct mei_device *dev) |
3ce72726 | 369 | { |
52c34561 | 370 | struct mei_me_hw *hw = to_me_hw(dev); |
18caeb70 | 371 | u32 hcsr; |
3ce72726 OW |
372 | char read_ptr, write_ptr; |
373 | ||
18caeb70 | 374 | hcsr = mei_hcsr_read(hw); |
726917f0 | 375 | |
18caeb70 TW |
376 | read_ptr = (char) ((hcsr & H_CBRP) >> 8); |
377 | write_ptr = (char) ((hcsr & H_CBWP) >> 16); | |
3ce72726 OW |
378 | |
379 | return (unsigned char) (write_ptr - read_ptr); | |
380 | } | |
381 | ||
382 | /** | |
393b148f | 383 | * mei_me_hbuf_is_empty - checks if host buffer is empty. |
3ce72726 OW |
384 | * |
385 | * @dev: the device structure | |
386 | * | |
a8605ea2 | 387 | * Return: true if empty, false - otherwise. |
3ce72726 | 388 | */ |
827eef51 | 389 | static bool mei_me_hbuf_is_empty(struct mei_device *dev) |
3ce72726 | 390 | { |
726917f0 | 391 | return mei_hbuf_filled_slots(dev) == 0; |
3ce72726 OW |
392 | } |
393 | ||
394 | /** | |
827eef51 | 395 | * mei_me_hbuf_empty_slots - counts write empty slots. |
3ce72726 OW |
396 | * |
397 | * @dev: the device structure | |
398 | * | |
a8605ea2 | 399 | * Return: -EOVERFLOW if overflow, otherwise empty slots count |
3ce72726 | 400 | */ |
827eef51 | 401 | static int mei_me_hbuf_empty_slots(struct mei_device *dev) |
3ce72726 | 402 | { |
24aadc80 | 403 | unsigned char filled_slots, empty_slots; |
3ce72726 | 404 | |
726917f0 | 405 | filled_slots = mei_hbuf_filled_slots(dev); |
24aadc80 | 406 | empty_slots = dev->hbuf_depth - filled_slots; |
3ce72726 OW |
407 | |
408 | /* check for overflow */ | |
24aadc80 | 409 | if (filled_slots > dev->hbuf_depth) |
3ce72726 OW |
410 | return -EOVERFLOW; |
411 | ||
412 | return empty_slots; | |
413 | } | |
414 | ||
ce23139c AU |
415 | /** |
416 | * mei_me_hbuf_max_len - returns size of hw buffer. | |
417 | * | |
418 | * @dev: the device structure | |
419 | * | |
420 | * Return: size of hw buffer in bytes | |
421 | */ | |
827eef51 TW |
422 | static size_t mei_me_hbuf_max_len(const struct mei_device *dev) |
423 | { | |
424 | return dev->hbuf_depth * sizeof(u32) - sizeof(struct mei_msg_hdr); | |
425 | } | |
426 | ||
427 | ||
3ce72726 | 428 | /** |
7ca96aa2 | 429 | * mei_me_write_message - writes a message to mei device. |
3ce72726 OW |
430 | * |
431 | * @dev: the device structure | |
7353f85c | 432 | * @header: mei HECI header of message |
438763f3 | 433 | * @buf: message payload will be written |
3ce72726 | 434 | * |
a8605ea2 | 435 | * Return: -EIO if write has failed |
3ce72726 | 436 | */ |
827eef51 TW |
437 | static int mei_me_write_message(struct mei_device *dev, |
438 | struct mei_msg_hdr *header, | |
439 | unsigned char *buf) | |
3ce72726 | 440 | { |
52c34561 | 441 | struct mei_me_hw *hw = to_me_hw(dev); |
c8c8d080 | 442 | unsigned long rem; |
438763f3 | 443 | unsigned long length = header->length; |
169d1338 | 444 | u32 *reg_buf = (u32 *)buf; |
88eb99f2 | 445 | u32 hcsr; |
c8c8d080 | 446 | u32 dw_cnt; |
169d1338 TW |
447 | int i; |
448 | int empty_slots; | |
3ce72726 | 449 | |
2bf94cab | 450 | dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header)); |
3ce72726 | 451 | |
726917f0 | 452 | empty_slots = mei_hbuf_empty_slots(dev); |
2bf94cab | 453 | dev_dbg(dev->dev, "empty slots = %hu.\n", empty_slots); |
3ce72726 | 454 | |
7bdf72d3 | 455 | dw_cnt = mei_data2slots(length); |
169d1338 | 456 | if (empty_slots < 0 || dw_cnt > empty_slots) |
9d098192 | 457 | return -EMSGSIZE; |
3ce72726 | 458 | |
b68301e9 | 459 | mei_me_reg_write(hw, H_CB_WW, *((u32 *) header)); |
3ce72726 | 460 | |
169d1338 | 461 | for (i = 0; i < length / 4; i++) |
b68301e9 | 462 | mei_me_reg_write(hw, H_CB_WW, reg_buf[i]); |
3ce72726 | 463 | |
169d1338 TW |
464 | rem = length & 0x3; |
465 | if (rem > 0) { | |
466 | u32 reg = 0; | |
92db1555 | 467 | |
169d1338 | 468 | memcpy(®, &buf[length - rem], rem); |
b68301e9 | 469 | mei_me_reg_write(hw, H_CB_WW, reg); |
3ce72726 OW |
470 | } |
471 | ||
52c34561 TW |
472 | hcsr = mei_hcsr_read(hw) | H_IG; |
473 | mei_hcsr_set(hw, hcsr); | |
827eef51 | 474 | if (!mei_me_hw_is_ready(dev)) |
1ccb7b62 | 475 | return -EIO; |
3ce72726 | 476 | |
1ccb7b62 | 477 | return 0; |
3ce72726 OW |
478 | } |
479 | ||
480 | /** | |
827eef51 | 481 | * mei_me_count_full_read_slots - counts read full slots. |
3ce72726 OW |
482 | * |
483 | * @dev: the device structure | |
484 | * | |
a8605ea2 | 485 | * Return: -EOVERFLOW if overflow, otherwise filled slots count |
3ce72726 | 486 | */ |
827eef51 | 487 | static int mei_me_count_full_read_slots(struct mei_device *dev) |
3ce72726 | 488 | { |
52c34561 | 489 | struct mei_me_hw *hw = to_me_hw(dev); |
18caeb70 | 490 | u32 me_csr; |
3ce72726 OW |
491 | char read_ptr, write_ptr; |
492 | unsigned char buffer_depth, filled_slots; | |
493 | ||
18caeb70 TW |
494 | me_csr = mei_me_mecsr_read(hw); |
495 | buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24); | |
496 | read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8); | |
497 | write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16); | |
3ce72726 OW |
498 | filled_slots = (unsigned char) (write_ptr - read_ptr); |
499 | ||
500 | /* check for overflow */ | |
501 | if (filled_slots > buffer_depth) | |
502 | return -EOVERFLOW; | |
503 | ||
2bf94cab | 504 | dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots); |
3ce72726 OW |
505 | return (int)filled_slots; |
506 | } | |
507 | ||
508 | /** | |
827eef51 | 509 | * mei_me_read_slots - reads a message from mei device. |
3ce72726 OW |
510 | * |
511 | * @dev: the device structure | |
512 | * @buffer: message buffer will be written | |
513 | * @buffer_length: message size will be read | |
ce23139c AU |
514 | * |
515 | * Return: always 0 | |
3ce72726 | 516 | */ |
827eef51 | 517 | static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer, |
edf1eed4 | 518 | unsigned long buffer_length) |
3ce72726 | 519 | { |
52c34561 | 520 | struct mei_me_hw *hw = to_me_hw(dev); |
edf1eed4 | 521 | u32 *reg_buf = (u32 *)buffer; |
88eb99f2 | 522 | u32 hcsr; |
3ce72726 | 523 | |
edf1eed4 | 524 | for (; buffer_length >= sizeof(u32); buffer_length -= sizeof(u32)) |
827eef51 | 525 | *reg_buf++ = mei_me_mecbrw_read(dev); |
3ce72726 OW |
526 | |
527 | if (buffer_length > 0) { | |
827eef51 | 528 | u32 reg = mei_me_mecbrw_read(dev); |
92db1555 | 529 | |
edf1eed4 | 530 | memcpy(reg_buf, ®, buffer_length); |
3ce72726 OW |
531 | } |
532 | ||
52c34561 TW |
533 | hcsr = mei_hcsr_read(hw) | H_IG; |
534 | mei_hcsr_set(hw, hcsr); | |
827eef51 | 535 | return 0; |
3ce72726 OW |
536 | } |
537 | ||
b16c3571 | 538 | /** |
152de90d | 539 | * mei_me_pg_enter - write pg enter register |
b16c3571 TW |
540 | * |
541 | * @dev: the device structure | |
542 | */ | |
543 | static void mei_me_pg_enter(struct mei_device *dev) | |
544 | { | |
545 | struct mei_me_hw *hw = to_me_hw(dev); | |
546 | u32 reg = mei_me_reg_read(hw, H_HPG_CSR); | |
92db1555 | 547 | |
b16c3571 TW |
548 | reg |= H_HPG_CSR_PGI; |
549 | mei_me_reg_write(hw, H_HPG_CSR, reg); | |
550 | } | |
551 | ||
552 | /** | |
152de90d | 553 | * mei_me_pg_exit - write pg exit register |
b16c3571 TW |
554 | * |
555 | * @dev: the device structure | |
556 | */ | |
557 | static void mei_me_pg_exit(struct mei_device *dev) | |
558 | { | |
559 | struct mei_me_hw *hw = to_me_hw(dev); | |
560 | u32 reg = mei_me_reg_read(hw, H_HPG_CSR); | |
561 | ||
562 | WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n"); | |
563 | ||
564 | reg |= H_HPG_CSR_PGIHEXR; | |
565 | mei_me_reg_write(hw, H_HPG_CSR, reg); | |
566 | } | |
567 | ||
ba9cdd0e TW |
568 | /** |
569 | * mei_me_pg_set_sync - perform pg entry procedure | |
570 | * | |
571 | * @dev: the device structure | |
572 | * | |
a8605ea2 | 573 | * Return: 0 on success an error code otherwise |
ba9cdd0e TW |
574 | */ |
575 | int mei_me_pg_set_sync(struct mei_device *dev) | |
576 | { | |
577 | struct mei_me_hw *hw = to_me_hw(dev); | |
578 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); | |
579 | int ret; | |
580 | ||
581 | dev->pg_event = MEI_PG_EVENT_WAIT; | |
582 | ||
583 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD); | |
584 | if (ret) | |
585 | return ret; | |
586 | ||
587 | mutex_unlock(&dev->device_lock); | |
588 | wait_event_timeout(dev->wait_pg, | |
589 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
590 | mutex_lock(&dev->device_lock); | |
591 | ||
592 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) { | |
593 | mei_me_pg_enter(dev); | |
594 | ret = 0; | |
595 | } else { | |
596 | ret = -ETIME; | |
597 | } | |
598 | ||
599 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
600 | hw->pg_state = MEI_PG_ON; | |
601 | ||
602 | return ret; | |
603 | } | |
604 | ||
605 | /** | |
606 | * mei_me_pg_unset_sync - perform pg exit procedure | |
607 | * | |
608 | * @dev: the device structure | |
609 | * | |
a8605ea2 | 610 | * Return: 0 on success an error code otherwise |
ba9cdd0e TW |
611 | */ |
612 | int mei_me_pg_unset_sync(struct mei_device *dev) | |
613 | { | |
614 | struct mei_me_hw *hw = to_me_hw(dev); | |
615 | unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT); | |
616 | int ret; | |
617 | ||
618 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) | |
619 | goto reply; | |
620 | ||
621 | dev->pg_event = MEI_PG_EVENT_WAIT; | |
622 | ||
623 | mei_me_pg_exit(dev); | |
624 | ||
625 | mutex_unlock(&dev->device_lock); | |
626 | wait_event_timeout(dev->wait_pg, | |
627 | dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout); | |
628 | mutex_lock(&dev->device_lock); | |
629 | ||
630 | reply: | |
631 | if (dev->pg_event == MEI_PG_EVENT_RECEIVED) | |
632 | ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD); | |
633 | else | |
634 | ret = -ETIME; | |
635 | ||
636 | dev->pg_event = MEI_PG_EVENT_IDLE; | |
637 | hw->pg_state = MEI_PG_OFF; | |
638 | ||
639 | return ret; | |
640 | } | |
641 | ||
ee7e5afd TW |
642 | /** |
643 | * mei_me_pg_is_enabled - detect if PG is supported by HW | |
644 | * | |
645 | * @dev: the device structure | |
646 | * | |
a8605ea2 | 647 | * Return: true is pg supported, false otherwise |
ee7e5afd TW |
648 | */ |
649 | static bool mei_me_pg_is_enabled(struct mei_device *dev) | |
650 | { | |
651 | struct mei_me_hw *hw = to_me_hw(dev); | |
652 | u32 reg = mei_me_reg_read(hw, ME_CSR_HA); | |
653 | ||
654 | if ((reg & ME_PGIC_HRA) == 0) | |
655 | goto notsupported; | |
656 | ||
bae1cc7d | 657 | if (!dev->hbm_f_pg_supported) |
ee7e5afd TW |
658 | goto notsupported; |
659 | ||
660 | return true; | |
661 | ||
662 | notsupported: | |
2bf94cab | 663 | dev_dbg(dev->dev, "pg: not supported: HGP = %d hbm version %d.%d ?= %d.%d\n", |
ee7e5afd TW |
664 | !!(reg & ME_PGIC_HRA), |
665 | dev->version.major_version, | |
666 | dev->version.minor_version, | |
667 | HBM_MAJOR_VERSION_PGI, | |
668 | HBM_MINOR_VERSION_PGI); | |
669 | ||
670 | return false; | |
671 | } | |
672 | ||
06ecd645 TW |
673 | /** |
674 | * mei_me_irq_quick_handler - The ISR of the MEI device | |
675 | * | |
676 | * @irq: The irq number | |
677 | * @dev_id: pointer to the device structure | |
678 | * | |
a8605ea2 | 679 | * Return: irqreturn_t |
06ecd645 TW |
680 | */ |
681 | ||
682 | irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id) | |
683 | { | |
684 | struct mei_device *dev = (struct mei_device *) dev_id; | |
685 | struct mei_me_hw *hw = to_me_hw(dev); | |
686 | u32 csr_reg = mei_hcsr_read(hw); | |
687 | ||
688 | if ((csr_reg & H_IS) != H_IS) | |
689 | return IRQ_NONE; | |
690 | ||
691 | /* clear H_IS bit in H_CSR */ | |
b68301e9 | 692 | mei_me_reg_write(hw, H_CSR, csr_reg); |
06ecd645 TW |
693 | |
694 | return IRQ_WAKE_THREAD; | |
695 | } | |
696 | ||
697 | /** | |
698 | * mei_me_irq_thread_handler - function called after ISR to handle the interrupt | |
699 | * processing. | |
700 | * | |
701 | * @irq: The irq number | |
702 | * @dev_id: pointer to the device structure | |
703 | * | |
a8605ea2 | 704 | * Return: irqreturn_t |
06ecd645 TW |
705 | * |
706 | */ | |
707 | irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id) | |
708 | { | |
709 | struct mei_device *dev = (struct mei_device *) dev_id; | |
710 | struct mei_cl_cb complete_list; | |
06ecd645 | 711 | s32 slots; |
544f9460 | 712 | int rets = 0; |
06ecd645 | 713 | |
2bf94cab | 714 | dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n"); |
06ecd645 TW |
715 | /* initialize our complete list */ |
716 | mutex_lock(&dev->device_lock); | |
717 | mei_io_list_init(&complete_list); | |
718 | ||
719 | /* Ack the interrupt here | |
720 | * In case of MSI we don't go through the quick handler */ | |
d08b8fc0 | 721 | if (pci_dev_msi_enabled(to_pci_dev(dev->dev))) |
06ecd645 TW |
722 | mei_clear_interrupts(dev); |
723 | ||
724 | /* check if ME wants a reset */ | |
33ec0826 | 725 | if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) { |
2bf94cab | 726 | dev_warn(dev->dev, "FW not ready: resetting.\n"); |
544f9460 TW |
727 | schedule_work(&dev->reset_work); |
728 | goto end; | |
06ecd645 TW |
729 | } |
730 | ||
731 | /* check if we need to start the dev */ | |
732 | if (!mei_host_is_ready(dev)) { | |
733 | if (mei_hw_is_ready(dev)) { | |
b04ada92 | 734 | mei_me_hw_reset_release(dev); |
2bf94cab | 735 | dev_dbg(dev->dev, "we need to start the dev.\n"); |
06ecd645 | 736 | |
aafae7ec | 737 | dev->recvd_hw_ready = true; |
2c2b93ec | 738 | wake_up(&dev->wait_hw_ready); |
06ecd645 | 739 | } else { |
2bf94cab | 740 | dev_dbg(dev->dev, "Spurious Interrupt\n"); |
06ecd645 | 741 | } |
544f9460 | 742 | goto end; |
06ecd645 TW |
743 | } |
744 | /* check slots available for reading */ | |
745 | slots = mei_count_full_read_slots(dev); | |
746 | while (slots > 0) { | |
2bf94cab | 747 | dev_dbg(dev->dev, "slots to read = %08x\n", slots); |
06ecd645 | 748 | rets = mei_irq_read_handler(dev, &complete_list, &slots); |
b1b94b5d TW |
749 | /* There is a race between ME write and interrupt delivery: |
750 | * Not all data is always available immediately after the | |
751 | * interrupt, so try to read again on the next interrupt. | |
752 | */ | |
753 | if (rets == -ENODATA) | |
754 | break; | |
755 | ||
33ec0826 | 756 | if (rets && dev->dev_state != MEI_DEV_RESETTING) { |
2bf94cab | 757 | dev_err(dev->dev, "mei_irq_read_handler ret = %d.\n", |
b1b94b5d | 758 | rets); |
544f9460 | 759 | schedule_work(&dev->reset_work); |
06ecd645 | 760 | goto end; |
544f9460 | 761 | } |
06ecd645 | 762 | } |
544f9460 | 763 | |
6aae48ff TW |
764 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); |
765 | ||
ba9cdd0e TW |
766 | /* |
767 | * During PG handshake only allowed write is the replay to the | |
768 | * PG exit message, so block calling write function | |
769 | * if the pg state is not idle | |
770 | */ | |
771 | if (dev->pg_event == MEI_PG_EVENT_IDLE) { | |
772 | rets = mei_irq_write_handler(dev, &complete_list); | |
773 | dev->hbuf_is_ready = mei_hbuf_is_ready(dev); | |
774 | } | |
06ecd645 | 775 | |
4c6e22b8 | 776 | mei_irq_compl_handler(dev, &complete_list); |
06ecd645 | 777 | |
544f9460 | 778 | end: |
2bf94cab | 779 | dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets); |
544f9460 | 780 | mutex_unlock(&dev->device_lock); |
06ecd645 TW |
781 | return IRQ_HANDLED; |
782 | } | |
04dd3661 | 783 | |
827eef51 TW |
784 | static const struct mei_hw_ops mei_me_hw_ops = { |
785 | ||
1bd30b6a | 786 | .fw_status = mei_me_fw_status, |
964a2331 TW |
787 | .pg_state = mei_me_pg_state, |
788 | ||
827eef51 TW |
789 | .host_is_ready = mei_me_host_is_ready, |
790 | ||
791 | .hw_is_ready = mei_me_hw_is_ready, | |
792 | .hw_reset = mei_me_hw_reset, | |
aafae7ec TW |
793 | .hw_config = mei_me_hw_config, |
794 | .hw_start = mei_me_hw_start, | |
827eef51 | 795 | |
ee7e5afd TW |
796 | .pg_is_enabled = mei_me_pg_is_enabled, |
797 | ||
827eef51 TW |
798 | .intr_clear = mei_me_intr_clear, |
799 | .intr_enable = mei_me_intr_enable, | |
800 | .intr_disable = mei_me_intr_disable, | |
801 | ||
802 | .hbuf_free_slots = mei_me_hbuf_empty_slots, | |
803 | .hbuf_is_ready = mei_me_hbuf_is_empty, | |
804 | .hbuf_max_len = mei_me_hbuf_max_len, | |
805 | ||
806 | .write = mei_me_write_message, | |
807 | ||
808 | .rdbuf_full_slots = mei_me_count_full_read_slots, | |
809 | .read_hdr = mei_me_mecbrw_read, | |
810 | .read = mei_me_read_slots | |
811 | }; | |
812 | ||
c919951d TW |
813 | static bool mei_me_fw_type_nm(struct pci_dev *pdev) |
814 | { | |
815 | u32 reg; | |
92db1555 | 816 | |
c919951d TW |
817 | pci_read_config_dword(pdev, PCI_CFG_HFS_2, ®); |
818 | /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */ | |
819 | return (reg & 0x600) == 0x200; | |
820 | } | |
821 | ||
822 | #define MEI_CFG_FW_NM \ | |
823 | .quirk_probe = mei_me_fw_type_nm | |
824 | ||
825 | static bool mei_me_fw_type_sps(struct pci_dev *pdev) | |
826 | { | |
827 | u32 reg; | |
828 | /* Read ME FW Status check for SPS Firmware */ | |
829 | pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®); | |
830 | /* if bits [19:16] = 15, running SPS Firmware */ | |
831 | return (reg & 0xf0000) == 0xf0000; | |
832 | } | |
833 | ||
834 | #define MEI_CFG_FW_SPS \ | |
835 | .quirk_probe = mei_me_fw_type_sps | |
836 | ||
837 | ||
8d929d48 AU |
838 | #define MEI_CFG_LEGACY_HFS \ |
839 | .fw_status.count = 0 | |
840 | ||
841 | #define MEI_CFG_ICH_HFS \ | |
842 | .fw_status.count = 1, \ | |
843 | .fw_status.status[0] = PCI_CFG_HFS_1 | |
844 | ||
845 | #define MEI_CFG_PCH_HFS \ | |
846 | .fw_status.count = 2, \ | |
847 | .fw_status.status[0] = PCI_CFG_HFS_1, \ | |
848 | .fw_status.status[1] = PCI_CFG_HFS_2 | |
849 | ||
edca5ea3 AU |
850 | #define MEI_CFG_PCH8_HFS \ |
851 | .fw_status.count = 6, \ | |
852 | .fw_status.status[0] = PCI_CFG_HFS_1, \ | |
853 | .fw_status.status[1] = PCI_CFG_HFS_2, \ | |
854 | .fw_status.status[2] = PCI_CFG_HFS_3, \ | |
855 | .fw_status.status[3] = PCI_CFG_HFS_4, \ | |
856 | .fw_status.status[4] = PCI_CFG_HFS_5, \ | |
857 | .fw_status.status[5] = PCI_CFG_HFS_6 | |
8d929d48 AU |
858 | |
859 | /* ICH Legacy devices */ | |
860 | const struct mei_cfg mei_me_legacy_cfg = { | |
861 | MEI_CFG_LEGACY_HFS, | |
862 | }; | |
863 | ||
864 | /* ICH devices */ | |
865 | const struct mei_cfg mei_me_ich_cfg = { | |
866 | MEI_CFG_ICH_HFS, | |
867 | }; | |
868 | ||
869 | /* PCH devices */ | |
870 | const struct mei_cfg mei_me_pch_cfg = { | |
871 | MEI_CFG_PCH_HFS, | |
872 | }; | |
873 | ||
c919951d TW |
874 | |
875 | /* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */ | |
876 | const struct mei_cfg mei_me_pch_cpt_pbg_cfg = { | |
877 | MEI_CFG_PCH_HFS, | |
878 | MEI_CFG_FW_NM, | |
879 | }; | |
880 | ||
edca5ea3 AU |
881 | /* PCH8 Lynx Point and newer devices */ |
882 | const struct mei_cfg mei_me_pch8_cfg = { | |
883 | MEI_CFG_PCH8_HFS, | |
884 | }; | |
885 | ||
886 | /* PCH8 Lynx Point with quirk for SPS Firmware exclusion */ | |
887 | const struct mei_cfg mei_me_pch8_sps_cfg = { | |
888 | MEI_CFG_PCH8_HFS, | |
c919951d TW |
889 | MEI_CFG_FW_SPS, |
890 | }; | |
891 | ||
52c34561 | 892 | /** |
393b148f | 893 | * mei_me_dev_init - allocates and initializes the mei device structure |
52c34561 TW |
894 | * |
895 | * @pdev: The pci device structure | |
8d929d48 | 896 | * @cfg: per device generation config |
52c34561 | 897 | * |
a8605ea2 | 898 | * Return: The mei_device_device pointer on success, NULL on failure. |
52c34561 | 899 | */ |
8d929d48 AU |
900 | struct mei_device *mei_me_dev_init(struct pci_dev *pdev, |
901 | const struct mei_cfg *cfg) | |
52c34561 TW |
902 | { |
903 | struct mei_device *dev; | |
4ad96db6 | 904 | struct mei_me_hw *hw; |
52c34561 TW |
905 | |
906 | dev = kzalloc(sizeof(struct mei_device) + | |
907 | sizeof(struct mei_me_hw), GFP_KERNEL); | |
908 | if (!dev) | |
909 | return NULL; | |
4ad96db6 | 910 | hw = to_me_hw(dev); |
52c34561 | 911 | |
3a7e9b6c | 912 | mei_device_init(dev, &pdev->dev, &mei_me_hw_ops); |
4ad96db6 | 913 | hw->cfg = cfg; |
52c34561 TW |
914 | return dev; |
915 | } | |
06ecd645 | 916 |