[linux-block.git] / drivers / misc / ics932s401.c

/*
 * A driver for the Integrated Circuits ICS932S401
 * Copyright (C) 2008 IBM
 *
 * Author: Darrick J. Wong <darrick.wong@oracle.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/module.h>
#include <linux/jiffies.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/log2.h>
#include <linux/slab.h>

/* Addresses to scan */
static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END };

/* ICS932S401 registers */
#define ICS932S401_REG_CFG2			0x01
#define		ICS932S401_CFG1_SPREAD		0x01
#define ICS932S401_REG_CFG7			0x06
#define		ICS932S401_FS_MASK		0x07
#define	ICS932S401_REG_VENDOR_REV		0x07
#define		ICS932S401_VENDOR		1
#define		ICS932S401_VENDOR_MASK		0x0F
#define		ICS932S401_REV			4
#define		ICS932S401_REV_SHIFT		4
#define ICS932S401_REG_DEVICE			0x09
#define		ICS932S401_DEVICE		11
#define	ICS932S401_REG_CTRL			0x0A
#define		ICS932S401_MN_ENABLED		0x80
#define		ICS932S401_CPU_ALT		0x04
#define		ICS932S401_SRC_ALT		0x08
#define ICS932S401_REG_CPU_M_CTRL		0x0B
#define		ICS932S401_M_MASK		0x3F
#define	ICS932S401_REG_CPU_N_CTRL		0x0C
#define	ICS932S401_REG_CPU_SPREAD1		0x0D
#define ICS932S401_REG_CPU_SPREAD2		0x0E
#define		ICS932S401_SPREAD_MASK		0x7FFF
#define ICS932S401_REG_SRC_M_CTRL		0x0F
#define ICS932S401_REG_SRC_N_CTRL		0x10
#define	ICS932S401_REG_SRC_SPREAD1		0x11
#define ICS932S401_REG_SRC_SPREAD2		0x12
#define ICS932S401_REG_CPU_DIVISOR		0x13
#define		ICS932S401_CPU_DIVISOR_SHIFT	4
#define ICS932S401_REG_PCISRC_DIVISOR		0x14
#define		ICS932S401_SRC_DIVISOR_MASK	0x0F
#define		ICS932S401_PCI_DIVISOR_SHIFT	4

/* Base clock is 14.318MHz */
#define BASE_CLOCK				14318

#define NUM_REGS				21
#define NUM_MIRRORED_REGS			15

static int regs_to_copy[NUM_MIRRORED_REGS] = {
	ICS932S401_REG_CFG2,
	ICS932S401_REG_CFG7,
	ICS932S401_REG_VENDOR_REV,
	ICS932S401_REG_DEVICE,
	ICS932S401_REG_CTRL,
	ICS932S401_REG_CPU_M_CTRL,
	ICS932S401_REG_CPU_N_CTRL,
	ICS932S401_REG_CPU_SPREAD1,
	ICS932S401_REG_CPU_SPREAD2,
	ICS932S401_REG_SRC_M_CTRL,
	ICS932S401_REG_SRC_N_CTRL,
	ICS932S401_REG_SRC_SPREAD1,
	ICS932S401_REG_SRC_SPREAD2,
	ICS932S401_REG_CPU_DIVISOR,
	ICS932S401_REG_PCISRC_DIVISOR,
};

/* How often do we reread sensors values? (In jiffies) */
#define SENSOR_REFRESH_INTERVAL	(2 * HZ)

/* How often do we reread sensor limit values? (In jiffies) */
#define LIMIT_REFRESH_INTERVAL	(60 * HZ)

struct ics932s401_data {
	struct attribute_group	attrs;
	struct mutex		lock;
	char			sensors_valid;
	unsigned long		sensors_last_updated;	/* In jiffies */

	u8			regs[NUM_REGS];
};

static int ics932s401_probe(struct i2c_client *client,
			 const struct i2c_device_id *id);
static int ics932s401_detect(struct i2c_client *client,
			  struct i2c_board_info *info);
static int ics932s401_remove(struct i2c_client *client);

static const struct i2c_device_id ics932s401_id[] = {
	{ "ics932s401", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, ics932s401_id);

static struct i2c_driver ics932s401_driver = {
	.class		= I2C_CLASS_HWMON,
	.driver = {
		.name	= "ics932s401",
	},
	.probe		= ics932s401_probe,
	.remove		= ics932s401_remove,
	.id_table	= ics932s401_id,
	.detect		= ics932s401_detect,
	.address_list	= normal_i2c,
};

static struct ics932s401_data *ics932s401_update_device(struct device *dev)
{
	struct i2c_client *client = to_i2c_client(dev);
	struct ics932s401_data *data = i2c_get_clientdata(client);
	unsigned long local_jiffies = jiffies;
	int i, temp;

	mutex_lock(&data->lock);
	if (time_before(local_jiffies, data->sensors_last_updated +
		SENSOR_REFRESH_INTERVAL)
		&& data->sensors_valid)
		goto out;

	/*
	 * Each register must be read as a word and then right shifted 8 bits.
	 * Not really sure why this is; setting the "byte count programming"
	 * register to 1 does not fix this problem.
	 */
	for (i = 0; i < NUM_MIRRORED_REGS; i++) {
		temp = i2c_smbus_read_word_data(client, regs_to_copy[i]);
		data->regs[regs_to_copy[i]] = temp >> 8;
	}

	data->sensors_last_updated = local_jiffies;
	data->sensors_valid = 1;

out:
	mutex_unlock(&data->lock);
	return data;
}

static ssize_t show_spread_enabled(struct device *dev,
				   struct device_attribute *devattr,
				   char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);

	if (data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD)
		return sprintf(buf, "1\n");

	return sprintf(buf, "0\n");
}

/* bit to cpu khz map */
static const int fs_speeds[] = {
	266666,
	133333,
	200000,
	166666,
	333333,
	100000,
	400000,
	0,
};

/* clock divisor map */
static const int divisors[] = {2, 3, 5, 15, 4, 6, 10, 30, 8, 12, 20, 60, 16,
			       24, 40, 120};

/* Calculate CPU frequency from the M/N registers. */
static int calculate_cpu_freq(struct ics932s401_data *data)
{
	int m, n, freq;

	m = data->regs[ICS932S401_REG_CPU_M_CTRL] & ICS932S401_M_MASK;
	n = data->regs[ICS932S401_REG_CPU_N_CTRL];

	/* Pull in bits 8 & 9 from the M register */
	n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x80) << 1;
	n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x40) << 3;

	freq = BASE_CLOCK * (n + 8) / (m + 2);
	freq /= divisors[data->regs[ICS932S401_REG_CPU_DIVISOR] >>
			 ICS932S401_CPU_DIVISOR_SHIFT];

	return freq;
}

static ssize_t show_cpu_clock(struct device *dev,
			      struct device_attribute *devattr,
			      char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);

	return sprintf(buf, "%d\n", calculate_cpu_freq(data));
}

static ssize_t show_cpu_clock_sel(struct device *dev,
				  struct device_attribute *devattr,
				  char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);
	int freq;

	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
		freq = calculate_cpu_freq(data);
	else {
		/* Freq is neatly wrapped up for us */
		int fid = data->regs[ICS932S401_REG_CFG7] & ICS932S401_FS_MASK;

		freq = fs_speeds[fid];
		if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT) {
			switch (freq) {
			case 166666:
				freq = 160000;
				break;
			case 333333:
				freq = 320000;
				break;
			}
		}
	}

	return sprintf(buf, "%d\n", freq);
}

/* Calculate SRC frequency from the M/N registers. */
static int calculate_src_freq(struct ics932s401_data *data)
{
	int m, n, freq;

	m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
	n = data->regs[ICS932S401_REG_SRC_N_CTRL];

	/* Pull in bits 8 & 9 from the M register */
	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;

	freq = BASE_CLOCK * (n + 8) / (m + 2);
	freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] &
			 ICS932S401_SRC_DIVISOR_MASK];

	return freq;
}

static ssize_t show_src_clock(struct device *dev,
			      struct device_attribute *devattr,
			      char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);

	return sprintf(buf, "%d\n", calculate_src_freq(data));
}

static ssize_t show_src_clock_sel(struct device *dev,
				  struct device_attribute *devattr,
				  char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);
	int freq;

	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
		freq = calculate_src_freq(data);
	else
		/* Freq is neatly wrapped up for us */
		if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT &&
		    data->regs[ICS932S401_REG_CTRL] & ICS932S401_SRC_ALT)
			freq = 96000;
		else
			freq = 100000;

	return sprintf(buf, "%d\n", freq);
}

/* Calculate PCI frequency from the SRC M/N registers. */
static int calculate_pci_freq(struct ics932s401_data *data)
{
	int m, n, freq;

	m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
	n = data->regs[ICS932S401_REG_SRC_N_CTRL];

	/* Pull in bits 8 & 9 from the M register */
	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
	n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;

	freq = BASE_CLOCK * (n + 8) / (m + 2);
	freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] >>
			 ICS932S401_PCI_DIVISOR_SHIFT];

	return freq;
}

static ssize_t show_pci_clock(struct device *dev,
			      struct device_attribute *devattr,
			      char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);

	return sprintf(buf, "%d\n", calculate_pci_freq(data));
}

static ssize_t show_pci_clock_sel(struct device *dev,
				  struct device_attribute *devattr,
				  char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);
	int freq;

	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
		freq = calculate_pci_freq(data);
	else
		freq = 33333;

	return sprintf(buf, "%d\n", freq);
}

static ssize_t show_value(struct device *dev,
			  struct device_attribute *devattr,
			  char *buf);

static ssize_t show_spread(struct device *dev,
			   struct device_attribute *devattr,
			   char *buf);

static DEVICE_ATTR(spread_enabled, S_IRUGO, show_spread_enabled, NULL);
static DEVICE_ATTR(cpu_clock_selection, S_IRUGO, show_cpu_clock_sel, NULL);
static DEVICE_ATTR(cpu_clock, S_IRUGO, show_cpu_clock, NULL);
static DEVICE_ATTR(src_clock_selection, S_IRUGO, show_src_clock_sel, NULL);
static DEVICE_ATTR(src_clock, S_IRUGO, show_src_clock, NULL);
static DEVICE_ATTR(pci_clock_selection, S_IRUGO, show_pci_clock_sel, NULL);
static DEVICE_ATTR(pci_clock, S_IRUGO, show_pci_clock, NULL);
static DEVICE_ATTR(usb_clock, S_IRUGO, show_value, NULL);
static DEVICE_ATTR(ref_clock, S_IRUGO, show_value, NULL);
static DEVICE_ATTR(cpu_spread, S_IRUGO, show_spread, NULL);
static DEVICE_ATTR(src_spread, S_IRUGO, show_spread, NULL);

static struct attribute *ics932s401_attr[] = {
	&dev_attr_spread_enabled.attr,
	&dev_attr_cpu_clock_selection.attr,
	&dev_attr_cpu_clock.attr,
	&dev_attr_src_clock_selection.attr,
	&dev_attr_src_clock.attr,
	&dev_attr_pci_clock_selection.attr,
	&dev_attr_pci_clock.attr,
	&dev_attr_usb_clock.attr,
	&dev_attr_ref_clock.attr,
	&dev_attr_cpu_spread.attr,
	&dev_attr_src_spread.attr,
	NULL
};

static ssize_t show_value(struct device *dev,
			  struct device_attribute *devattr,
			  char *buf)
{
	int x;

	if (devattr == &dev_attr_usb_clock)
		x = 48000;
	else if (devattr == &dev_attr_ref_clock)
		x = BASE_CLOCK;
	else
		BUG();

	return sprintf(buf, "%d\n", x);
}

static ssize_t show_spread(struct device *dev,
			   struct device_attribute *devattr,
			   char *buf)
{
	struct ics932s401_data *data = ics932s401_update_device(dev);
	int reg;
	unsigned long val;

	if (!(data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD))
		return sprintf(buf, "0%%\n");

	if (devattr == &dev_attr_src_spread)
		reg = ICS932S401_REG_SRC_SPREAD1;
	else if (devattr == &dev_attr_cpu_spread)
		reg = ICS932S401_REG_CPU_SPREAD1;
	else
		BUG();

	val = data->regs[reg] | (data->regs[reg + 1] << 8);
	val &= ICS932S401_SPREAD_MASK;

	/* Scale 0..2^14 to -0.5. */
	val = 500000 * val / 16384;
	return sprintf(buf, "-0.%lu%%\n", val);
}

/* Return 0 if detection is successful, -ENODEV otherwise */
static int ics932s401_detect(struct i2c_client *client,
			  struct i2c_board_info *info)
{
	struct i2c_adapter *adapter = client->adapter;
	int vendor, device, revision;

	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
		return -ENODEV;

	vendor = i2c_smbus_read_word_data(client, ICS932S401_REG_VENDOR_REV);
	vendor >>= 8;
	revision = vendor >> ICS932S401_REV_SHIFT;
	vendor &= ICS932S401_VENDOR_MASK;
	if (vendor != ICS932S401_VENDOR)
		return -ENODEV;

	device = i2c_smbus_read_word_data(client, ICS932S401_REG_DEVICE);
	device >>= 8;
	if (device != ICS932S401_DEVICE)
		return -ENODEV;

	if (revision != ICS932S401_REV)
		dev_info(&adapter->dev, "Unknown revision %d\n", revision);

	strlcpy(info->type, "ics932s401", I2C_NAME_SIZE);

	return 0;
}

static int ics932s401_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
	struct ics932s401_data *data;
	int err;

	data = kzalloc(sizeof(struct ics932s401_data), GFP_KERNEL);
	if (!data) {
		err = -ENOMEM;
		goto exit;
	}

	i2c_set_clientdata(client, data);
	mutex_init(&data->lock);

	dev_info(&client->dev, "%s chip found\n", client->name);

	/* Register sysfs hooks */
	data->attrs.attrs = ics932s401_attr;
	err = sysfs_create_group(&client->dev.kobj, &data->attrs);
	if (err)
		goto exit_free;

	return 0;

exit_free:
	kfree(data);
exit:
	return err;
}

static int ics932s401_remove(struct i2c_client *client)
{
	struct ics932s401_data *data = i2c_get_clientdata(client);

	sysfs_remove_group(&client->dev.kobj, &data->attrs);
	kfree(data);
	return 0;
}

module_i2c_driver(ics932s401_driver);

MODULE_AUTHOR("Darrick J. Wong <darrick.wong@oracle.com>");
MODULE_DESCRIPTION("ICS932S401 driver");
MODULE_LICENSE("GPL");

/* IBM IntelliStation Z30 */
MODULE_ALIAS("dmi:bvnIBM:*:rn9228:*");
MODULE_ALIAS("dmi:bvnIBM:*:rn9232:*");

/* IBM x3650/x3550 */
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3650*");
MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3550*");
Commit	Line	Data
a412ae3f DW	1	/*
	2	* A driver for the Integrated Circuits ICS932S401
	3	* Copyright (C) 2008 IBM
	4	*
5407e051	5	* Author: Darrick J. Wong <darrick.wong@oracle.com>
a412ae3f DW	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/module.h>
	23	#include <linux/jiffies.h>
	24	#include <linux/i2c.h>
	25	#include <linux/err.h>
	26	#include <linux/mutex.h>
	27	#include <linux/delay.h>
	28	#include <linux/log2.h>
5a0e3ad6	29	#include <linux/slab.h>
a412ae3f DW	30
	31	/* Addresses to scan */
	32	static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END };
	33
a412ae3f DW	34	/* ICS932S401 registers */
a412ae3f DW	35	#define ICS932S401_REG_CFG2 0x01
1e3ae175	36	#define ICS932S401_CFG1_SPREAD 0x01
a412ae3f DW	37	#define ICS932S401_REG_CFG7 0x06
	38	#define ICS932S401_FS_MASK 0x07
	39	#define ICS932S401_REG_VENDOR_REV 0x07
	40	#define ICS932S401_VENDOR 1
	41	#define ICS932S401_VENDOR_MASK 0x0F
	42	#define ICS932S401_REV 4
	43	#define ICS932S401_REV_SHIFT 4
	44	#define ICS932S401_REG_DEVICE 0x09
	45	#define ICS932S401_DEVICE 11
	46	#define ICS932S401_REG_CTRL 0x0A
	47	#define ICS932S401_MN_ENABLED 0x80
	48	#define ICS932S401_CPU_ALT 0x04
	49	#define ICS932S401_SRC_ALT 0x08
	50	#define ICS932S401_REG_CPU_M_CTRL 0x0B
	51	#define ICS932S401_M_MASK 0x3F
	52	#define ICS932S401_REG_CPU_N_CTRL 0x0C
	53	#define ICS932S401_REG_CPU_SPREAD1 0x0D
	54	#define ICS932S401_REG_CPU_SPREAD2 0x0E
	55	#define ICS932S401_SPREAD_MASK 0x7FFF
	56	#define ICS932S401_REG_SRC_M_CTRL 0x0F
	57	#define ICS932S401_REG_SRC_N_CTRL 0x10
	58	#define ICS932S401_REG_SRC_SPREAD1 0x11
	59	#define ICS932S401_REG_SRC_SPREAD2 0x12
	60	#define ICS932S401_REG_CPU_DIVISOR 0x13
1e3ae175	61	#define ICS932S401_CPU_DIVISOR_SHIFT 4
a412ae3f DW	62	#define ICS932S401_REG_PCISRC_DIVISOR 0x14
	63	#define ICS932S401_SRC_DIVISOR_MASK 0x0F
	64	#define ICS932S401_PCI_DIVISOR_SHIFT 4
	65
	66	/* Base clock is 14.318MHz */
	67	#define BASE_CLOCK 14318
	68
	69	#define NUM_REGS 21
	70	#define NUM_MIRRORED_REGS 15
	71
	72	static int regs_to_copy[NUM_MIRRORED_REGS] = {
	73	ICS932S401_REG_CFG2,
	74	ICS932S401_REG_CFG7,
	75	ICS932S401_REG_VENDOR_REV,
	76	ICS932S401_REG_DEVICE,
	77	ICS932S401_REG_CTRL,
	78	ICS932S401_REG_CPU_M_CTRL,
	79	ICS932S401_REG_CPU_N_CTRL,
	80	ICS932S401_REG_CPU_SPREAD1,
	81	ICS932S401_REG_CPU_SPREAD2,
	82	ICS932S401_REG_SRC_M_CTRL,
	83	ICS932S401_REG_SRC_N_CTRL,
	84	ICS932S401_REG_SRC_SPREAD1,
	85	ICS932S401_REG_SRC_SPREAD2,
	86	ICS932S401_REG_CPU_DIVISOR,
	87	ICS932S401_REG_PCISRC_DIVISOR,
	88	};
	89
	90	/* How often do we reread sensors values? (In jiffies) */
	91	#define SENSOR_REFRESH_INTERVAL (2 * HZ)
	92
	93	/* How often do we reread sensor limit values? (In jiffies) */
	94	#define LIMIT_REFRESH_INTERVAL (60 * HZ)
	95
	96	struct ics932s401_data {
	97	struct attribute_group attrs;
	98	struct mutex lock;
	99	char sensors_valid;
	100	unsigned long sensors_last_updated; /* In jiffies */
	101
	102	u8 regs[NUM_REGS];
	103	};
	104
	105	static int ics932s401_probe(struct i2c_client *client,
	106	const struct i2c_device_id *id);
310ec792	107	static int ics932s401_detect(struct i2c_client *client,
a412ae3f DW	108	struct i2c_board_info *info);
	109	static int ics932s401_remove(struct i2c_client *client);
	110
	111	static const struct i2c_device_id ics932s401_id[] = {
1f86df49	112	{ "ics932s401", 0 },
a412ae3f DW	113	{ }
	114	};
	115	MODULE_DEVICE_TABLE(i2c, ics932s401_id);
	116
	117	static struct i2c_driver ics932s401_driver = {
	118	.class = I2C_CLASS_HWMON,
	119	.driver = {
	120	.name = "ics932s401",
	121	},
	122	.probe = ics932s401_probe,
	123	.remove = ics932s401_remove,
	124	.id_table = ics932s401_id,
	125	.detect = ics932s401_detect,
c3813d6a	126	.address_list = normal_i2c,
a412ae3f DW	127	};
	128
	129	static struct ics932s401_data ics932s401_update_device(struct device dev)
	130	{
	131	struct i2c_client *client = to_i2c_client(dev);
	132	struct ics932s401_data *data = i2c_get_clientdata(client);
	133	unsigned long local_jiffies = jiffies;
	134	int i, temp;
	135
	136	mutex_lock(&data->lock);
	137	if (time_before(local_jiffies, data->sensors_last_updated +
	138	SENSOR_REFRESH_INTERVAL)
	139	&& data->sensors_valid)
	140	goto out;
	141
	142	/*
	143	* Each register must be read as a word and then right shifted 8 bits.
	144	* Not really sure why this is; setting the "byte count programming"
	145	* register to 1 does not fix this problem.
	146	*/
	147	for (i = 0; i < NUM_MIRRORED_REGS; i++) {
	148	temp = i2c_smbus_read_word_data(client, regs_to_copy[i]);
	149	data->regs[regs_to_copy[i]] = temp >> 8;
	150	}
	151
	152	data->sensors_last_updated = local_jiffies;
	153	data->sensors_valid = 1;
	154
	155	out:
	156	mutex_unlock(&data->lock);
	157	return data;
	158	}
	159
	160	static ssize_t show_spread_enabled(struct device *dev,
	161	struct device_attribute *devattr,
	162	char *buf)
	163	{
	164	struct ics932s401_data *data = ics932s401_update_device(dev);
	165
	166	if (data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD)
	167	return sprintf(buf, "1\n");
	168
	169	return sprintf(buf, "0\n");
	170	}
	171
	172	/* bit to cpu khz map */
	173	static const int fs_speeds[] = {
	174	266666,
	175	133333,
	176	200000,
	177	166666,
	178	333333,
	179	100000,
	180	400000,
	181	0,
	182	};
	183
	184	/* clock divisor map */
	185	static const int divisors[] = {2, 3, 5, 15, 4, 6, 10, 30, 8, 12, 20, 60, 16,
	186	24, 40, 120};
	187
	188	/* Calculate CPU frequency from the M/N registers. */
	189	static int calculate_cpu_freq(struct ics932s401_data *data)
	190	{
191	int m, n, freq;
192
193	m = data->regs[ICS932S401_REG_CPU_M_CTRL] & ICS932S401_M_MASK;
194	n = data->regs[ICS932S401_REG_CPU_N_CTRL];
195
196	/* Pull in bits 8 & 9 from the M register */
197	n \|= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x80) << 1;
198	n \|= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x40) << 3;
199
200	freq = BASE_CLOCK * (n + 8) / (m + 2);
201	freq /= divisors[data->regs[ICS932S401_REG_CPU_DIVISOR] >>
202	ICS932S401_CPU_DIVISOR_SHIFT];
203
204	return freq;
205	}
206
207	static ssize_t show_cpu_clock(struct device *dev,
208	struct device_attribute *devattr,
209	char *buf)
210	{
211	struct ics932s401_data *data = ics932s401_update_device(dev);
212
213	return sprintf(buf, "%d\n", calculate_cpu_freq(data));
214	}
215
216	static ssize_t show_cpu_clock_sel(struct device *dev,
217	struct device_attribute *devattr,
218	char *buf)
219	{
220	struct ics932s401_data *data = ics932s401_update_device(dev);
221	int freq;
222
223	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
224	freq = calculate_cpu_freq(data);
225	else {
226	/* Freq is neatly wrapped up for us */
227	int fid = data->regs[ICS932S401_REG_CFG7] & ICS932S401_FS_MASK;
67d0833f	228
a412ae3f DW	229	freq = fs_speeds[fid];
	230	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT) {
	231	switch (freq) {
	232	case 166666:
	233	freq = 160000;
	234	break;
	235	case 333333:
	236	freq = 320000;
	237	break;
	238	}
	239	}
	240	}
	241
	242	return sprintf(buf, "%d\n", freq);
	243	}
	244
	245	/* Calculate SRC frequency from the M/N registers. */
	246	static int calculate_src_freq(struct ics932s401_data *data)
	247	{
	248	int m, n, freq;
	249
	250	m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
	251	n = data->regs[ICS932S401_REG_SRC_N_CTRL];
	252
	253	/* Pull in bits 8 & 9 from the M register */
	254	n \|= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
	255	n \|= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
	256
	257	freq = BASE_CLOCK * (n + 8) / (m + 2);
	258	freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] &
	259	ICS932S401_SRC_DIVISOR_MASK];
	260
	261	return freq;
	262	}
	263
	264	static ssize_t show_src_clock(struct device *dev,
	265	struct device_attribute *devattr,
	266	char *buf)
	267	{
	268	struct ics932s401_data *data = ics932s401_update_device(dev);
	269
	270	return sprintf(buf, "%d\n", calculate_src_freq(data));
	271	}
	272
	273	static ssize_t show_src_clock_sel(struct device *dev,
	274	struct device_attribute *devattr,
	275	char *buf)
	276	{
	277	struct ics932s401_data *data = ics932s401_update_device(dev);
	278	int freq;
	279
	280	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
	281	freq = calculate_src_freq(data);
	282	else
	283	/* Freq is neatly wrapped up for us */
	284	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT &&
	285	data->regs[ICS932S401_REG_CTRL] & ICS932S401_SRC_ALT)
	286	freq = 96000;
	287	else
	288	freq = 100000;
	289
	290	return sprintf(buf, "%d\n", freq);
	291	}
	292
293	/* Calculate PCI frequency from the SRC M/N registers. */
294	static int calculate_pci_freq(struct ics932s401_data *data)
295	{
296	int m, n, freq;
297
298	m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
299	n = data->regs[ICS932S401_REG_SRC_N_CTRL];
300
301	/* Pull in bits 8 & 9 from the M register */
302	n \|= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
303	n \|= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
304
305	freq = BASE_CLOCK * (n + 8) / (m + 2);
306	freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] >>
307	ICS932S401_PCI_DIVISOR_SHIFT];
308
309	return freq;
310	}
311
312	static ssize_t show_pci_clock(struct device *dev,
313	struct device_attribute *devattr,
314	char *buf)
315	{
316	struct ics932s401_data *data = ics932s401_update_device(dev);
317
318	return sprintf(buf, "%d\n", calculate_pci_freq(data));
319	}
320
321	static ssize_t show_pci_clock_sel(struct device *dev,
322	struct device_attribute *devattr,
323	char *buf)
324	{
325	struct ics932s401_data *data = ics932s401_update_device(dev);
326	int freq;
327
328	if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
329	freq = calculate_pci_freq(data);
330	else
331	freq = 33333;
332
333	return sprintf(buf, "%d\n", freq);
334	}
335
336	static ssize_t show_value(struct device *dev,
337	struct device_attribute *devattr,
338	char *buf);
339
340	static ssize_t show_spread(struct device *dev,
341	struct device_attribute *devattr,
342	char *buf);
343
344	static DEVICE_ATTR(spread_enabled, S_IRUGO, show_spread_enabled, NULL);
345	static DEVICE_ATTR(cpu_clock_selection, S_IRUGO, show_cpu_clock_sel, NULL);
346	static DEVICE_ATTR(cpu_clock, S_IRUGO, show_cpu_clock, NULL);
347	static DEVICE_ATTR(src_clock_selection, S_IRUGO, show_src_clock_sel, NULL);
348	static DEVICE_ATTR(src_clock, S_IRUGO, show_src_clock, NULL);
349	static DEVICE_ATTR(pci_clock_selection, S_IRUGO, show_pci_clock_sel, NULL);
350	static DEVICE_ATTR(pci_clock, S_IRUGO, show_pci_clock, NULL);
351	static DEVICE_ATTR(usb_clock, S_IRUGO, show_value, NULL);
352	static DEVICE_ATTR(ref_clock, S_IRUGO, show_value, NULL);
353	static DEVICE_ATTR(cpu_spread, S_IRUGO, show_spread, NULL);
354	static DEVICE_ATTR(src_spread, S_IRUGO, show_spread, NULL);
355
3288de12	356	static struct attribute *ics932s401_attr[] = {
a412ae3f DW	357	&dev_attr_spread_enabled.attr,
	358	&dev_attr_cpu_clock_selection.attr,
	359	&dev_attr_cpu_clock.attr,
	360	&dev_attr_src_clock_selection.attr,
	361	&dev_attr_src_clock.attr,
	362	&dev_attr_pci_clock_selection.attr,
	363	&dev_attr_pci_clock.attr,
	364	&dev_attr_usb_clock.attr,
	365	&dev_attr_ref_clock.attr,
	366	&dev_attr_cpu_spread.attr,
	367	&dev_attr_src_spread.attr,
	368	NULL
	369	};
	370
	371	static ssize_t show_value(struct device *dev,
	372	struct device_attribute *devattr,
	373	char *buf)
	374	{
	375	int x;
	376
	377	if (devattr == &dev_attr_usb_clock)
	378	x = 48000;
	379	else if (devattr == &dev_attr_ref_clock)
	380	x = BASE_CLOCK;
	381	else
	382	BUG();
	383
	384	return sprintf(buf, "%d\n", x);
	385	}
	386
	387	static ssize_t show_spread(struct device *dev,
	388	struct device_attribute *devattr,
	389	char *buf)
	390	{
	391	struct ics932s401_data *data = ics932s401_update_device(dev);
	392	int reg;
	393	unsigned long val;
	394
	395	if (!(data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD))
	396	return sprintf(buf, "0%%\n");
	397
	398	if (devattr == &dev_attr_src_spread)
	399	reg = ICS932S401_REG_SRC_SPREAD1;
	400	else if (devattr == &dev_attr_cpu_spread)
	401	reg = ICS932S401_REG_CPU_SPREAD1;
	402	else
	403	BUG();
	404
	405	val = data->regs[reg] \| (data->regs[reg + 1] << 8);
	406	val &= ICS932S401_SPREAD_MASK;
	407
	408	/* Scale 0..2^14 to -0.5. */
	409	val = 500000 * val / 16384;
	410	return sprintf(buf, "-0.%lu%%\n", val);
	411	}
	412
	413	/* Return 0 if detection is successful, -ENODEV otherwise */
310ec792	414	static int ics932s401_detect(struct i2c_client *client,
a412ae3f DW	415	struct i2c_board_info *info)
	416	{
	417	struct i2c_adapter *adapter = client->adapter;
c2e90e9b	418	int vendor, device, revision;
a412ae3f DW	419
	420	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
	421	return -ENODEV;
	422
c2e90e9b JD	423	vendor = i2c_smbus_read_word_data(client, ICS932S401_REG_VENDOR_REV);
	424	vendor >>= 8;
	425	revision = vendor >> ICS932S401_REV_SHIFT;
	426	vendor &= ICS932S401_VENDOR_MASK;
	427	if (vendor != ICS932S401_VENDOR)
	428	return -ENODEV;
	429
	430	device = i2c_smbus_read_word_data(client, ICS932S401_REG_DEVICE);
	431	device >>= 8;
	432	if (device != ICS932S401_DEVICE)
	433	return -ENODEV;
	434
	435	if (revision != ICS932S401_REV)
	436	dev_info(&adapter->dev, "Unknown revision %d\n", revision);
a412ae3f DW	437
	438	strlcpy(info->type, "ics932s401", I2C_NAME_SIZE);
	439
	440	return 0;
	441	}
	442
	443	static int ics932s401_probe(struct i2c_client *client,
	444	const struct i2c_device_id *id)
	445	{
	446	struct ics932s401_data *data;
	447	int err;
	448
	449	data = kzalloc(sizeof(struct ics932s401_data), GFP_KERNEL);
	450	if (!data) {
	451	err = -ENOMEM;
	452	goto exit;
	453	}
	454
	455	i2c_set_clientdata(client, data);
	456	mutex_init(&data->lock);
	457
	458	dev_info(&client->dev, "%s chip found\n", client->name);
	459
	460	/* Register sysfs hooks */
	461	data->attrs.attrs = ics932s401_attr;
	462	err = sysfs_create_group(&client->dev.kobj, &data->attrs);
	463	if (err)
	464	goto exit_free;
	465
	466	return 0;
	467
	468	exit_free:
	469	kfree(data);
	470	exit:
	471	return err;
	472	}
	473
	474	static int ics932s401_remove(struct i2c_client *client)
	475	{
	476	struct ics932s401_data *data = i2c_get_clientdata(client);
	477
	478	sysfs_remove_group(&client->dev.kobj, &data->attrs);
	479	kfree(data);
	480	return 0;
	481	}
	482
a64fe2ed	483	module_i2c_driver(ics932s401_driver);
a412ae3f	484
5407e051	485	MODULE_AUTHOR("Darrick J. Wong <darrick.wong@oracle.com>");
a412ae3f DW	486	MODULE_DESCRIPTION("ICS932S401 driver");
	487	MODULE_LICENSE("GPL");
	488
a412ae3f DW	489	/* IBM IntelliStation Z30 */
	490	MODULE_ALIAS("dmi:bvnIBM::rn9228:");
	491	MODULE_ALIAS("dmi:bvnIBM::rn9232:");
	492
	493	/* IBM x3650/x3550 */
	494	MODULE_ALIAS("dmi:bvnIBM::pnIBMSystemx3650");
	495	MODULE_ALIAS("dmi:bvnIBM::pnIBMSystemx3550");