[linux-2.6-block.git] / drivers / misc / habanalabs / goya / goyaP.h

/* SPDX-License-Identifier: GPL-2.0
 *
 * Copyright 2016-2019 HabanaLabs, Ltd.
 * All Rights Reserved.
 *
 */

#ifndef GOYAP_H_
#define GOYAP_H_

#include <uapi/misc/habanalabs.h>
#include "habanalabs.h"
#include "include/hl_boot_if.h"
#include "include/goya/goya_packets.h"
#include "include/goya/goya.h"
#include "include/goya/goya_async_events.h"
#include "include/goya/goya_fw_if.h"

#define NUMBER_OF_CMPLT_QUEUES		5
#define NUMBER_OF_EXT_HW_QUEUES		5
#define NUMBER_OF_CPU_HW_QUEUES		1
#define NUMBER_OF_INT_HW_QUEUES		9
#define NUMBER_OF_HW_QUEUES		(NUMBER_OF_EXT_HW_QUEUES + \
					NUMBER_OF_CPU_HW_QUEUES + \
					NUMBER_OF_INT_HW_QUEUES)

/*
 * Number of MSIX interrupts IDS:
 * Each completion queue has 1 ID
 * The event queue has 1 ID
 */
#define NUMBER_OF_INTERRUPTS		(NUMBER_OF_CMPLT_QUEUES + 1)

#if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES)
#error "Number of H/W queues must be smaller than HL_MAX_QUEUES"
#endif

#if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
#endif

#define QMAN_FENCE_TIMEOUT_USEC		10000		/* 10 ms */

#define QMAN_STOP_TIMEOUT_USEC		100000		/* 100 ms */

#define CORESIGHT_TIMEOUT_USEC		100000		/* 100 ms */

#define GOYA_CPU_TIMEOUT_USEC		10000000	/* 10s */

#define TPC_ENABLED_MASK		0xFF

#define PLL_HIGH_DEFAULT		1575000000	/* 1.575 GHz */

#define MAX_POWER_DEFAULT		200000		/* 200W */

#define DRAM_PHYS_DEFAULT_SIZE		0x100000000ull	/* 4GB */

/* DRAM Memory Map */

#define CPU_FW_IMAGE_SIZE		0x10000000	/* 256MB */
#define MMU_PAGE_TABLES_SIZE		0x0FC00000	/* 252MB */
#define MMU_DRAM_DEFAULT_PAGE_SIZE	0x00200000	/* 2MB */
#define MMU_CACHE_MNG_SIZE		0x00001000	/* 4KB */

#define CPU_FW_IMAGE_ADDR		DRAM_PHYS_BASE
#define MMU_PAGE_TABLES_ADDR		(CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
#define MMU_DRAM_DEFAULT_PAGE_ADDR	(MMU_PAGE_TABLES_ADDR + \
						MMU_PAGE_TABLES_SIZE)
#define MMU_CACHE_MNG_ADDR		(MMU_DRAM_DEFAULT_PAGE_ADDR + \
					MMU_DRAM_DEFAULT_PAGE_SIZE)
#define DRAM_KMD_END_ADDR		(MMU_CACHE_MNG_ADDR + \
						MMU_CACHE_MNG_SIZE)

#define DRAM_BASE_ADDR_USER		0x20000000

#if (DRAM_KMD_END_ADDR > DRAM_BASE_ADDR_USER)
#error "KMD must reserve no more than 512MB"
#endif

/*
 * SRAM Memory Map for KMD
 *
 * KMD occupies KMD_SRAM_SIZE bytes from the start of SRAM. It is used for
 * MME/TPC QMANs
 *
 */

#define MME_QMAN_BASE_OFFSET	0x000000	/* Must be 0 */
#define MME_QMAN_LENGTH		64
#define TPC_QMAN_LENGTH		64

#define TPC0_QMAN_BASE_OFFSET	(MME_QMAN_BASE_OFFSET + \
				(MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
#define TPC1_QMAN_BASE_OFFSET	(TPC0_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
#define TPC2_QMAN_BASE_OFFSET	(TPC1_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
#define TPC3_QMAN_BASE_OFFSET	(TPC2_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
#define TPC4_QMAN_BASE_OFFSET	(TPC3_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
#define TPC5_QMAN_BASE_OFFSET	(TPC4_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
#define TPC6_QMAN_BASE_OFFSET	(TPC5_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
#define TPC7_QMAN_BASE_OFFSET	(TPC6_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))

#define SRAM_KMD_RES_OFFSET	(TPC7_QMAN_BASE_OFFSET + \
				(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))

#if (SRAM_KMD_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
#error "MME/TPC QMANs SRAM space exceeds limit"
#endif

#define SRAM_USER_BASE_OFFSET	GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START

/* Virtual address space */
#define VA_HOST_SPACE_START	0x1000000000000ull	/* 256TB */
#define VA_HOST_SPACE_END	0x3FF8000000000ull	/* 1PB - 1TB */
#define VA_HOST_SPACE_SIZE	(VA_HOST_SPACE_END - \
					VA_HOST_SPACE_START) /* 767TB */

#define VA_DDR_SPACE_START	0x800000000ull		/* 32GB */
#define VA_DDR_SPACE_END	0x2000000000ull		/* 128GB */
#define VA_DDR_SPACE_SIZE	(VA_DDR_SPACE_END - \
					VA_DDR_SPACE_START)	/* 128GB */

#if (HL_CPU_ACCESSIBLE_MEM_SIZE != SZ_2M)
#error "HL_CPU_ACCESSIBLE_MEM_SIZE must be exactly 2MB to enable MMU mapping"
#endif

#define VA_CPU_ACCESSIBLE_MEM_ADDR	0x8000000000ull

#define DMA_MAX_TRANSFER_SIZE	U32_MAX

#define HW_CAP_PLL		0x00000001
#define HW_CAP_DDR_0		0x00000002
#define HW_CAP_DDR_1		0x00000004
#define HW_CAP_MME		0x00000008
#define HW_CAP_CPU		0x00000010
#define HW_CAP_DMA		0x00000020
#define HW_CAP_MSIX		0x00000040
#define HW_CAP_CPU_Q		0x00000080
#define HW_CAP_MMU		0x00000100
#define HW_CAP_TPC_MBIST	0x00000200
#define HW_CAP_GOLDEN		0x00000400
#define HW_CAP_TPC		0x00000800

enum goya_fw_component {
	FW_COMP_UBOOT,
	FW_COMP_PREBOOT
};

struct goya_device {
	/* TODO: remove hw_queues_lock after moving to scheduler code */
	spinlock_t	hw_queues_lock;

	u64		mme_clk;
	u64		tpc_clk;
	u64		ic_clk;

	u64		ddr_bar_cur_addr;
	u32		events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
	u32		hw_cap_initialized;
	u8		device_cpu_mmu_mappings_done;
};

void goya_get_fixed_properties(struct hl_device *hdev);
int goya_mmu_init(struct hl_device *hdev);
void goya_init_dma_qmans(struct hl_device *hdev);
void goya_init_mme_qmans(struct hl_device *hdev);
void goya_init_tpc_qmans(struct hl_device *hdev);
int goya_init_cpu_queues(struct hl_device *hdev);
void goya_init_security(struct hl_device *hdev);
int goya_late_init(struct hl_device *hdev);
void goya_late_fini(struct hl_device *hdev);

void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd);
void goya_update_eq_ci(struct hl_device *hdev, u32 val);
void goya_restore_phase_topology(struct hl_device *hdev);
int goya_context_switch(struct hl_device *hdev, u32 asid);

int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
			u8 i2c_addr, u8 i2c_reg, u32 *val);
int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
			u8 i2c_addr, u8 i2c_reg, u32 val);
void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);

int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
int goya_test_queues(struct hl_device *hdev);
int goya_test_cpu_queue(struct hl_device *hdev);
int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
				u32 timeout, long *result);

long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
			long value);
u64 goya_get_max_power(struct hl_device *hdev);
void goya_set_max_power(struct hl_device *hdev, u64 value);

void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
void goya_add_device_attr(struct hl_device *hdev,
			struct attribute_group *dev_attr_grp);
int goya_armcp_info_get(struct hl_device *hdev);
int goya_debug_coresight(struct hl_device *hdev, void *data);
void goya_halt_coresight(struct hl_device *hdev);

int goya_suspend(struct hl_device *hdev);
int goya_resume(struct hl_device *hdev);

void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
void *goya_get_events_stat(struct hl_device *hdev, u32 *size);

void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address,
				u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec);
int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
				dma_addr_t *dma_handle,	u16 *queue_len);
u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
int goya_send_heartbeat(struct hl_device *hdev);
void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
					dma_addr_t *dma_handle);
void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
					void *vaddr);
void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);

#endif /* GOYAP_H_ */
Commit	Line	Data
99b9d7b4 OG	1	/* SPDX-License-Identifier: GPL-2.0
	2	*
	3	* Copyright 2016-2019 HabanaLabs, Ltd.
	4	* All Rights Reserved.
	5	*
	6	*/
	7
	8	#ifndef GOYAP_H_
	9	#define GOYAP_H_
	10
	11	#include <uapi/misc/habanalabs.h>
	12	#include "habanalabs.h"
839c4803	13	#include "include/hl_boot_if.h"
9494a8dd	14	#include "include/goya/goya_packets.h"
99b9d7b4	15	#include "include/goya/goya.h"
9494a8dd	16	#include "include/goya/goya_async_events.h"
839c4803	17	#include "include/goya/goya_fw_if.h"
99b9d7b4 OG	18
	19	#define NUMBER_OF_CMPLT_QUEUES 5
	20	#define NUMBER_OF_EXT_HW_QUEUES 5
	21	#define NUMBER_OF_CPU_HW_QUEUES 1
	22	#define NUMBER_OF_INT_HW_QUEUES 9
	23	#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
	24	NUMBER_OF_CPU_HW_QUEUES + \
	25	NUMBER_OF_INT_HW_QUEUES)
	26
	27	/*
	28	* Number of MSIX interrupts IDS:
	29	* Each completion queue has 1 ID
	30	* The event queue has 1 ID
	31	*/
	32	#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + 1)
	33
	34	#if (NUMBER_OF_HW_QUEUES >= HL_MAX_QUEUES)
	35	#error "Number of H/W queues must be smaller than HL_MAX_QUEUES"
	36	#endif
	37
	38	#if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
	39	#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
	40	#endif
	41
bedd1442	42	#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */
99b9d7b4	43
bedd1442	44	#define QMAN_STOP_TIMEOUT_USEC 100000 /* 100 ms */
99b9d7b4	45
bedd1442 OG	46	#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
	47
	48	#define GOYA_CPU_TIMEOUT_USEC 10000000 /* 10s */
8ba2876d	49
99b9d7b4 OG	50	#define TPC_ENABLED_MASK 0xFF
	51
	52	#define PLL_HIGH_DEFAULT 1575000000 /* 1.575 GHz */
	53
d91389bc OG	54	#define MAX_POWER_DEFAULT 200000 /* 200W */
d91389bc OG	55
99b9d7b4 OG	56	#define DRAM_PHYS_DEFAULT_SIZE 0x100000000ull /* 4GB */
	57
	58	/* DRAM Memory Map */
	59
27ca384c	60	#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
e0a29952	61	#define MMU_PAGE_TABLES_SIZE 0x0FC00000 /* 252MB */
27ca384c OS	62	#define MMU_DRAM_DEFAULT_PAGE_SIZE 0x00200000 /* 2MB */
27ca384c OS	63	#define MMU_CACHE_MNG_SIZE 0x00001000 /* 4KB */
27ca384c OS	64
	65	#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
	66	#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
	67	#define MMU_DRAM_DEFAULT_PAGE_ADDR (MMU_PAGE_TABLES_ADDR + \
	68	MMU_PAGE_TABLES_SIZE)
	69	#define MMU_CACHE_MNG_ADDR (MMU_DRAM_DEFAULT_PAGE_ADDR + \
	70	MMU_DRAM_DEFAULT_PAGE_SIZE)
e0a29952	71	#define DRAM_KMD_END_ADDR (MMU_CACHE_MNG_ADDR + \
27ca384c	72	MMU_CACHE_MNG_SIZE)
99b9d7b4	73
e0a29952 OG	74	#define DRAM_BASE_ADDR_USER 0x20000000
	75
	76	#if (DRAM_KMD_END_ADDR > DRAM_BASE_ADDR_USER)
	77	#error "KMD must reserve no more than 512MB"
99b9d7b4 OG	78	#endif
	79
	80	/*
	81	* SRAM Memory Map for KMD
	82	*
	83	* KMD occupies KMD_SRAM_SIZE bytes from the start of SRAM. It is used for
	84	* MME/TPC QMANs
	85	*
	86	*/
	87
	88	#define MME_QMAN_BASE_OFFSET 0x000000 /* Must be 0 */
	89	#define MME_QMAN_LENGTH 64
	90	#define TPC_QMAN_LENGTH 64
	91
	92	#define TPC0_QMAN_BASE_OFFSET (MME_QMAN_BASE_OFFSET + \
	93	(MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	94	#define TPC1_QMAN_BASE_OFFSET (TPC0_QMAN_BASE_OFFSET + \
	95	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	96	#define TPC2_QMAN_BASE_OFFSET (TPC1_QMAN_BASE_OFFSET + \
	97	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	98	#define TPC3_QMAN_BASE_OFFSET (TPC2_QMAN_BASE_OFFSET + \
	99	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	100	#define TPC4_QMAN_BASE_OFFSET (TPC3_QMAN_BASE_OFFSET + \
	101	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	102	#define TPC5_QMAN_BASE_OFFSET (TPC4_QMAN_BASE_OFFSET + \
	103	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	104	#define TPC6_QMAN_BASE_OFFSET (TPC5_QMAN_BASE_OFFSET + \
	105	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	106	#define TPC7_QMAN_BASE_OFFSET (TPC6_QMAN_BASE_OFFSET + \
	107	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	108
	109	#define SRAM_KMD_RES_OFFSET (TPC7_QMAN_BASE_OFFSET + \
	110	(TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
	111
	112	#if (SRAM_KMD_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
	113	#error "MME/TPC QMANs SRAM space exceeds limit"
	114	#endif
	115
	116	#define SRAM_USER_BASE_OFFSET GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
	117
	118	/* Virtual address space */
	119	#define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */
	120	#define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */
	121	#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
	122	VA_HOST_SPACE_START) /* 767TB */
	123
	124	#define VA_DDR_SPACE_START 0x800000000ull /* 32GB */
	125	#define VA_DDR_SPACE_END 0x2000000000ull /* 128GB */
	126	#define VA_DDR_SPACE_SIZE (VA_DDR_SPACE_END - \
	127	VA_DDR_SPACE_START) /* 128GB */
	128
95b5a8b8 OG	129	#if (HL_CPU_ACCESSIBLE_MEM_SIZE != SZ_2M)
	130	#error "HL_CPU_ACCESSIBLE_MEM_SIZE must be exactly 2MB to enable MMU mapping"
	131	#endif
	132
	133	#define VA_CPU_ACCESSIBLE_MEM_ADDR 0x8000000000ull
	134
e99f1683	135	#define DMA_MAX_TRANSFER_SIZE U32_MAX
99b9d7b4 OG	136
	137	#define HW_CAP_PLL 0x00000001
	138	#define HW_CAP_DDR_0 0x00000002
	139	#define HW_CAP_DDR_1 0x00000004
	140	#define HW_CAP_MME 0x00000008
	141	#define HW_CAP_CPU 0x00000010
	142	#define HW_CAP_DMA 0x00000020
	143	#define HW_CAP_MSIX 0x00000040
	144	#define HW_CAP_CPU_Q 0x00000080
	145	#define HW_CAP_MMU 0x00000100
	146	#define HW_CAP_TPC_MBIST 0x00000200
	147	#define HW_CAP_GOLDEN 0x00000400
	148	#define HW_CAP_TPC 0x00000800
	149
99b9d7b4 OG	150	enum goya_fw_component {
	151	FW_COMP_UBOOT,
	152	FW_COMP_PREBOOT
	153	};
	154
	155	struct goya_device {
	156	/* TODO: remove hw_queues_lock after moving to scheduler code */
	157	spinlock_t hw_queues_lock;
d91389bc OG	158
	159	u64 mme_clk;
	160	u64 tpc_clk;
	161	u64 ic_clk;
	162
99b9d7b4	163	u64 ddr_bar_cur_addr;
1251f23a	164	u32 events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
99b9d7b4	165	u32 hw_cap_initialized;
95b5a8b8	166	u8 device_cpu_mmu_mappings_done;
99b9d7b4 OG	167	};
99b9d7b4 OG	168
b2377e03 OG	169	void goya_get_fixed_properties(struct hl_device *hdev);
	170	int goya_mmu_init(struct hl_device *hdev);
	171	void goya_init_dma_qmans(struct hl_device *hdev);
	172	void goya_init_mme_qmans(struct hl_device *hdev);
	173	void goya_init_tpc_qmans(struct hl_device *hdev);
	174	int goya_init_cpu_queues(struct hl_device *hdev);
	175	void goya_init_security(struct hl_device *hdev);
	176	int goya_late_init(struct hl_device *hdev);
	177	void goya_late_fini(struct hl_device *hdev);
	178
	179	void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
b9040c99	180	void goya_pqe_write(struct hl_device hdev, __le64 pqe, struct hl_bd *bd);
b2377e03 OG	181	void goya_update_eq_ci(struct hl_device *hdev, u32 val);
	182	void goya_restore_phase_topology(struct hl_device *hdev);
	183	int goya_context_switch(struct hl_device *hdev, u32 asid);
	184
c2164773 OG	185	int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
	186	u8 i2c_addr, u8 i2c_reg, u32 *val);
	187	int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
	188	u8 i2c_addr, u8 i2c_reg, u32 val);
b2377e03 OG	189	void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);
	190
	191	int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
	192	int goya_test_queues(struct hl_device *hdev);
9494a8dd OG	193	int goya_test_cpu_queue(struct hl_device *hdev);
	194	int goya_send_cpu_message(struct hl_device hdev, u32 msg, u16 len,
	195	u32 timeout, long *result);
b2377e03	196
d91389bc OG	197	long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
	198	long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
	199	long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
	200	long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
	201	long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
	202	void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
	203	long value);
b2377e03 OG	204	u64 goya_get_max_power(struct hl_device *hdev);
	205	void goya_set_max_power(struct hl_device *hdev, u64 value);
	206
d91389bc OG	207	void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
	208	void goya_add_device_attr(struct hl_device *hdev,
	209	struct attribute_group *dev_attr_grp);
393e5b55	210	int goya_armcp_info_get(struct hl_device *hdev);
315bc055	211	int goya_debug_coresight(struct hl_device hdev, void data);
89225ce4	212	void goya_halt_coresight(struct hl_device *hdev);
b2377e03	213
5e6e0239 OG	214	int goya_suspend(struct hl_device *hdev);
5e6e0239 OG	215	int goya_resume(struct hl_device *hdev);
b2377e03	216
5e6e0239 OG	217	void goya_handle_eqe(struct hl_device hdev, struct hl_eq_entry eq_entry);
5e6e0239 OG	218	void goya_get_events_stat(struct hl_device hdev, u32 *size);
b2377e03	219
921a465b OG	220	void goya_add_end_of_cb_packets(struct hl_device *hdev, u64 kernel_address,
921a465b OG	221	u32 len, u64 cq_addr, u32 cq_val, u32 msix_vec);
5e6e0239 OG	222	int goya_cs_parser(struct hl_device hdev, struct hl_cs_parser parser);
5e6e0239 OG	223	void goya_get_int_queue_base(struct hl_device hdev, u32 queue_id,
b2377e03	224	dma_addr_t dma_handle, u16 queue_len);
5e6e0239	225	u32 goya_get_dma_desc_list_size(struct hl_device hdev, struct sg_table sgt);
5e6e0239	226	int goya_send_heartbeat(struct hl_device *hdev);
bedd1442 OG	227	void goya_cpu_accessible_dma_pool_alloc(struct hl_device hdev, size_t size,
	228	dma_addr_t *dma_handle);
	229	void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
	230	void *vaddr);
95b5a8b8	231	void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
5e6e0239	232
99b9d7b4	233	#endif /* GOYAP_H_ */