[linux-2.6-block.git] / drivers / misc / eeprom / eeprom_93xx46.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for 93xx46 EEPROMs
 *
 * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
 */

#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
#include <linux/kernel.h>
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/spi/spi.h>
#include <linux/nvmem-provider.h>
#include <linux/eeprom_93xx46.h>

#define OP_START	0x4
#define OP_WRITE	(OP_START | 0x1)
#define OP_READ		(OP_START | 0x2)
#define ADDR_EWDS	0x00
#define ADDR_ERAL	0x20
#define ADDR_EWEN	0x30

struct eeprom_93xx46_devtype_data {
	unsigned int quirks;
	unsigned char flags;
};

static const struct eeprom_93xx46_devtype_data at93c46_data = {
	.flags = EE_SIZE1K,
};

static const struct eeprom_93xx46_devtype_data at93c56_data = {
	.flags = EE_SIZE2K,
};

static const struct eeprom_93xx46_devtype_data at93c66_data = {
	.flags = EE_SIZE4K,
};

static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
	.flags = EE_SIZE1K,
	.quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ |
		  EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
};

static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = {
	.flags = EE_SIZE1K,
	.quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE,
};

struct eeprom_93xx46_dev {
	struct spi_device *spi;
	struct eeprom_93xx46_platform_data *pdata;
	struct mutex lock;
	struct nvmem_config nvmem_config;
	struct nvmem_device *nvmem;
	int addrlen;
	int size;
};

static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
{
	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
}

static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
{
	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
}

static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
{
	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
}

static int eeprom_93xx46_read(void *priv, unsigned int off,
			      void *val, size_t count)
{
	struct eeprom_93xx46_dev *edev = priv;
	char *buf = val;
	int err = 0;
	int bits;

	if (unlikely(off >= edev->size))
		return 0;
	if ((off + count) > edev->size)
		count = edev->size - off;
	if (unlikely(!count))
		return count;

	mutex_lock(&edev->lock);

	if (edev->pdata->prepare)
		edev->pdata->prepare(edev);

	/* The opcode in front of the address is three bits. */
	bits = edev->addrlen + 3;

	while (count) {
		struct spi_message m;
		struct spi_transfer t[2] = { { 0 } };
		u16 cmd_addr = OP_READ << edev->addrlen;
		size_t nbytes = count;

		if (edev->pdata->flags & EE_ADDR8) {
			cmd_addr |= off;
			if (has_quirk_single_word_read(edev))
				nbytes = 1;
		} else {
			cmd_addr |= (off >> 1);
			if (has_quirk_single_word_read(edev))
				nbytes = 2;
		}

		dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
			cmd_addr, edev->spi->max_speed_hz);

		if (has_quirk_extra_read_cycle(edev)) {
			cmd_addr <<= 1;
			bits += 1;
		}

		spi_message_init(&m);

		t[0].tx_buf = (char *)&cmd_addr;
		t[0].len = 2;
		t[0].bits_per_word = bits;
		spi_message_add_tail(&t[0], &m);

		t[1].rx_buf = buf;
		t[1].len = count;
		t[1].bits_per_word = 8;
		spi_message_add_tail(&t[1], &m);

		err = spi_sync(edev->spi, &m);
		/* have to wait at least Tcsl ns */
		ndelay(250);

		if (err) {
			dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
				nbytes, (int)off, err);
			break;
		}

		buf += nbytes;
		off += nbytes;
		count -= nbytes;
	}

	if (edev->pdata->finish)
		edev->pdata->finish(edev);

	mutex_unlock(&edev->lock);

	return err;
}

static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
{
	struct spi_message m;
	struct spi_transfer t;
	int bits, ret;
	u16 cmd_addr;

	/* The opcode in front of the address is three bits. */
	bits = edev->addrlen + 3;

	cmd_addr = OP_START << edev->addrlen;
	if (edev->pdata->flags & EE_ADDR8)
		cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1;
	else
		cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS);

	if (has_quirk_instruction_length(edev)) {
		cmd_addr <<= 2;
		bits += 2;
	}

	dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
			is_on ? "en" : "ds", cmd_addr, bits);

	spi_message_init(&m);
	memset(&t, 0, sizeof(t));

	t.tx_buf = &cmd_addr;
	t.len = 2;
	t.bits_per_word = bits;
	spi_message_add_tail(&t, &m);

	mutex_lock(&edev->lock);

	if (edev->pdata->prepare)
		edev->pdata->prepare(edev);

	ret = spi_sync(edev->spi, &m);
	/* have to wait at least Tcsl ns */
	ndelay(250);
	if (ret)
		dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
			is_on ? "en" : "dis", ret);

	if (edev->pdata->finish)
		edev->pdata->finish(edev);

	mutex_unlock(&edev->lock);
	return ret;
}

static ssize_t
eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
			 const char *buf, unsigned off)
{
	struct spi_message m;
	struct spi_transfer t[2];
	int bits, data_len, ret;
	u16 cmd_addr;

	if (unlikely(off >= edev->size))
		return -EINVAL;

	/* The opcode in front of the address is three bits. */
	bits = edev->addrlen + 3;

	cmd_addr = OP_WRITE << edev->addrlen;

	if (edev->pdata->flags & EE_ADDR8) {
		cmd_addr |= off;
		data_len = 1;
	} else {
		cmd_addr |= (off >> 1);
		data_len = 2;
	}

	dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = (char *)&cmd_addr;
	t[0].len = 2;
	t[0].bits_per_word = bits;
	spi_message_add_tail(&t[0], &m);

	t[1].tx_buf = buf;
	t[1].len = data_len;
	t[1].bits_per_word = 8;
	spi_message_add_tail(&t[1], &m);

	ret = spi_sync(edev->spi, &m);
	/* have to wait program cycle time Twc ms */
	mdelay(6);
	return ret;
}

static int eeprom_93xx46_write(void *priv, unsigned int off,
				   void *val, size_t count)
{
	struct eeprom_93xx46_dev *edev = priv;
	char *buf = val;
	int i, ret, step = 1;

	if (unlikely(off >= edev->size))
		return -EFBIG;
	if ((off + count) > edev->size)
		count = edev->size - off;
	if (unlikely(!count))
		return count;

	/* only write even number of bytes on 16-bit devices */
	if (edev->pdata->flags & EE_ADDR16) {
		step = 2;
		count &= ~1;
	}

	/* erase/write enable */
	ret = eeprom_93xx46_ew(edev, 1);
	if (ret)
		return ret;

	mutex_lock(&edev->lock);

	if (edev->pdata->prepare)
		edev->pdata->prepare(edev);

	for (i = 0; i < count; i += step) {
		ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
		if (ret) {
			dev_err(&edev->spi->dev, "write failed at %d: %d\n",
				(int)off + i, ret);
			break;
		}
	}

	if (edev->pdata->finish)
		edev->pdata->finish(edev);

	mutex_unlock(&edev->lock);

	/* erase/write disable */
	eeprom_93xx46_ew(edev, 0);
	return ret;
}

static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
{
	struct eeprom_93xx46_platform_data *pd = edev->pdata;
	struct spi_message m;
	struct spi_transfer t;
	int bits, ret;
	u16 cmd_addr;

	/* The opcode in front of the address is three bits. */
	bits = edev->addrlen + 3;

	cmd_addr = OP_START << edev->addrlen;
	if (edev->pdata->flags & EE_ADDR8)
		cmd_addr |= ADDR_ERAL << 1;
	else
		cmd_addr |= ADDR_ERAL;

	if (has_quirk_instruction_length(edev)) {
		cmd_addr <<= 2;
		bits += 2;
	}

	dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);

	spi_message_init(&m);
	memset(&t, 0, sizeof(t));

	t.tx_buf = &cmd_addr;
	t.len = 2;
	t.bits_per_word = bits;
	spi_message_add_tail(&t, &m);

	mutex_lock(&edev->lock);

	if (edev->pdata->prepare)
		edev->pdata->prepare(edev);

	ret = spi_sync(edev->spi, &m);
	if (ret)
		dev_err(&edev->spi->dev, "erase error %d\n", ret);
	/* have to wait erase cycle time Tec ms */
	mdelay(6);

	if (pd->finish)
		pd->finish(edev);

	mutex_unlock(&edev->lock);
	return ret;
}

static ssize_t eeprom_93xx46_store_erase(struct device *dev,
					 struct device_attribute *attr,
					 const char *buf, size_t count)
{
	struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
	int erase = 0, ret;

	sscanf(buf, "%d", &erase);
	if (erase) {
		ret = eeprom_93xx46_ew(edev, 1);
		if (ret)
			return ret;
		ret = eeprom_93xx46_eral(edev);
		if (ret)
			return ret;
		ret = eeprom_93xx46_ew(edev, 0);
		if (ret)
			return ret;
	}
	return count;
}
static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);

static void select_assert(void *context)
{
	struct eeprom_93xx46_dev *edev = context;

	gpiod_set_value_cansleep(edev->pdata->select, 1);
}

static void select_deassert(void *context)
{
	struct eeprom_93xx46_dev *edev = context;

	gpiod_set_value_cansleep(edev->pdata->select, 0);
}

static const struct of_device_id eeprom_93xx46_of_table[] = {
	{ .compatible = "eeprom-93xx46", .data = &at93c46_data, },
	{ .compatible = "atmel,at93c46", .data = &at93c46_data, },
	{ .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
	{ .compatible = "atmel,at93c56", .data = &at93c56_data, },
	{ .compatible = "atmel,at93c66", .data = &at93c66_data, },
	{ .compatible = "microchip,93lc46b", .data = &microchip_93lc46b_data, },
	{}
};
MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);

static const struct spi_device_id eeprom_93xx46_spi_ids[] = {
	{ .name = "eeprom-93xx46",
	  .driver_data = (kernel_ulong_t)&at93c46_data, },
	{ .name = "at93c46",
	  .driver_data = (kernel_ulong_t)&at93c46_data, },
	{ .name = "at93c46d",
	  .driver_data = (kernel_ulong_t)&atmel_at93c46d_data, },
	{ .name = "at93c56",
	  .driver_data = (kernel_ulong_t)&at93c56_data, },
	{ .name = "at93c66",
	  .driver_data = (kernel_ulong_t)&at93c66_data, },
	{ .name = "93lc46b",
	  .driver_data = (kernel_ulong_t)&microchip_93lc46b_data, },
	{}
};
MODULE_DEVICE_TABLE(spi, eeprom_93xx46_spi_ids);

static int eeprom_93xx46_probe_dt(struct spi_device *spi)
{
	const struct of_device_id *of_id =
		of_match_device(eeprom_93xx46_of_table, &spi->dev);
	struct device_node *np = spi->dev.of_node;
	struct eeprom_93xx46_platform_data *pd;
	u32 tmp;
	int ret;

	pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
	if (!pd)
		return -ENOMEM;

	ret = of_property_read_u32(np, "data-size", &tmp);
	if (ret < 0) {
		dev_err(&spi->dev, "data-size property not found\n");
		return ret;
	}

	if (tmp == 8) {
		pd->flags |= EE_ADDR8;
	} else if (tmp == 16) {
		pd->flags |= EE_ADDR16;
	} else {
		dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
		return -EINVAL;
	}

	if (of_property_read_bool(np, "read-only"))
		pd->flags |= EE_READONLY;

	pd->select = devm_gpiod_get_optional(&spi->dev, "select",
					     GPIOD_OUT_LOW);
	if (IS_ERR(pd->select))
		return PTR_ERR(pd->select);

	pd->prepare = select_assert;
	pd->finish = select_deassert;
	gpiod_direction_output(pd->select, 0);

	if (of_id->data) {
		const struct eeprom_93xx46_devtype_data *data = of_id->data;

		pd->quirks = data->quirks;
		pd->flags |= data->flags;
	}

	spi->dev.platform_data = pd;

	return 0;
}

static int eeprom_93xx46_probe(struct spi_device *spi)
{
	struct eeprom_93xx46_platform_data *pd;
	struct eeprom_93xx46_dev *edev;
	int err;

	if (spi->dev.of_node) {
		err = eeprom_93xx46_probe_dt(spi);
		if (err < 0)
			return err;
	}

	pd = spi->dev.platform_data;
	if (!pd) {
		dev_err(&spi->dev, "missing platform data\n");
		return -ENODEV;
	}

	edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
	if (!edev)
		return -ENOMEM;

	if (pd->flags & EE_SIZE1K)
		edev->size = 128;
	else if (pd->flags & EE_SIZE2K)
		edev->size = 256;
	else if (pd->flags & EE_SIZE4K)
		edev->size = 512;
	else {
		dev_err(&spi->dev, "unspecified size\n");
		return -EINVAL;
	}

	if (pd->flags & EE_ADDR8)
		edev->addrlen = ilog2(edev->size);
	else if (pd->flags & EE_ADDR16)
		edev->addrlen = ilog2(edev->size) - 1;
	else {
		dev_err(&spi->dev, "unspecified address type\n");
		return -EINVAL;
	}

	mutex_init(&edev->lock);

	edev->spi = spi;
	edev->pdata = pd;

	edev->nvmem_config.type = NVMEM_TYPE_EEPROM;
	edev->nvmem_config.name = dev_name(&spi->dev);
	edev->nvmem_config.dev = &spi->dev;
	edev->nvmem_config.read_only = pd->flags & EE_READONLY;
	edev->nvmem_config.root_only = true;
	edev->nvmem_config.owner = THIS_MODULE;
	edev->nvmem_config.compat = true;
	edev->nvmem_config.base_dev = &spi->dev;
	edev->nvmem_config.reg_read = eeprom_93xx46_read;
	edev->nvmem_config.reg_write = eeprom_93xx46_write;
	edev->nvmem_config.priv = edev;
	edev->nvmem_config.stride = 4;
	edev->nvmem_config.word_size = 1;
	edev->nvmem_config.size = edev->size;

	edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
	if (IS_ERR(edev->nvmem))
		return PTR_ERR(edev->nvmem);

	dev_info(&spi->dev, "%d-bit eeprom containing %d bytes %s\n",
		(pd->flags & EE_ADDR8) ? 8 : 16,
		edev->size,
		(pd->flags & EE_READONLY) ? "(readonly)" : "");

	if (!(pd->flags & EE_READONLY)) {
		if (device_create_file(&spi->dev, &dev_attr_erase))
			dev_err(&spi->dev, "can't create erase interface\n");
	}

	spi_set_drvdata(spi, edev);
	return 0;
}

static void eeprom_93xx46_remove(struct spi_device *spi)
{
	struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);

	if (!(edev->pdata->flags & EE_READONLY))
		device_remove_file(&spi->dev, &dev_attr_erase);
}

static struct spi_driver eeprom_93xx46_driver = {
	.driver = {
		.name	= "93xx46",
		.of_match_table = of_match_ptr(eeprom_93xx46_of_table),
	},
	.probe		= eeprom_93xx46_probe,
	.remove		= eeprom_93xx46_remove,
	.id_table	= eeprom_93xx46_spi_ids,
};

module_spi_driver(eeprom_93xx46_driver);

MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs");
MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
MODULE_ALIAS("spi:93xx46");
MODULE_ALIAS("spi:eeprom-93xx46");
MODULE_ALIAS("spi:93lc46b");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
06b4501e AG	2	/*
	3	* Driver for 93xx46 EEPROMs
	4	*
	5	* (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
06b4501e AG	6	*/
	7
	8	#include <linux/delay.h>
	9	#include <linux/device.h>
3ca9b1ac	10	#include <linux/gpio/consumer.h>
06b4501e	11	#include <linux/kernel.h>
4a5ff99b	12	#include <linux/log2.h>
06b4501e AG	13	#include <linux/module.h>
06b4501e AG	14	#include <linux/mutex.h>
c074abe0 CT	15	#include <linux/of.h>
c074abe0 CT	16	#include <linux/of_device.h>
06b4501e AG	17	#include <linux/slab.h>
06b4501e AG	18	#include <linux/spi/spi.h>
1c4b6e2c	19	#include <linux/nvmem-provider.h>
06b4501e AG	20	#include <linux/eeprom_93xx46.h>
	21
	22	#define OP_START 0x4
	23	#define OP_WRITE (OP_START \| 0x1)
	24	#define OP_READ (OP_START \| 0x2)
	25	#define ADDR_EWDS 0x00
	26	#define ADDR_ERAL 0x20
	27	#define ADDR_EWEN 0x30
	28
e1379b56 CT	29	struct eeprom_93xx46_devtype_data {
e1379b56 CT	30	unsigned int quirks;
14374fbb EGP	31	unsigned char flags;
	32	};
	33
	34	static const struct eeprom_93xx46_devtype_data at93c46_data = {
	35	.flags = EE_SIZE1K,
	36	};
	37
	38	static const struct eeprom_93xx46_devtype_data at93c56_data = {
	39	.flags = EE_SIZE2K,
	40	};
	41
	42	static const struct eeprom_93xx46_devtype_data at93c66_data = {
	43	.flags = EE_SIZE4K,
e1379b56 CT	44	};
	45
	46	static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = {
14374fbb	47	.flags = EE_SIZE1K,
e1379b56 CT	48	.quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ \|
	49	EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH,
	50	};
	51
f6f1f8e6	52	static const struct eeprom_93xx46_devtype_data microchip_93lc46b_data = {
14374fbb	53	.flags = EE_SIZE1K,
f6f1f8e6 AG	54	.quirks = EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE,
	55	};
	56
06b4501e AG	57	struct eeprom_93xx46_dev {
	58	struct spi_device *spi;
	59	struct eeprom_93xx46_platform_data *pdata;
06b4501e	60	struct mutex lock;
1c4b6e2c AL	61	struct nvmem_config nvmem_config;
1c4b6e2c AL	62	struct nvmem_device *nvmem;
06b4501e	63	int addrlen;
1c4b6e2c	64	int size;
06b4501e AG	65	};
06b4501e AG	66
e1379b56 CT	67	static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
	68	{
	69	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
	70	}
	71
	72	static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
	73	{
	74	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
	75	}
	76
f6f1f8e6 AG	77	static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
	78	{
	79	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
	80	}
	81
a8ab316a SK	82	static int eeprom_93xx46_read(void *priv, unsigned int off,
a8ab316a SK	83	void *val, size_t count)
06b4501e	84	{
a8ab316a SK	85	struct eeprom_93xx46_dev *edev = priv;
	86	char *buf = val;
	87	int err = 0;
4a5ff99b	88	int bits;
06b4501e	89
1c4b6e2c AL	90	if (unlikely(off >= edev->size))
	91	return 0;
	92	if ((off + count) > edev->size)
	93	count = edev->size - off;
	94	if (unlikely(!count))
	95	return count;
06b4501e	96
e1379b56	97	mutex_lock(&edev->lock);
06b4501e	98
e1379b56 CT	99	if (edev->pdata->prepare)
e1379b56 CT	100	edev->pdata->prepare(edev);
06b4501e	101
4a5ff99b EGP	102	/* The opcode in front of the address is three bits. */
	103	bits = edev->addrlen + 3;
	104
e1379b56 CT	105	while (count) {
	106	struct spi_message m;
	107	struct spi_transfer t[2] = { { 0 } };
	108	u16 cmd_addr = OP_READ << edev->addrlen;
	109	size_t nbytes = count;
e1379b56	110
4a5ff99b EGP	111	if (edev->pdata->flags & EE_ADDR8) {
4a5ff99b EGP	112	cmd_addr \|= off;
e1379b56 CT	113	if (has_quirk_single_word_read(edev))
	114	nbytes = 1;
	115	} else {
4a5ff99b	116	cmd_addr \|= (off >> 1);
e1379b56 CT	117	if (has_quirk_single_word_read(edev))
	118	nbytes = 2;
	119	}
06b4501e	120
e1379b56 CT	121	dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
e1379b56 CT	122	cmd_addr, edev->spi->max_speed_hz);
06b4501e	123
f6f1f8e6 AG	124	if (has_quirk_extra_read_cycle(edev)) {
	125	cmd_addr <<= 1;
	126	bits += 1;
	127	}
	128
e1379b56	129	spi_message_init(&m);
06b4501e	130
e1379b56 CT	131	t[0].tx_buf = (char *)&cmd_addr;
	132	t[0].len = 2;
	133	t[0].bits_per_word = bits;
	134	spi_message_add_tail(&t[0], &m);
06b4501e	135
e1379b56 CT	136	t[1].rx_buf = buf;
	137	t[1].len = count;
	138	t[1].bits_per_word = 8;
	139	spi_message_add_tail(&t[1], &m);
06b4501e	140
e1379b56 CT	141	err = spi_sync(edev->spi, &m);
	142	/* have to wait at least Tcsl ns */
	143	ndelay(250);
06b4501e	144
e1379b56 CT	145	if (err) {
	146	dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
	147	nbytes, (int)off, err);
e1379b56 CT	148	break;
	149	}
	150
	151	buf += nbytes;
	152	off += nbytes;
	153	count -= nbytes;
06b4501e AG	154	}
	155
	156	if (edev->pdata->finish)
	157	edev->pdata->finish(edev);
	158
	159	mutex_unlock(&edev->lock);
a8ab316a SK	160
a8ab316a SK	161	return err;
06b4501e AG	162	}
	163
	164	static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
	165	{
	166	struct spi_message m;
	167	struct spi_transfer t;
	168	int bits, ret;
	169	u16 cmd_addr;
	170
4a5ff99b EGP	171	/* The opcode in front of the address is three bits. */
	172	bits = edev->addrlen + 3;
	173
06b4501e	174	cmd_addr = OP_START << edev->addrlen;
4a5ff99b	175	if (edev->pdata->flags & EE_ADDR8)
06b4501e	176	cmd_addr \|= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1;
4a5ff99b	177	else
06b4501e	178	cmd_addr \|= (is_on ? ADDR_EWEN : ADDR_EWDS);
06b4501e	179
e1379b56 CT	180	if (has_quirk_instruction_length(edev)) {
	181	cmd_addr <<= 2;
	182	bits += 2;
	183	}
	184
	185	dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
	186	is_on ? "en" : "ds", cmd_addr, bits);
06b4501e AG	187
	188	spi_message_init(&m);
	189	memset(&t, 0, sizeof(t));
	190
	191	t.tx_buf = &cmd_addr;
	192	t.len = 2;
	193	t.bits_per_word = bits;
	194	spi_message_add_tail(&t, &m);
	195
	196	mutex_lock(&edev->lock);
	197
	198	if (edev->pdata->prepare)
	199	edev->pdata->prepare(edev);
	200
	201	ret = spi_sync(edev->spi, &m);
	202	/* have to wait at least Tcsl ns */
	203	ndelay(250);
	204	if (ret)
	205	dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
	206	is_on ? "en" : "dis", ret);
	207
	208	if (edev->pdata->finish)
	209	edev->pdata->finish(edev);
	210
	211	mutex_unlock(&edev->lock);
	212	return ret;
	213	}
	214
	215	static ssize_t
	216	eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
	217	const char *buf, unsigned off)
	218	{
	219	struct spi_message m;
	220	struct spi_transfer t[2];
	221	int bits, data_len, ret;
	222	u16 cmd_addr;
	223
4a5ff99b EGP	224	if (unlikely(off >= edev->size))
	225	return -EINVAL;
	226
	227	/* The opcode in front of the address is three bits. */
	228	bits = edev->addrlen + 3;
	229
06b4501e AG	230	cmd_addr = OP_WRITE << edev->addrlen;
06b4501e AG	231
4a5ff99b EGP	232	if (edev->pdata->flags & EE_ADDR8) {
4a5ff99b EGP	233	cmd_addr \|= off;
06b4501e AG	234	data_len = 1;
06b4501e AG	235	} else {
4a5ff99b	236	cmd_addr \|= (off >> 1);
06b4501e AG	237	data_len = 2;
	238	}
	239
	240	dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
	241
	242	spi_message_init(&m);
	243	memset(t, 0, sizeof(t));
	244
	245	t[0].tx_buf = (char *)&cmd_addr;
	246	t[0].len = 2;
	247	t[0].bits_per_word = bits;
	248	spi_message_add_tail(&t[0], &m);
	249
	250	t[1].tx_buf = buf;
	251	t[1].len = data_len;
	252	t[1].bits_per_word = 8;
	253	spi_message_add_tail(&t[1], &m);
	254
	255	ret = spi_sync(edev->spi, &m);
	256	/* have to wait program cycle time Twc ms */
	257	mdelay(6);
	258	return ret;
	259	}
	260
a8ab316a SK	261	static int eeprom_93xx46_write(void *priv, unsigned int off,
a8ab316a SK	262	void *val, size_t count)
06b4501e	263	{
a8ab316a SK	264	struct eeprom_93xx46_dev *edev = priv;
a8ab316a SK	265	char *buf = val;
06b4501e AG	266	int i, ret, step = 1;
06b4501e AG	267
1c4b6e2c AL	268	if (unlikely(off >= edev->size))
	269	return -EFBIG;
	270	if ((off + count) > edev->size)
	271	count = edev->size - off;
	272	if (unlikely(!count))
	273	return count;
06b4501e	274
06b4501e	275	/* only write even number of bytes on 16-bit devices */
4a5ff99b	276	if (edev->pdata->flags & EE_ADDR16) {
06b4501e AG	277	step = 2;
	278	count &= ~1;
	279	}
	280
	281	/* erase/write enable */
	282	ret = eeprom_93xx46_ew(edev, 1);
	283	if (ret)
	284	return ret;
	285
	286	mutex_lock(&edev->lock);
	287
	288	if (edev->pdata->prepare)
	289	edev->pdata->prepare(edev);
	290
	291	for (i = 0; i < count; i += step) {
	292	ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
	293	if (ret) {
	294	dev_err(&edev->spi->dev, "write failed at %d: %d\n",
	295	(int)off + i, ret);
	296	break;
	297	}
	298	}
	299
	300	if (edev->pdata->finish)
	301	edev->pdata->finish(edev);
	302
	303	mutex_unlock(&edev->lock);
	304
	305	/* erase/write disable */
	306	eeprom_93xx46_ew(edev, 0);
a8ab316a	307	return ret;
1c4b6e2c AL	308	}
1c4b6e2c AL	309
06b4501e AG	310	static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
	311	{
	312	struct eeprom_93xx46_platform_data *pd = edev->pdata;
	313	struct spi_message m;
	314	struct spi_transfer t;
	315	int bits, ret;
	316	u16 cmd_addr;
	317
4a5ff99b EGP	318	/* The opcode in front of the address is three bits. */
	319	bits = edev->addrlen + 3;
	320
06b4501e	321	cmd_addr = OP_START << edev->addrlen;
4a5ff99b	322	if (edev->pdata->flags & EE_ADDR8)
06b4501e	323	cmd_addr \|= ADDR_ERAL << 1;
4a5ff99b	324	else
06b4501e	325	cmd_addr \|= ADDR_ERAL;
06b4501e	326
e1379b56 CT	327	if (has_quirk_instruction_length(edev)) {
	328	cmd_addr <<= 2;
	329	bits += 2;
	330	}
	331
	332	dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
	333
06b4501e AG	334	spi_message_init(&m);
	335	memset(&t, 0, sizeof(t));
	336
	337	t.tx_buf = &cmd_addr;
	338	t.len = 2;
	339	t.bits_per_word = bits;
	340	spi_message_add_tail(&t, &m);
	341
	342	mutex_lock(&edev->lock);
	343
	344	if (edev->pdata->prepare)
	345	edev->pdata->prepare(edev);
	346
	347	ret = spi_sync(edev->spi, &m);
	348	if (ret)
	349	dev_err(&edev->spi->dev, "erase error %d\n", ret);
	350	/* have to wait erase cycle time Tec ms */
	351	mdelay(6);
	352
	353	if (pd->finish)
	354	pd->finish(edev);
	355
	356	mutex_unlock(&edev->lock);
	357	return ret;
	358	}
	359
	360	static ssize_t eeprom_93xx46_store_erase(struct device *dev,
	361	struct device_attribute *attr,
	362	const char *buf, size_t count)
	363	{
	364	struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
	365	int erase = 0, ret;
	366
	367	sscanf(buf, "%d", &erase);
	368	if (erase) {
	369	ret = eeprom_93xx46_ew(edev, 1);
	370	if (ret)
	371	return ret;
	372	ret = eeprom_93xx46_eral(edev);
	373	if (ret)
	374	return ret;
	375	ret = eeprom_93xx46_ew(edev, 0);
	376	if (ret)
	377	return ret;
	378	}
	379	return count;
	380	}
	381	static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase);
	382
3ca9b1ac CT	383	static void select_assert(void *context)
	384	{
	385	struct eeprom_93xx46_dev *edev = context;
	386
	387	gpiod_set_value_cansleep(edev->pdata->select, 1);
	388	}
	389
	390	static void select_deassert(void *context)
	391	{
	392	struct eeprom_93xx46_dev *edev = context;
	393
	394	gpiod_set_value_cansleep(edev->pdata->select, 0);
	395	}
	396
c074abe0	397	static const struct of_device_id eeprom_93xx46_of_table[] = {
14374fbb EGP	398	{ .compatible = "eeprom-93xx46", .data = &at93c46_data, },
14374fbb EGP	399	{ .compatible = "atmel,at93c46", .data = &at93c46_data, },
e1379b56	400	{ .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, },
14374fbb EGP	401	{ .compatible = "atmel,at93c56", .data = &at93c56_data, },
14374fbb EGP	402	{ .compatible = "atmel,at93c66", .data = &at93c66_data, },
f6f1f8e6	403	{ .compatible = "microchip,93lc46b", .data = &microchip_93lc46b_data, },
c074abe0 CT	404	{}
	405	};
	406	MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table);
	407
137879f7 MB	408	static const struct spi_device_id eeprom_93xx46_spi_ids[] = {
	409	{ .name = "eeprom-93xx46",
	410	.driver_data = (kernel_ulong_t)&at93c46_data, },
	411	{ .name = "at93c46",
	412	.driver_data = (kernel_ulong_t)&at93c46_data, },
	413	{ .name = "at93c46d",
	414	.driver_data = (kernel_ulong_t)&atmel_at93c46d_data, },
	415	{ .name = "at93c56",
	416	.driver_data = (kernel_ulong_t)&at93c56_data, },
	417	{ .name = "at93c66",
	418	.driver_data = (kernel_ulong_t)&at93c66_data, },
	419	{ .name = "93lc46b",
	420	.driver_data = (kernel_ulong_t)&microchip_93lc46b_data, },
	421	{}
	422	};
f4275272	423	MODULE_DEVICE_TABLE(spi, eeprom_93xx46_spi_ids);
137879f7	424
c074abe0 CT	425	static int eeprom_93xx46_probe_dt(struct spi_device *spi)
c074abe0 CT	426	{
e1379b56 CT	427	const struct of_device_id *of_id =
e1379b56 CT	428	of_match_device(eeprom_93xx46_of_table, &spi->dev);
c074abe0 CT	429	struct device_node *np = spi->dev.of_node;
	430	struct eeprom_93xx46_platform_data *pd;
	431	u32 tmp;
	432	int ret;
	433
	434	pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL);
	435	if (!pd)
	436	return -ENOMEM;
	437
	438	ret = of_property_read_u32(np, "data-size", &tmp);
	439	if (ret < 0) {
	440	dev_err(&spi->dev, "data-size property not found\n");
	441	return ret;
	442	}
	443
	444	if (tmp == 8) {
	445	pd->flags \|= EE_ADDR8;
	446	} else if (tmp == 16) {
	447	pd->flags \|= EE_ADDR16;
	448	} else {
	449	dev_err(&spi->dev, "invalid data-size (%d)\n", tmp);
	450	return -EINVAL;
	451	}
	452
	453	if (of_property_read_bool(np, "read-only"))
	454	pd->flags \|= EE_READONLY;
	455
54ec6023 FE	456	pd->select = devm_gpiod_get_optional(&spi->dev, "select",
	457	GPIOD_OUT_LOW);
	458	if (IS_ERR(pd->select))
	459	return PTR_ERR(pd->select);
3ca9b1ac	460
54ec6023 FE	461	pd->prepare = select_assert;
	462	pd->finish = select_deassert;
	463	gpiod_direction_output(pd->select, 0);
3ca9b1ac	464
e1379b56 CT	465	if (of_id->data) {
	466	const struct eeprom_93xx46_devtype_data *data = of_id->data;
	467
	468	pd->quirks = data->quirks;
14374fbb	469	pd->flags \|= data->flags;
e1379b56 CT	470	}
e1379b56 CT	471
c074abe0 CT	472	spi->dev.platform_data = pd;
	473
	474	return 0;
	475	}
	476
80c8ae28	477	static int eeprom_93xx46_probe(struct spi_device *spi)
06b4501e AG	478	{
	479	struct eeprom_93xx46_platform_data *pd;
	480	struct eeprom_93xx46_dev *edev;
	481	int err;
	482
c074abe0 CT	483	if (spi->dev.of_node) {
	484	err = eeprom_93xx46_probe_dt(spi);
	485	if (err < 0)
	486	return err;
	487	}
	488
06b4501e AG	489	pd = spi->dev.platform_data;
	490	if (!pd) {
	491	dev_err(&spi->dev, "missing platform data\n");
	492	return -ENODEV;
	493	}
	494
c853d690	495	edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
06b4501e AG	496	if (!edev)
	497	return -ENOMEM;
	498
14374fbb EGP	499	if (pd->flags & EE_SIZE1K)
	500	edev->size = 128;
	501	else if (pd->flags & EE_SIZE2K)
	502	edev->size = 256;
	503	else if (pd->flags & EE_SIZE4K)
	504	edev->size = 512;
	505	else {
	506	dev_err(&spi->dev, "unspecified size\n");
	507	return -EINVAL;
	508	}
4a5ff99b	509
06b4501e	510	if (pd->flags & EE_ADDR8)
4a5ff99b	511	edev->addrlen = ilog2(edev->size);
06b4501e	512	else if (pd->flags & EE_ADDR16)
4a5ff99b	513	edev->addrlen = ilog2(edev->size) - 1;
06b4501e AG	514	else {
06b4501e AG	515	dev_err(&spi->dev, "unspecified address type\n");
c853d690	516	return -EINVAL;
06b4501e AG	517	}
	518
	519	mutex_init(&edev->lock);
	520
dd69a18a	521	edev->spi = spi;
06b4501e AG	522	edev->pdata = pd;
06b4501e AG	523
1d62a2ce	524	edev->nvmem_config.type = NVMEM_TYPE_EEPROM;
1c4b6e2c AL	525	edev->nvmem_config.name = dev_name(&spi->dev);
	526	edev->nvmem_config.dev = &spi->dev;
	527	edev->nvmem_config.read_only = pd->flags & EE_READONLY;
	528	edev->nvmem_config.root_only = true;
	529	edev->nvmem_config.owner = THIS_MODULE;
	530	edev->nvmem_config.compat = true;
	531	edev->nvmem_config.base_dev = &spi->dev;
a8ab316a SK	532	edev->nvmem_config.reg_read = eeprom_93xx46_read;
	533	edev->nvmem_config.reg_write = eeprom_93xx46_write;
	534	edev->nvmem_config.priv = edev;
	535	edev->nvmem_config.stride = 4;
	536	edev->nvmem_config.word_size = 1;
	537	edev->nvmem_config.size = edev->size;
1c4b6e2c	538
c853d690 BG	539	edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
	540	if (IS_ERR(edev->nvmem))
	541	return PTR_ERR(edev->nvmem);
06b4501e	542
14374fbb	543	dev_info(&spi->dev, "%d-bit eeprom containing %d bytes %s\n",
06b4501e	544	(pd->flags & EE_ADDR8) ? 8 : 16,
14374fbb	545	edev->size,
06b4501e AG	546	(pd->flags & EE_READONLY) ? "(readonly)" : "");
	547
	548	if (!(pd->flags & EE_READONLY)) {
	549	if (device_create_file(&spi->dev, &dev_attr_erase))
	550	dev_err(&spi->dev, "can't create erase interface\n");
	551	}
	552
5ba75b55	553	spi_set_drvdata(spi, edev);
06b4501e	554	return 0;
06b4501e AG	555	}
06b4501e AG	556
a0386bba	557	static void eeprom_93xx46_remove(struct spi_device *spi)
06b4501e	558	{
5ba75b55	559	struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
06b4501e AG	560
	561	if (!(edev->pdata->flags & EE_READONLY))
	562	device_remove_file(&spi->dev, &dev_attr_erase);
06b4501e AG	563	}
	564
	565	static struct spi_driver eeprom_93xx46_driver = {
	566	.driver = {
	567	.name = "93xx46",
c074abe0	568	.of_match_table = of_match_ptr(eeprom_93xx46_of_table),
06b4501e AG	569	},
06b4501e AG	570	.probe = eeprom_93xx46_probe,
2d6bed9c	571	.remove = eeprom_93xx46_remove,
137879f7	572	.id_table = eeprom_93xx46_spi_ids,
06b4501e AG	573	};
06b4501e AG	574
a3dc3c9e	575	module_spi_driver(eeprom_93xx46_driver);
06b4501e AG	576
	577	MODULE_LICENSE("GPL");
	578	MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs");
	579	MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
4540b9fb	580	MODULE_ALIAS("spi:93xx46");
13613a22	581	MODULE_ALIAS("spi:eeprom-93xx46");
47771f17	582	MODULE_ALIAS("spi:93lc46b");