[linux-2.6-block.git] / drivers / misc / eeprom / at25.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Driver for most of the SPI EEPROMs, such as Atmel AT25 models
 * and Cypress FRAMs FM25 models.
 *
 * Copyright (C) 2006 David Brownell
 */

#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/sched.h>
#include <linux/slab.h>

#include <linux/spi/eeprom.h>
#include <linux/spi/spi.h>

#include <linux/nvmem-provider.h>

/*
 * NOTE: this is an *EEPROM* driver. The vagaries of product naming
 * mean that some AT25 products are EEPROMs, and others are FLASH.
 * Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
 * not this one!
 *
 * EEPROMs that can be used with this driver include, for example:
 *   AT25M02, AT25128B
 */

#define	FM25_SN_LEN	8		/* serial number length */
#define EE_MAXADDRLEN	3		/* 24 bit addresses, up to 2 MBytes */

struct at25_data {
	struct spi_eeprom	chip;
	struct spi_device	*spi;
	struct mutex		lock;
	unsigned		addrlen;
	struct nvmem_config	nvmem_config;
	struct nvmem_device	*nvmem;
	u8 sernum[FM25_SN_LEN];
	u8 command[EE_MAXADDRLEN + 1];
};

#define	AT25_WREN	0x06		/* latch the write enable */
#define	AT25_WRDI	0x04		/* reset the write enable */
#define	AT25_RDSR	0x05		/* read status register */
#define	AT25_WRSR	0x01		/* write status register */
#define	AT25_READ	0x03		/* read byte(s) */
#define	AT25_WRITE	0x02		/* write byte(s)/sector */
#define	FM25_SLEEP	0xb9		/* enter sleep mode */
#define	FM25_RDID	0x9f		/* read device ID */
#define	FM25_RDSN	0xc3		/* read S/N */

#define	AT25_SR_nRDY	0x01		/* nRDY = write-in-progress */
#define	AT25_SR_WEN	0x02		/* write enable (latched) */
#define	AT25_SR_BP0	0x04		/* BP for software writeprotect */
#define	AT25_SR_BP1	0x08
#define	AT25_SR_WPEN	0x80		/* writeprotect enable */

#define	AT25_INSTR_BIT3	0x08		/* additional address bit in instr */

#define	FM25_ID_LEN	9		/* ID length */

/*
 * Specs often allow 5ms for a page write, sometimes 20ms;
 * it's important to recover from write timeouts.
 */
#define	EE_TIMEOUT	25

/*-------------------------------------------------------------------------*/

#define	io_limit	PAGE_SIZE	/* bytes */

static int at25_ee_read(void *priv, unsigned int offset,
			void *val, size_t count)
{
	struct at25_data *at25 = priv;
	char *buf = val;
	size_t max_chunk = spi_max_transfer_size(at25->spi);
	size_t num_msgs = DIV_ROUND_UP(count, max_chunk);
	size_t nr_bytes = 0;
	unsigned int msg_offset;
	size_t msg_count;
	u8			*cp;
	ssize_t			status;
	struct spi_transfer	t[2];
	struct spi_message	m;
	u8			instr;

	if (unlikely(offset >= at25->chip.byte_len))
		return -EINVAL;
	if ((offset + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - offset;
	if (unlikely(!count))
		return -EINVAL;

	msg_offset = (unsigned int)offset;
	msg_count = min(count, max_chunk);
	while (num_msgs) {
		cp = at25->command;

		instr = AT25_READ;
		if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
			if (msg_offset >= BIT(at25->addrlen * 8))
				instr |= AT25_INSTR_BIT3;

		mutex_lock(&at25->lock);

		*cp++ = instr;

		/* 8/16/24-bit address is written MSB first */
		switch (at25->addrlen) {
		default:	/* case 3 */
			*cp++ = msg_offset >> 16;
			fallthrough;
		case 2:
			*cp++ = msg_offset >> 8;
			fallthrough;
		case 1:
		case 0:	/* can't happen: for better code generation */
			*cp++ = msg_offset >> 0;
		}

		spi_message_init(&m);
		memset(t, 0, sizeof(t));

		t[0].tx_buf = at25->command;
		t[0].len = at25->addrlen + 1;
		spi_message_add_tail(&t[0], &m);

		t[1].rx_buf = buf + nr_bytes;
		t[1].len = msg_count;
		spi_message_add_tail(&t[1], &m);

		status = spi_sync(at25->spi, &m);

		mutex_unlock(&at25->lock);

		if (status)
			return status;

		--num_msgs;
		msg_offset += msg_count;
		nr_bytes += msg_count;
	}

	dev_dbg(&at25->spi->dev, "read %zu bytes at %d\n",
		count, offset);
	return 0;
}

/* Read extra registers as ID or serial number */
static int fm25_aux_read(struct at25_data *at25, u8 *buf, uint8_t command,
			 int len)
{
	int status;
	struct spi_transfer t[2];
	struct spi_message m;

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = at25->command;
	t[0].len = 1;
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = len;
	spi_message_add_tail(&t[1], &m);

	mutex_lock(&at25->lock);

	at25->command[0] = command;

	status = spi_sync(at25->spi, &m);
	dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);

	mutex_unlock(&at25->lock);
	return status;
}

static ssize_t sernum_show(struct device *dev, struct device_attribute *attr, char *buf)
{
	struct at25_data *at25;

	at25 = dev_get_drvdata(dev);
	return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum);
}
static DEVICE_ATTR_RO(sernum);

static struct attribute *sernum_attrs[] = {
	&dev_attr_sernum.attr,
	NULL,
};
ATTRIBUTE_GROUPS(sernum);

static int at25_ee_write(void *priv, unsigned int off, void *val, size_t count)
{
	struct at25_data *at25 = priv;
	size_t maxsz = spi_max_transfer_size(at25->spi);
	const char *buf = val;
	int			status = 0;
	unsigned		buf_size;
	u8			*bounce;

	if (unlikely(off >= at25->chip.byte_len))
		return -EFBIG;
	if ((off + count) > at25->chip.byte_len)
		count = at25->chip.byte_len - off;
	if (unlikely(!count))
		return -EINVAL;

	/* Temp buffer starts with command and address */
	buf_size = at25->chip.page_size;
	if (buf_size > io_limit)
		buf_size = io_limit;
	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	if (!bounce)
		return -ENOMEM;

	/*
	 * For write, rollover is within the page ... so we write at
	 * most one page, then manually roll over to the next page.
	 */
	mutex_lock(&at25->lock);
	do {
		unsigned long	timeout, retries;
		unsigned	segment;
		unsigned	offset = (unsigned) off;
		u8		*cp = bounce;
		int		sr;
		u8		instr;

		*cp = AT25_WREN;
		status = spi_write(at25->spi, cp, 1);
		if (status < 0) {
			dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
			break;
		}

		instr = AT25_WRITE;
		if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
			if (offset >= BIT(at25->addrlen * 8))
				instr |= AT25_INSTR_BIT3;
		*cp++ = instr;

		/* 8/16/24-bit address is written MSB first */
		switch (at25->addrlen) {
		default:	/* case 3 */
			*cp++ = offset >> 16;
			fallthrough;
		case 2:
			*cp++ = offset >> 8;
			fallthrough;
		case 1:
		case 0:	/* can't happen: for better code generation */
			*cp++ = offset >> 0;
		}

		/* Write as much of a page as we can */
		segment = buf_size - (offset % buf_size);
		if (segment > count)
			segment = count;
		if (segment > maxsz)
			segment = maxsz;
		memcpy(cp, buf, segment);
		status = spi_write(at25->spi, bounce,
				segment + at25->addrlen + 1);
		dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
			segment, offset, status);
		if (status < 0)
			break;

		/*
		 * REVISIT this should detect (or prevent) failed writes
		 * to read-only sections of the EEPROM...
		 */

		/* Wait for non-busy status */
		timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
		retries = 0;
		do {

			sr = spi_w8r8(at25->spi, AT25_RDSR);
			if (sr < 0 || (sr & AT25_SR_nRDY)) {
				dev_dbg(&at25->spi->dev,
					"rdsr --> %d (%02x)\n", sr, sr);
				/* at HZ=100, this is sloooow */
				msleep(1);
				continue;
			}
			if (!(sr & AT25_SR_nRDY))
				break;
		} while (retries++ < 3 || time_before_eq(jiffies, timeout));

		if ((sr < 0) || (sr & AT25_SR_nRDY)) {
			dev_err(&at25->spi->dev,
				"write %u bytes offset %u, timeout after %u msecs\n",
				segment, offset,
				jiffies_to_msecs(jiffies -
					(timeout - EE_TIMEOUT)));
			status = -ETIMEDOUT;
			break;
		}

		off += segment;
		buf += segment;
		count -= segment;

	} while (count > 0);

	mutex_unlock(&at25->lock);

	kfree(bounce);
	return status;
}

/*-------------------------------------------------------------------------*/

static int at25_fw_to_chip(struct device *dev, struct spi_eeprom *chip)
{
	u32 val;
	int err;

	strscpy(chip->name, "at25", sizeof(chip->name));

	err = device_property_read_u32(dev, "size", &val);
	if (err)
		err = device_property_read_u32(dev, "at25,byte-len", &val);
	if (err) {
		dev_err(dev, "Error: missing \"size\" property\n");
		return err;
	}
	chip->byte_len = val;

	err = device_property_read_u32(dev, "pagesize", &val);
	if (err)
		err = device_property_read_u32(dev, "at25,page-size", &val);
	if (err) {
		dev_err(dev, "Error: missing \"pagesize\" property\n");
		return err;
	}
	chip->page_size = val;

	err = device_property_read_u32(dev, "address-width", &val);
	if (err) {
		err = device_property_read_u32(dev, "at25,addr-mode", &val);
		if (err) {
			dev_err(dev, "Error: missing \"address-width\" property\n");
			return err;
		}
		chip->flags = (u16)val;
	} else {
		switch (val) {
		case 9:
			chip->flags |= EE_INSTR_BIT3_IS_ADDR;
			fallthrough;
		case 8:
			chip->flags |= EE_ADDR1;
			break;
		case 16:
			chip->flags |= EE_ADDR2;
			break;
		case 24:
			chip->flags |= EE_ADDR3;
			break;
		default:
			dev_err(dev,
				"Error: bad \"address-width\" property: %u\n",
				val);
			return -ENODEV;
		}
		if (device_property_present(dev, "read-only"))
			chip->flags |= EE_READONLY;
	}
	return 0;
}

static int at25_fram_to_chip(struct device *dev, struct spi_eeprom *chip)
{
	struct at25_data *at25 = container_of(chip, struct at25_data, chip);
	u8 sernum[FM25_SN_LEN];
	u8 id[FM25_ID_LEN];
	int i;

	strscpy(chip->name, "fm25", sizeof(chip->name));

	/* Get ID of chip */
	fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN);
	if (id[6] != 0xc2) {
		dev_err(dev, "Error: no Cypress FRAM (id %02x)\n", id[6]);
		return -ENODEV;
	}
	/* Set size found in ID */
	if (id[7] < 0x21 || id[7] > 0x26) {
		dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]);
		return -ENODEV;
	}

	chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024;
	if (chip->byte_len > 64 * 1024)
		chip->flags |= EE_ADDR3;
	else
		chip->flags |= EE_ADDR2;

	if (id[8]) {
		fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN);
		/* Swap byte order */
		for (i = 0; i < FM25_SN_LEN; i++)
			at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i];
	}

	chip->page_size = PAGE_SIZE;
	return 0;
}

static const struct of_device_id at25_of_match[] = {
	{ .compatible = "atmel,at25" },
	{ .compatible = "cypress,fm25" },
	{ }
};
MODULE_DEVICE_TABLE(of, at25_of_match);

static const struct spi_device_id at25_spi_ids[] = {
	{ .name = "at25" },
	{ .name = "fm25" },
	{ }
};
MODULE_DEVICE_TABLE(spi, at25_spi_ids);

static int at25_probe(struct spi_device *spi)
{
	struct at25_data	*at25 = NULL;
	int			err;
	int			sr;
	struct spi_eeprom *pdata;
	bool is_fram;

	err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25");
	if (err >= 0)
		is_fram = true;
	else
		is_fram = false;

	/*
	 * Ping the chip ... the status register is pretty portable,
	 * unlike probing manufacturer IDs. We do expect that system
	 * firmware didn't write it in the past few milliseconds!
	 */
	sr = spi_w8r8(spi, AT25_RDSR);
	if (sr < 0 || sr & AT25_SR_nRDY) {
		dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
		return -ENXIO;
	}

	at25 = devm_kzalloc(&spi->dev, sizeof(*at25), GFP_KERNEL);
	if (!at25)
		return -ENOMEM;

	mutex_init(&at25->lock);
	at25->spi = spi;
	spi_set_drvdata(spi, at25);

	/* Chip description */
	pdata = dev_get_platdata(&spi->dev);
	if (pdata) {
		at25->chip = *pdata;
	} else {
		if (is_fram)
			err = at25_fram_to_chip(&spi->dev, &at25->chip);
		else
			err = at25_fw_to_chip(&spi->dev, &at25->chip);
		if (err)
			return err;
	}

	/* For now we only support 8/16/24 bit addressing */
	if (at25->chip.flags & EE_ADDR1)
		at25->addrlen = 1;
	else if (at25->chip.flags & EE_ADDR2)
		at25->addrlen = 2;
	else if (at25->chip.flags & EE_ADDR3)
		at25->addrlen = 3;
	else {
		dev_dbg(&spi->dev, "unsupported address type\n");
		return -EINVAL;
	}

	at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM;
	at25->nvmem_config.name = dev_name(&spi->dev);
	at25->nvmem_config.dev = &spi->dev;
	at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY;
	at25->nvmem_config.root_only = true;
	at25->nvmem_config.owner = THIS_MODULE;
	at25->nvmem_config.compat = true;
	at25->nvmem_config.base_dev = &spi->dev;
	at25->nvmem_config.reg_read = at25_ee_read;
	at25->nvmem_config.reg_write = at25_ee_write;
	at25->nvmem_config.priv = at25;
	at25->nvmem_config.stride = 1;
	at25->nvmem_config.word_size = 1;
	at25->nvmem_config.size = at25->chip.byte_len;

	at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
	if (IS_ERR(at25->nvmem))
		return PTR_ERR(at25->nvmem);

	dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n",
		 (at25->chip.byte_len < 1024) ?
			at25->chip.byte_len : (at25->chip.byte_len / 1024),
		 (at25->chip.byte_len < 1024) ? "Byte" : "KByte",
		 at25->chip.name, is_fram ? "fram" : "eeprom",
		 (at25->chip.flags & EE_READONLY) ? " (readonly)" : "",
		 at25->chip.page_size);
	return 0;
}

/*-------------------------------------------------------------------------*/

static struct spi_driver at25_driver = {
	.driver = {
		.name		= "at25",
		.of_match_table = at25_of_match,
		.dev_groups	= sernum_groups,
	},
	.probe		= at25_probe,
	.id_table	= at25_spi_ids,
};

module_spi_driver(at25_driver);

MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
MODULE_AUTHOR("David Brownell");
MODULE_LICENSE("GPL");
MODULE_ALIAS("spi:at25");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
b587b13a	2	/*
1ca54ce9 AS	3	* Driver for most of the SPI EEPROMs, such as Atmel AT25 models
1ca54ce9 AS	4	* and Cypress FRAMs FM25 models.
b587b13a DB	5	*
b587b13a DB	6	* Copyright (C) 2006 David Brownell
b587b13a DB	7	*/
b587b13a DB	8
d059ed1b	9	#include <linux/bits.h>
b587b13a DB	10	#include <linux/delay.h>
b587b13a DB	11	#include <linux/device.h>
d5fb1304 AS	12	#include <linux/kernel.h>
	13	#include <linux/module.h>
	14	#include <linux/property.h>
b587b13a	15	#include <linux/sched.h>
d5fb1304	16	#include <linux/slab.h>
b587b13a	17
b587b13a	18	#include <linux/spi/eeprom.h>
d5fb1304 AS	19	#include <linux/spi/spi.h>
	20
	21	#include <linux/nvmem-provider.h>
b587b13a	22
3f86f14c	23	/*
1ca54ce9	24	* NOTE: this is an EEPROM driver. The vagaries of product naming
3f86f14c DB	25	* mean that some AT25 products are EEPROMs, and others are FLASH.
	26	* Handle FLASH chips with the drivers/mtd/devices/m25p80.c driver,
	27	* not this one!
667aef00 JN	28	*
	29	* EEPROMs that can be used with this driver include, for example:
	30	* AT25M02, AT25128B
3f86f14c DB	31	*/
3f86f14c DB	32
fd307a4a	33	#define FM25_SN_LEN 8 /* serial number length */
5b47b751 CL	34	#define EE_MAXADDRLEN 3 /* 24 bit addresses, up to 2 MBytes */
5b47b751 CL	35
b587b13a	36	struct at25_data {
31a45d27	37	struct spi_eeprom chip;
b587b13a DB	38	struct spi_device *spi;
b587b13a DB	39	struct mutex lock;
b587b13a	40	unsigned addrlen;
5a99f570 AL	41	struct nvmem_config nvmem_config;
5a99f570 AL	42	struct nvmem_device *nvmem;
fd307a4a	43	u8 sernum[FM25_SN_LEN];
5b47b751	44	u8 command[EE_MAXADDRLEN + 1];
b587b13a DB	45	};
	46
	47	#define AT25_WREN 0x06 /* latch the write enable */
	48	#define AT25_WRDI 0x04 /* reset the write enable */
	49	#define AT25_RDSR 0x05 /* read status register */
	50	#define AT25_WRSR 0x01 /* write status register */
	51	#define AT25_READ 0x03 /* read byte(s) */
	52	#define AT25_WRITE 0x02 /* write byte(s)/sector */
fd307a4a JP	53	#define FM25_SLEEP 0xb9 /* enter sleep mode */
	54	#define FM25_RDID 0x9f /* read device ID */
	55	#define FM25_RDSN 0xc3 /* read S/N */
b587b13a DB	56
	57	#define AT25_SR_nRDY 0x01 /* nRDY = write-in-progress */
	58	#define AT25_SR_WEN 0x02 /* write enable (latched) */
	59	#define AT25_SR_BP0 0x04 /* BP for software writeprotect */
	60	#define AT25_SR_BP1 0x08
	61	#define AT25_SR_WPEN 0x80 /* writeprotect enable */
	62
1ca54ce9	63	#define AT25_INSTR_BIT3 0x08 /* additional address bit in instr */
b587b13a	64
fd307a4a JP	65	#define FM25_ID_LEN 9 /* ID length */
fd307a4a JP	66
1ca54ce9 AS	67	/*
1ca54ce9 AS	68	* Specs often allow 5ms for a page write, sometimes 20ms;
b587b13a DB	69	* it's important to recover from write timeouts.
	70	*/
	71	#define EE_TIMEOUT 25
	72
	73	/-------------------------------------------------------------------------/
	74
	75	#define io_limit PAGE_SIZE /* bytes */
	76
01973a01 SK	77	static int at25_ee_read(void *priv, unsigned int offset,
01973a01 SK	78	void *val, size_t count)
b587b13a	79	{
01973a01 SK	80	struct at25_data *at25 = priv;
01973a01 SK	81	char *buf = val;
0a35780c BB	82	size_t max_chunk = spi_max_transfer_size(at25->spi);
	83	size_t num_msgs = DIV_ROUND_UP(count, max_chunk);
	84	size_t nr_bytes = 0;
	85	unsigned int msg_offset;
	86	size_t msg_count;
b587b13a DB	87	u8 *cp;
	88	ssize_t status;
	89	struct spi_transfer t[2];
	90	struct spi_message m;
b4161f0b	91	u8 instr;
b587b13a	92
5a99f570	93	if (unlikely(offset >= at25->chip.byte_len))
01973a01	94	return -EINVAL;
5a99f570 AL	95	if ((offset + count) > at25->chip.byte_len)
5a99f570 AL	96	count = at25->chip.byte_len - offset;
14dd1ff0	97	if (unlikely(!count))
01973a01	98	return -EINVAL;
14dd1ff0	99
0a35780c BB	100	msg_offset = (unsigned int)offset;
	101	msg_count = min(count, max_chunk);
	102	while (num_msgs) {
	103	cp = at25->command;
b4161f0b	104
0a35780c BB	105	instr = AT25_READ;
	106	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
	107	if (msg_offset >= BIT(at25->addrlen * 8))
	108	instr \|= AT25_INSTR_BIT3;
5b47b751	109
0a35780c	110	mutex_lock(&at25->lock);
5b47b751	111
0a35780c	112	*cp++ = instr;
b587b13a	113
0a35780c BB	114	/* 8/16/24-bit address is written MSB first */
	115	switch (at25->addrlen) {
	116	default: /* case 3 */
	117	*cp++ = msg_offset >> 16;
	118	fallthrough;
	119	case 2:
	120	*cp++ = msg_offset >> 8;
	121	fallthrough;
	122	case 1:
	123	case 0: /* can't happen: for better code generation */
	124	*cp++ = msg_offset >> 0;
	125	}
b587b13a	126
0a35780c BB	127	spi_message_init(&m);
0a35780c BB	128	memset(t, 0, sizeof(t));
b587b13a	129
0a35780c BB	130	t[0].tx_buf = at25->command;
	131	t[0].len = at25->addrlen + 1;
	132	spi_message_add_tail(&t[0], &m);
b587b13a	133
0a35780c BB	134	t[1].rx_buf = buf + nr_bytes;
	135	t[1].len = msg_count;
	136	spi_message_add_tail(&t[1], &m);
b587b13a	137
0a35780c BB	138	status = spi_sync(at25->spi, &m);
	139
	140	mutex_unlock(&at25->lock);
	141
	142	if (status)
	143	return status;
	144
	145	--num_msgs;
	146	msg_offset += msg_count;
	147	nr_bytes += msg_count;
	148	}
	149
	150	dev_dbg(&at25->spi->dev, "read %zu bytes at %d\n",
	151	count, offset);
	152	return 0;
b587b13a DB	153	}
b587b13a DB	154
1ca54ce9	155	/* Read extra registers as ID or serial number */
fd307a4a JP	156	static int fm25_aux_read(struct at25_data at25, u8 buf, uint8_t command,
	157	int len)
	158	{
	159	int status;
	160	struct spi_transfer t[2];
	161	struct spi_message m;
	162
	163	spi_message_init(&m);
	164	memset(t, 0, sizeof(t));
	165
5b47b751	166	t[0].tx_buf = at25->command;
fd307a4a JP	167	t[0].len = 1;
	168	spi_message_add_tail(&t[0], &m);
	169
	170	t[1].rx_buf = buf;
	171	t[1].len = len;
	172	spi_message_add_tail(&t[1], &m);
	173
	174	mutex_lock(&at25->lock);
	175
5b47b751 CL	176	at25->command[0] = command;
5b47b751 CL	177
fd307a4a JP	178	status = spi_sync(at25->spi, &m);
	179	dev_dbg(&at25->spi->dev, "read %d aux bytes --> %d\n", len, status);
	180
	181	mutex_unlock(&at25->lock);
	182	return status;
	183	}
	184
	185	static ssize_t sernum_show(struct device dev, struct device_attribute attr, char *buf)
	186	{
	187	struct at25_data *at25;
	188
	189	at25 = dev_get_drvdata(dev);
604288bc	190	return sysfs_emit(buf, "%*ph\n", (int)sizeof(at25->sernum), at25->sernum);
fd307a4a JP	191	}
	192	static DEVICE_ATTR_RO(sernum);
	193
	194	static struct attribute *sernum_attrs[] = {
	195	&dev_attr_sernum.attr,
	196	NULL,
	197	};
	198	ATTRIBUTE_GROUPS(sernum);
	199
01973a01	200	static int at25_ee_write(void priv, unsigned int off, void val, size_t count)
b587b13a	201	{
01973a01	202	struct at25_data *at25 = priv;
0a35780c	203	size_t maxsz = spi_max_transfer_size(at25->spi);
01973a01 SK	204	const char *buf = val;
01973a01 SK	205	int status = 0;
b587b13a DB	206	unsigned buf_size;
	207	u8 *bounce;
	208
5a99f570	209	if (unlikely(off >= at25->chip.byte_len))
14dd1ff0	210	return -EFBIG;
5a99f570 AL	211	if ((off + count) > at25->chip.byte_len)
5a99f570 AL	212	count = at25->chip.byte_len - off;
14dd1ff0	213	if (unlikely(!count))
01973a01	214	return -EINVAL;
14dd1ff0	215
b587b13a DB	216	/* Temp buffer starts with command and address */
	217	buf_size = at25->chip.page_size;
	218	if (buf_size > io_limit)
	219	buf_size = io_limit;
	220	bounce = kmalloc(buf_size + at25->addrlen + 1, GFP_KERNEL);
	221	if (!bounce)
	222	return -ENOMEM;
	223
1ca54ce9 AS	224	/*
1ca54ce9 AS	225	* For write, rollover is within the page ... so we write at
b587b13a DB	226	* most one page, then manually roll over to the next page.
b587b13a DB	227	*/
b587b13a DB	228	mutex_lock(&at25->lock);
	229	do {
	230	unsigned long timeout, retries;
	231	unsigned segment;
	232	unsigned offset = (unsigned) off;
b4161f0b	233	u8 *cp = bounce;
f0d83679	234	int sr;
b4161f0b	235	u8 instr;
b587b13a DB	236
	237	*cp = AT25_WREN;
	238	status = spi_write(at25->spi, cp, 1);
	239	if (status < 0) {
3936e4c8	240	dev_dbg(&at25->spi->dev, "WREN --> %d\n", status);
b587b13a DB	241	break;
	242	}
	243
b4161f0b IS	244	instr = AT25_WRITE;
b4161f0b IS	245	if (at25->chip.flags & EE_INSTR_BIT3_IS_ADDR)
d059ed1b	246	if (offset >= BIT(at25->addrlen * 8))
b4161f0b IS	247	instr \|= AT25_INSTR_BIT3;
	248	*cp++ = instr;
	249
b587b13a DB	250	/* 8/16/24-bit address is written MSB first */
	251	switch (at25->addrlen) {
	252	default: /* case 3 */
	253	*cp++ = offset >> 16;
df561f66	254	fallthrough;
b587b13a DB	255	case 2:
b587b13a DB	256	*cp++ = offset >> 8;
df561f66	257	fallthrough;
b587b13a	258	case 1:
1ca54ce9	259	case 0: /* can't happen: for better code generation */
b587b13a DB	260	*cp++ = offset >> 0;
	261	}
	262
	263	/* Write as much of a page as we can */
	264	segment = buf_size - (offset % buf_size);
	265	if (segment > count)
	266	segment = count;
0a35780c BB	267	if (segment > maxsz)
0a35780c BB	268	segment = maxsz;
b587b13a DB	269	memcpy(cp, buf, segment);
	270	status = spi_write(at25->spi, bounce,
	271	segment + at25->addrlen + 1);
3936e4c8 AS	272	dev_dbg(&at25->spi->dev, "write %u bytes at %u --> %d\n",
3936e4c8 AS	273	segment, offset, status);
b587b13a DB	274	if (status < 0)
	275	break;
	276
1ca54ce9 AS	277	/*
	278	* REVISIT this should detect (or prevent) failed writes
	279	* to read-only sections of the EEPROM...
b587b13a DB	280	*/
	281
	282	/* Wait for non-busy status */
	283	timeout = jiffies + msecs_to_jiffies(EE_TIMEOUT);
	284	retries = 0;
	285	do {
b587b13a DB	286
	287	sr = spi_w8r8(at25->spi, AT25_RDSR);
	288	if (sr < 0 \|\| (sr & AT25_SR_nRDY)) {
	289	dev_dbg(&at25->spi->dev,
	290	"rdsr --> %d (%02x)\n", sr, sr);
	291	/* at HZ=100, this is sloooow */
	292	msleep(1);
	293	continue;
	294	}
	295	if (!(sr & AT25_SR_nRDY))
	296	break;
	297	} while (retries++ < 3 \|\| time_before_eq(jiffies, timeout));
	298
f0d83679	299	if ((sr < 0) \|\| (sr & AT25_SR_nRDY)) {
b587b13a	300	dev_err(&at25->spi->dev,
3936e4c8	301	"write %u bytes offset %u, timeout after %u msecs\n",
b587b13a DB	302	segment, offset,
	303	jiffies_to_msecs(jiffies -
	304	(timeout - EE_TIMEOUT)));
	305	status = -ETIMEDOUT;
	306	break;
	307	}
	308
	309	off += segment;
	310	buf += segment;
	311	count -= segment;
b587b13a DB	312
	313	} while (count > 0);
	314
	315	mutex_unlock(&at25->lock);
	316
	317	kfree(bounce);
01973a01	318	return status;
b587b13a DB	319	}
b587b13a DB	320
b587b13a DB	321	/-------------------------------------------------------------------------/
b587b13a DB	322
f60e7074	323	static int at25_fw_to_chip(struct device dev, struct spi_eeprom chip)
d6ae0d57 DD	324	{
d6ae0d57 DD	325	u32 val;
c329fe53	326	int err;
d6ae0d57	327
710f8af1	328	strscpy(chip->name, "at25", sizeof(chip->name));
d6ae0d57	329
c329fe53 AS	330	err = device_property_read_u32(dev, "size", &val);
	331	if (err)
	332	err = device_property_read_u32(dev, "at25,byte-len", &val);
	333	if (err) {
d6ae0d57	334	dev_err(dev, "Error: missing \"size\" property\n");
c329fe53	335	return err;
d6ae0d57	336	}
c329fe53	337	chip->byte_len = val;
d6ae0d57	338
c329fe53 AS	339	err = device_property_read_u32(dev, "pagesize", &val);
	340	if (err)
	341	err = device_property_read_u32(dev, "at25,page-size", &val);
	342	if (err) {
d6ae0d57	343	dev_err(dev, "Error: missing \"pagesize\" property\n");
c329fe53	344	return err;
d6ae0d57	345	}
c329fe53 AS	346	chip->page_size = val;
c329fe53 AS	347
fb422f44	348	err = device_property_read_u32(dev, "address-width", &val);
c329fe53	349	if (err) {
fb422f44	350	err = device_property_read_u32(dev, "at25,addr-mode", &val);
c329fe53 AS	351	if (err) {
	352	dev_err(dev, "Error: missing \"address-width\" property\n");
	353	return err;
d6ae0d57	354	}
fb422f44 AS	355	chip->flags = (u16)val;
fb422f44 AS	356	} else {
d6ae0d57	357	switch (val) {
f8d3bc10 GU	358	case 9:
f8d3bc10 GU	359	chip->flags \|= EE_INSTR_BIT3_IS_ADDR;
df561f66	360	fallthrough;
d6ae0d57 DD	361	case 8:
	362	chip->flags \|= EE_ADDR1;
	363	break;
	364	case 16:
	365	chip->flags \|= EE_ADDR2;
	366	break;
	367	case 24:
	368	chip->flags \|= EE_ADDR3;
	369	break;
	370	default:
	371	dev_err(dev,
	372	"Error: bad \"address-width\" property: %u\n",
	373	val);
	374	return -ENODEV;
	375	}
f60e7074	376	if (device_property_present(dev, "read-only"))
d6ae0d57 DD	377	chip->flags \|= EE_READONLY;
	378	}
	379	return 0;
	380	}
	381
31a45d27 AS	382	static int at25_fram_to_chip(struct device dev, struct spi_eeprom chip)
	383	{
	384	struct at25_data *at25 = container_of(chip, struct at25_data, chip);
	385	u8 sernum[FM25_SN_LEN];
	386	u8 id[FM25_ID_LEN];
	387	int i;
	388
710f8af1	389	strscpy(chip->name, "fm25", sizeof(chip->name));
31a45d27 AS	390
	391	/* Get ID of chip */
	392	fm25_aux_read(at25, id, FM25_RDID, FM25_ID_LEN);
	393	if (id[6] != 0xc2) {
	394	dev_err(dev, "Error: no Cypress FRAM (id %02x)\n", id[6]);
	395	return -ENODEV;
	396	}
	397	/* Set size found in ID */
	398	if (id[7] < 0x21 \|\| id[7] > 0x26) {
	399	dev_err(dev, "Error: unsupported size (id %02x)\n", id[7]);
	400	return -ENODEV;
	401	}
	402
	403	chip->byte_len = BIT(id[7] - 0x21 + 4) * 1024;
	404	if (chip->byte_len > 64 * 1024)
	405	chip->flags \|= EE_ADDR3;
	406	else
	407	chip->flags \|= EE_ADDR2;
	408
	409	if (id[8]) {
	410	fm25_aux_read(at25, sernum, FM25_RDSN, FM25_SN_LEN);
	411	/* Swap byte order */
	412	for (i = 0; i < FM25_SN_LEN; i++)
	413	at25->sernum[i] = sernum[FM25_SN_LEN - 1 - i];
	414	}
	415
	416	chip->page_size = PAGE_SIZE;
	417	return 0;
	418	}
	419
fd307a4a	420	static const struct of_device_id at25_of_match[] = {
d6471ab9 AS	421	{ .compatible = "atmel,at25" },
d6471ab9 AS	422	{ .compatible = "cypress,fm25" },
fd307a4a JP	423	{ }
	424	};
	425	MODULE_DEVICE_TABLE(of, at25_of_match);
	426
9e2cd444	427	static const struct spi_device_id at25_spi_ids[] = {
d6471ab9 AS	428	{ .name = "at25" },
d6471ab9 AS	429	{ .name = "fm25" },
9e2cd444 MB	430	{ }
	431	};
	432	MODULE_DEVICE_TABLE(spi, at25_spi_ids);
	433
b587b13a DB	434	static int at25_probe(struct spi_device *spi)
	435	{
	436	struct at25_data *at25 = NULL;
b587b13a DB	437	int err;
b587b13a DB	438	int sr;
01d3c42a	439	struct spi_eeprom *pdata;
5b557298	440	bool is_fram;
fd307a4a	441
5b557298 AS	442	err = device_property_match_string(&spi->dev, "compatible", "cypress,fm25");
	443	if (err >= 0)
	444	is_fram = true;
	445	else
	446	is_fram = false;
b587b13a	447
1ca54ce9 AS	448	/*
	449	* Ping the chip ... the status register is pretty portable,
	450	* unlike probing manufacturer IDs. We do expect that system
b587b13a DB	451	* firmware didn't write it in the past few milliseconds!
	452	*/
	453	sr = spi_w8r8(spi, AT25_RDSR);
	454	if (sr < 0 \|\| sr & AT25_SR_nRDY) {
c6ca97d2	455	dev_dbg(&spi->dev, "rdsr --> %d (%02x)\n", sr, sr);
01fe7b43	456	return -ENXIO;
b587b13a DB	457	}
b587b13a DB	458
a6501e4b KC	459	at25 = devm_kzalloc(&spi->dev, sizeof(*at25), GFP_KERNEL);
	460	if (!at25)
	461	return -ENOMEM;
	462
b587b13a	463	mutex_init(&at25->lock);
96b2a45c	464	at25->spi = spi;
41ddcf67	465	spi_set_drvdata(spi, at25);
b587b13a	466
01d3c42a AS	467	/* Chip description */
	468	pdata = dev_get_platdata(&spi->dev);
	469	if (pdata) {
	470	at25->chip = *pdata;
	471	} else {
31a45d27 AS	472	if (is_fram)
31a45d27 AS	473	err = at25_fram_to_chip(&spi->dev, &at25->chip);
fd307a4a	474	else
31a45d27 AS	475	err = at25_fw_to_chip(&spi->dev, &at25->chip);
	476	if (err)
	477	return err;
fd307a4a JP	478	}
	479
	480	/* For now we only support 8/16/24 bit addressing */
	481	if (at25->chip.flags & EE_ADDR1)
	482	at25->addrlen = 1;
	483	else if (at25->chip.flags & EE_ADDR2)
	484	at25->addrlen = 2;
	485	else if (at25->chip.flags & EE_ADDR3)
	486	at25->addrlen = 3;
	487	else {
	488	dev_dbg(&spi->dev, "unsupported address type\n");
	489	return -EINVAL;
	490	}
	491
	492	at25->nvmem_config.type = is_fram ? NVMEM_TYPE_FRAM : NVMEM_TYPE_EEPROM;
5a99f570 AL	493	at25->nvmem_config.name = dev_name(&spi->dev);
5a99f570 AL	494	at25->nvmem_config.dev = &spi->dev;
51902c12	495	at25->nvmem_config.read_only = at25->chip.flags & EE_READONLY;
5a99f570 AL	496	at25->nvmem_config.root_only = true;
	497	at25->nvmem_config.owner = THIS_MODULE;
	498	at25->nvmem_config.compat = true;
	499	at25->nvmem_config.base_dev = &spi->dev;
01973a01 SK	500	at25->nvmem_config.reg_read = at25_ee_read;
	501	at25->nvmem_config.reg_write = at25_ee_write;
	502	at25->nvmem_config.priv = at25;
284f52ac	503	at25->nvmem_config.stride = 1;
01973a01	504	at25->nvmem_config.word_size = 1;
51902c12	505	at25->nvmem_config.size = at25->chip.byte_len;
5a99f570	506
96d08fb4	507	at25->nvmem = devm_nvmem_register(&spi->dev, &at25->nvmem_config);
5a99f570 AL	508	if (IS_ERR(at25->nvmem))
	509	return PTR_ERR(at25->nvmem);
	510
fd307a4a	511	dev_info(&spi->dev, "%d %s %s %s%s, pagesize %u\n",
9a626577 RS	512	(at25->chip.byte_len < 1024) ?
9a626577 RS	513	at25->chip.byte_len : (at25->chip.byte_len / 1024),
51902c12	514	(at25->chip.byte_len < 1024) ? "Byte" : "KByte",
fd307a4a	515	at25->chip.name, is_fram ? "fram" : "eeprom",
51902c12	516	(at25->chip.flags & EE_READONLY) ? " (readonly)" : "",
fd307a4a	517	at25->chip.page_size);
b587b13a	518	return 0;
b587b13a DB	519	}
b587b13a DB	520
b587b13a DB	521	/-------------------------------------------------------------------------/
	522
	523	static struct spi_driver at25_driver = {
	524	.driver = {
	525	.name = "at25",
fbfdb6ed	526	.of_match_table = at25_of_match,
fd307a4a	527	.dev_groups = sernum_groups,
b587b13a DB	528	},
b587b13a DB	529	.probe = at25_probe,
9e2cd444	530	.id_table = at25_spi_ids,
b587b13a DB	531	};
b587b13a DB	532
a3dc3c9e	533	module_spi_driver(at25_driver);
b587b13a DB	534
	535	MODULE_DESCRIPTION("Driver for most SPI EEPROMs");
	536	MODULE_AUTHOR("David Brownell");
	537	MODULE_LICENSE("GPL");
e0626e38	538	MODULE_ALIAS("spi:at25");