[linux-2.6-block.git] / drivers / misc / eeprom / at24.c

/*
 * at24.c - handle most I2C EEPROMs
 *
 * Copyright (C) 2005-2007 David Brownell
 * Copyright (C) 2008 Wolfram Sang, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/mod_devicetable.h>
#include <linux/log2.h>
#include <linux/bitops.h>
#include <linux/jiffies.h>
#include <linux/of.h>
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/nvmem-provider.h>
#include <linux/platform_data/at24.h>

/*
 * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
 * Differences between different vendor product lines (like Atmel AT24C or
 * MicroChip 24LC, etc) won't much matter for typical read/write access.
 * There are also I2C RAM chips, likewise interchangeable. One example
 * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes).
 *
 * However, misconfiguration can lose data. "Set 16-bit memory address"
 * to a part with 8-bit addressing will overwrite data. Writing with too
 * big a page size also loses data. And it's not safe to assume that the
 * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC
 * uses 0x51, for just one example.
 *
 * Accordingly, explicit board-specific configuration data should be used
 * in almost all cases. (One partial exception is an SMBus used to access
 * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.)
 *
 * So this driver uses "new style" I2C driver binding, expecting to be
 * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or
 * similar kernel-resident tables; or, configuration data coming from
 * a bootloader.
 *
 * Other than binding model, current differences from "eeprom" driver are
 * that this one handles write access and isn't restricted to 24c02 devices.
 * It also handles larger devices (32 kbit and up) with two-byte addresses,
 * which won't work on pure SMBus systems.
 */

struct at24_data {
	struct at24_platform_data chip;
	int use_smbus;
	int use_smbus_write;

	/*
	 * Lock protects against activities from other Linux tasks,
	 * but not from changes by other I2C masters.
	 */
	struct mutex lock;

	u8 *writebuf;
	unsigned write_max;
	unsigned num_addresses;

	struct nvmem_config nvmem_config;
	struct nvmem_device *nvmem;

	/*
	 * Some chips tie up multiple I2C addresses; dummy devices reserve
	 * them for us, and we'll use them with SMBus calls.
	 */
	struct i2c_client *client[];
};

/*
 * This parameter is to help this driver avoid blocking other drivers out
 * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C
 * clock, one 256 byte read takes about 1/43 second which is excessive;
 * but the 1/170 second it takes at 400 kHz may be quite reasonable; and
 * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible.
 *
 * This value is forced to be a power of two so that writes align on pages.
 */
static unsigned io_limit = 128;
module_param(io_limit, uint, 0);
MODULE_PARM_DESC(io_limit, "Maximum bytes per I/O (default 128)");

/*
 * Specs often allow 5 msec for a page write, sometimes 20 msec;
 * it's important to recover from write timeouts.
 */
static unsigned write_timeout = 25;
module_param(write_timeout, uint, 0);
MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes (default 25)");

#define AT24_SIZE_BYTELEN 5
#define AT24_SIZE_FLAGS 8

#define AT24_BITMASK(x) (BIT(x) - 1)

/* create non-zero magic value for given eeprom parameters */
#define AT24_DEVICE_MAGIC(_len, _flags) 		\
	((1 << AT24_SIZE_FLAGS | (_flags)) 		\
	    << AT24_SIZE_BYTELEN | ilog2(_len))

static const struct i2c_device_id at24_ids[] = {
	/* needs 8 addresses as A0-A2 are ignored */
	{ "24c00", AT24_DEVICE_MAGIC(128 / 8, AT24_FLAG_TAKE8ADDR) },
	/* old variants can't be handled with this generic entry! */
	{ "24c01", AT24_DEVICE_MAGIC(1024 / 8, 0) },
	{ "24c02", AT24_DEVICE_MAGIC(2048 / 8, 0) },
	/* spd is a 24c02 in memory DIMMs */
	{ "spd", AT24_DEVICE_MAGIC(2048 / 8,
		AT24_FLAG_READONLY | AT24_FLAG_IRUGO) },
	{ "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
	/* 24rf08 quirk is handled at i2c-core */
	{ "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
	{ "24c16", AT24_DEVICE_MAGIC(16384 / 8, 0) },
	{ "24c32", AT24_DEVICE_MAGIC(32768 / 8, AT24_FLAG_ADDR16) },
	{ "24c64", AT24_DEVICE_MAGIC(65536 / 8, AT24_FLAG_ADDR16) },
	{ "24c128", AT24_DEVICE_MAGIC(131072 / 8, AT24_FLAG_ADDR16) },
	{ "24c256", AT24_DEVICE_MAGIC(262144 / 8, AT24_FLAG_ADDR16) },
	{ "24c512", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
	{ "24c1024", AT24_DEVICE_MAGIC(1048576 / 8, AT24_FLAG_ADDR16) },
	{ "at24", 0 },
	{ /* END OF LIST */ }
};
MODULE_DEVICE_TABLE(i2c, at24_ids);

static const struct acpi_device_id at24_acpi_ids[] = {
	{ "INT3499", AT24_DEVICE_MAGIC(8192 / 8, 0) },
	{ }
};
MODULE_DEVICE_TABLE(acpi, at24_acpi_ids);

/*-------------------------------------------------------------------------*/

/*
 * This routine supports chips which consume multiple I2C addresses. It
 * computes the addressing information to be used for a given r/w request.
 * Assumes that sanity checks for offset happened at sysfs-layer.
 */
static struct i2c_client *at24_translate_offset(struct at24_data *at24,
		unsigned *offset)
{
	unsigned i;

	if (at24->chip.flags & AT24_FLAG_ADDR16) {
		i = *offset >> 16;
		*offset &= 0xffff;
	} else {
		i = *offset >> 8;
		*offset &= 0xff;
	}

	return at24->client[i];
}

static ssize_t at24_eeprom_read(struct at24_data *at24, char *buf,
		unsigned offset, size_t count)
{
	struct i2c_msg msg[2];
	u8 msgbuf[2];
	struct i2c_client *client;
	unsigned long timeout, read_time;
	int status, i;

	memset(msg, 0, sizeof(msg));

	/*
	 * REVISIT some multi-address chips don't rollover page reads to
	 * the next slave address, so we may need to truncate the count.
	 * Those chips might need another quirk flag.
	 *
	 * If the real hardware used four adjacent 24c02 chips and that
	 * were misconfigured as one 24c08, that would be a similar effect:
	 * one "eeprom" file not four, but larger reads would fail when
	 * they crossed certain pages.
	 */

	/*
	 * Slave address and byte offset derive from the offset. Always
	 * set the byte address; on a multi-master board, another master
	 * may have changed the chip's "current" address pointer.
	 */
	client = at24_translate_offset(at24, &offset);

	if (count > io_limit)
		count = io_limit;

	if (at24->use_smbus) {
		/* Smaller eeproms can work given some SMBus extension calls */
		if (count > I2C_SMBUS_BLOCK_MAX)
			count = I2C_SMBUS_BLOCK_MAX;
	} else {
		/*
		 * When we have a better choice than SMBus calls, use a
		 * combined I2C message. Write address; then read up to
		 * io_limit data bytes. Note that read page rollover helps us
		 * here (unlike writes). msgbuf is u8 and will cast to our
		 * needs.
		 */
		i = 0;
		if (at24->chip.flags & AT24_FLAG_ADDR16)
			msgbuf[i++] = offset >> 8;
		msgbuf[i++] = offset;

		msg[0].addr = client->addr;
		msg[0].buf = msgbuf;
		msg[0].len = i;

		msg[1].addr = client->addr;
		msg[1].flags = I2C_M_RD;
		msg[1].buf = buf;
		msg[1].len = count;
	}

	/*
	 * Reads fail if the previous write didn't complete yet. We may
	 * loop a few times until this one succeeds, waiting at least
	 * long enough for one entire page write to work.
	 */
	timeout = jiffies + msecs_to_jiffies(write_timeout);
	do {
		read_time = jiffies;
		if (at24->use_smbus) {
			status = i2c_smbus_read_i2c_block_data_or_emulated(client, offset,
									   count, buf);
		} else {
			status = i2c_transfer(client->adapter, msg, 2);
			if (status == 2)
				status = count;
		}
		dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n",
				count, offset, status, jiffies);

		if (status == count)
			return count;

		usleep_range(1000, 1500);
	} while (time_before(read_time, timeout));

	return -ETIMEDOUT;
}

static int at24_read(void *priv, unsigned int off, void *val, size_t count)
{
	struct at24_data *at24 = priv;
	char *buf = val;

	if (unlikely(!count))
		return count;

	/*
	 * Read data from chip, protecting against concurrent updates
	 * from this host, but not from other I2C masters.
	 */
	mutex_lock(&at24->lock);

	while (count) {
		int	status;

		status = at24_eeprom_read(at24, buf, off, count);
		if (status < 0) {
			mutex_unlock(&at24->lock);
			return status;
		}
		buf += status;
		off += status;
		count -= status;
	}

	mutex_unlock(&at24->lock);

	return 0;
}

/*
 * Note that if the hardware write-protect pin is pulled high, the whole
 * chip is normally write protected. But there are plenty of product
 * variants here, including OTP fuses and partial chip protect.
 *
 * We only use page mode writes; the alternative is sloooow. This routine
 * writes at most one page.
 */
static ssize_t at24_eeprom_write(struct at24_data *at24, const char *buf,
		unsigned offset, size_t count)
{
	struct i2c_client *client;
	struct i2c_msg msg;
	ssize_t status = 0;
	unsigned long timeout, write_time;
	unsigned next_page;

	/* Get corresponding I2C address and adjust offset */
	client = at24_translate_offset(at24, &offset);

	/* write_max is at most a page */
	if (count > at24->write_max)
		count = at24->write_max;

	/* Never roll over backwards, to the start of this page */
	next_page = roundup(offset + 1, at24->chip.page_size);
	if (offset + count > next_page)
		count = next_page - offset;

	/* If we'll use I2C calls for I/O, set up the message */
	if (!at24->use_smbus) {
		int i = 0;

		msg.addr = client->addr;
		msg.flags = 0;

		/* msg.buf is u8 and casts will mask the values */
		msg.buf = at24->writebuf;
		if (at24->chip.flags & AT24_FLAG_ADDR16)
			msg.buf[i++] = offset >> 8;

		msg.buf[i++] = offset;
		memcpy(&msg.buf[i], buf, count);
		msg.len = i + count;
	}

	/*
	 * Writes fail if the previous one didn't complete yet. We may
	 * loop a few times until this one succeeds, waiting at least
	 * long enough for one entire page write to work.
	 */
	timeout = jiffies + msecs_to_jiffies(write_timeout);
	do {
		write_time = jiffies;
		if (at24->use_smbus_write) {
			switch (at24->use_smbus_write) {
			case I2C_SMBUS_I2C_BLOCK_DATA:
				status = i2c_smbus_write_i2c_block_data(client,
						offset, count, buf);
				break;
			case I2C_SMBUS_BYTE_DATA:
				status = i2c_smbus_write_byte_data(client,
						offset, buf[0]);
				break;
			}

			if (status == 0)
				status = count;
		} else {
			status = i2c_transfer(client->adapter, &msg, 1);
			if (status == 1)
				status = count;
		}
		dev_dbg(&client->dev, "write %zu@%d --> %zd (%ld)\n",
				count, offset, status, jiffies);

		if (status == count)
			return count;

		usleep_range(1000, 1500);
	} while (time_before(write_time, timeout));

	return -ETIMEDOUT;
}

static int at24_write(void *priv, unsigned int off, void *val, size_t count)
{
	struct at24_data *at24 = priv;
	char *buf = val;

	if (unlikely(!count))
		return -EINVAL;

	/*
	 * Write data to chip, protecting against concurrent updates
	 * from this host, but not from other I2C masters.
	 */
	mutex_lock(&at24->lock);

	while (count) {
		int status;

		status = at24_eeprom_write(at24, buf, off, count);
		if (status < 0) {
			mutex_unlock(&at24->lock);
			return status;
		}
		buf += status;
		off += status;
		count -= status;
	}

	mutex_unlock(&at24->lock);

	return 0;
}

#ifdef CONFIG_OF
static void at24_get_ofdata(struct i2c_client *client,
		struct at24_platform_data *chip)
{
	const __be32 *val;
	struct device_node *node = client->dev.of_node;

	if (node) {
		if (of_get_property(node, "read-only", NULL))
			chip->flags |= AT24_FLAG_READONLY;
		val = of_get_property(node, "pagesize", NULL);
		if (val)
			chip->page_size = be32_to_cpup(val);
	}
}
#else
static void at24_get_ofdata(struct i2c_client *client,
		struct at24_platform_data *chip)
{ }
#endif /* CONFIG_OF */

static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
{
	struct at24_platform_data chip;
	kernel_ulong_t magic = 0;
	bool writable;
	int use_smbus = 0;
	int use_smbus_write = 0;
	struct at24_data *at24;
	int err;
	unsigned i, num_addresses;

	if (client->dev.platform_data) {
		chip = *(struct at24_platform_data *)client->dev.platform_data;
	} else {
		if (id) {
			magic = id->driver_data;
		} else {
			const struct acpi_device_id *aid;

			aid = acpi_match_device(at24_acpi_ids, &client->dev);
			if (aid)
				magic = aid->driver_data;
		}
		if (!magic)
			return -ENODEV;

		chip.byte_len = BIT(magic & AT24_BITMASK(AT24_SIZE_BYTELEN));
		magic >>= AT24_SIZE_BYTELEN;
		chip.flags = magic & AT24_BITMASK(AT24_SIZE_FLAGS);
		/*
		 * This is slow, but we can't know all eeproms, so we better
		 * play safe. Specifying custom eeprom-types via platform_data
		 * is recommended anyhow.
		 */
		chip.page_size = 1;

		/* update chipdata if OF is present */
		at24_get_ofdata(client, &chip);

		chip.setup = NULL;
		chip.context = NULL;
	}

	if (!is_power_of_2(chip.byte_len))
		dev_warn(&client->dev,
			"byte_len looks suspicious (no power of 2)!\n");
	if (!chip.page_size) {
		dev_err(&client->dev, "page_size must not be 0!\n");
		return -EINVAL;
	}
	if (!is_power_of_2(chip.page_size))
		dev_warn(&client->dev,
			"page_size looks suspicious (no power of 2)!\n");

	/* Use I2C operations unless we're stuck with SMBus extensions. */
	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
		if (chip.flags & AT24_FLAG_ADDR16)
			return -EPFNOSUPPORT;

		if (i2c_check_functionality(client->adapter,
				I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
			use_smbus = I2C_SMBUS_I2C_BLOCK_DATA;
		} else if (i2c_check_functionality(client->adapter,
				I2C_FUNC_SMBUS_READ_WORD_DATA)) {
			use_smbus = I2C_SMBUS_WORD_DATA;
		} else if (i2c_check_functionality(client->adapter,
				I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
			use_smbus = I2C_SMBUS_BYTE_DATA;
		} else {
			return -EPFNOSUPPORT;
		}

		if (i2c_check_functionality(client->adapter,
				I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
			use_smbus_write = I2C_SMBUS_I2C_BLOCK_DATA;
		} else if (i2c_check_functionality(client->adapter,
				I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
			use_smbus_write = I2C_SMBUS_BYTE_DATA;
			chip.page_size = 1;
		}
	}

	if (chip.flags & AT24_FLAG_TAKE8ADDR)
		num_addresses = 8;
	else
		num_addresses =	DIV_ROUND_UP(chip.byte_len,
			(chip.flags & AT24_FLAG_ADDR16) ? 65536 : 256);

	at24 = devm_kzalloc(&client->dev, sizeof(struct at24_data) +
		num_addresses * sizeof(struct i2c_client *), GFP_KERNEL);
	if (!at24)
		return -ENOMEM;

	mutex_init(&at24->lock);
	at24->use_smbus = use_smbus;
	at24->use_smbus_write = use_smbus_write;
	at24->chip = chip;
	at24->num_addresses = num_addresses;

	writable = !(chip.flags & AT24_FLAG_READONLY);
	if (writable) {
		if (!use_smbus || use_smbus_write) {

			unsigned write_max = chip.page_size;

			if (write_max > io_limit)
				write_max = io_limit;
			if (use_smbus && write_max > I2C_SMBUS_BLOCK_MAX)
				write_max = I2C_SMBUS_BLOCK_MAX;
			at24->write_max = write_max;

			/* buffer (data + address at the beginning) */
			at24->writebuf = devm_kzalloc(&client->dev,
				write_max + 2, GFP_KERNEL);
			if (!at24->writebuf)
				return -ENOMEM;
		} else {
			dev_warn(&client->dev,
				"cannot write due to controller restrictions.");
		}
	}

	at24->client[0] = client;

	/* use dummy devices for multiple-address chips */
	for (i = 1; i < num_addresses; i++) {
		at24->client[i] = i2c_new_dummy(client->adapter,
					client->addr + i);
		if (!at24->client[i]) {
			dev_err(&client->dev, "address 0x%02x unavailable\n",
					client->addr + i);
			err = -EADDRINUSE;
			goto err_clients;
		}
	}

	at24->nvmem_config.name = dev_name(&client->dev);
	at24->nvmem_config.dev = &client->dev;
	at24->nvmem_config.read_only = !writable;
	at24->nvmem_config.root_only = true;
	at24->nvmem_config.owner = THIS_MODULE;
	at24->nvmem_config.compat = true;
	at24->nvmem_config.base_dev = &client->dev;
	at24->nvmem_config.reg_read = at24_read;
	at24->nvmem_config.reg_write = at24_write;
	at24->nvmem_config.priv = at24;
	at24->nvmem_config.stride = 4;
	at24->nvmem_config.word_size = 1;
	at24->nvmem_config.size = chip.byte_len;

	at24->nvmem = nvmem_register(&at24->nvmem_config);

	if (IS_ERR(at24->nvmem)) {
		err = PTR_ERR(at24->nvmem);
		goto err_clients;
	}

	i2c_set_clientdata(client, at24);

	dev_info(&client->dev, "%u byte %s EEPROM, %s, %u bytes/write\n",
		chip.byte_len, client->name,
		writable ? "writable" : "read-only", at24->write_max);
	if (use_smbus == I2C_SMBUS_WORD_DATA ||
	    use_smbus == I2C_SMBUS_BYTE_DATA) {
		dev_notice(&client->dev, "Falling back to %s reads, "
			   "performance will suffer\n", use_smbus ==
			   I2C_SMBUS_WORD_DATA ? "word" : "byte");
	}

	/* export data to kernel code */
	if (chip.setup)
		chip.setup(at24->nvmem, chip.context);

	return 0;

err_clients:
	for (i = 1; i < num_addresses; i++)
		if (at24->client[i])
			i2c_unregister_device(at24->client[i]);

	return err;
}

static int at24_remove(struct i2c_client *client)
{
	struct at24_data *at24;
	int i;

	at24 = i2c_get_clientdata(client);

	nvmem_unregister(at24->nvmem);

	for (i = 1; i < at24->num_addresses; i++)
		i2c_unregister_device(at24->client[i]);

	return 0;
}

/*-------------------------------------------------------------------------*/

static struct i2c_driver at24_driver = {
	.driver = {
		.name = "at24",
		.acpi_match_table = ACPI_PTR(at24_acpi_ids),
	},
	.probe = at24_probe,
	.remove = at24_remove,
	.id_table = at24_ids,
};

static int __init at24_init(void)
{
	if (!io_limit) {
		pr_err("at24: io_limit must not be 0!\n");
		return -EINVAL;
	}

	io_limit = rounddown_pow_of_two(io_limit);
	return i2c_add_driver(&at24_driver);
}
module_init(at24_init);

static void __exit at24_exit(void)
{
	i2c_del_driver(&at24_driver);
}
module_exit(at24_exit);

MODULE_DESCRIPTION("Driver for most I2C EEPROMs");
MODULE_AUTHOR("David Brownell and Wolfram Sang");
MODULE_LICENSE("GPL");
Commit	Line	Data
2b7a5056 WS	1	/*
	2	* at24.c - handle most I2C EEPROMs
	3	*
	4	* Copyright (C) 2005-2007 David Brownell
	5	* Copyright (C) 2008 Wolfram Sang, Pengutronix
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12	#include <linux/kernel.h>
	13	#include <linux/init.h>
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/delay.h>
	17	#include <linux/mutex.h>
2b7a5056 WS	18	#include <linux/mod_devicetable.h>
	19	#include <linux/log2.h>
	20	#include <linux/bitops.h>
	21	#include <linux/jiffies.h>
9ed030d7	22	#include <linux/of.h>
40d8edc9	23	#include <linux/acpi.h>
2b7a5056	24	#include <linux/i2c.h>
57d15550	25	#include <linux/nvmem-provider.h>
25f73ed5	26	#include <linux/platform_data/at24.h>
2b7a5056 WS	27
	28	/*
	29	* I2C EEPROMs from most vendors are inexpensive and mostly interchangeable.
	30	* Differences between different vendor product lines (like Atmel AT24C or
	31	* MicroChip 24LC, etc) won't much matter for typical read/write access.
	32	* There are also I2C RAM chips, likewise interchangeable. One example
	33	* would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes).
	34	*
	35	* However, misconfiguration can lose data. "Set 16-bit memory address"
	36	* to a part with 8-bit addressing will overwrite data. Writing with too
	37	* big a page size also loses data. And it's not safe to assume that the
	38	* conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC
	39	* uses 0x51, for just one example.
	40	*
	41	* Accordingly, explicit board-specific configuration data should be used
	42	* in almost all cases. (One partial exception is an SMBus used to access
	43	* "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.)
	44	*
	45	* So this driver uses "new style" I2C driver binding, expecting to be
	46	* told what devices exist. That may be in arch/X/mach-Y/board-Z.c or
	47	* similar kernel-resident tables; or, configuration data coming from
	48	* a bootloader.
	49	*
	50	* Other than binding model, current differences from "eeprom" driver are
	51	* that this one handles write access and isn't restricted to 24c02 devices.
	52	* It also handles larger devices (32 kbit and up) with two-byte addresses,
	53	* which won't work on pure SMBus systems.
	54	*/
	55
	56	struct at24_data {
	57	struct at24_platform_data chip;
7aeb9664	58	int use_smbus;
a839ce66	59	int use_smbus_write;
2b7a5056 WS	60
	61	/*
	62	* Lock protects against activities from other Linux tasks,
	63	* but not from changes by other I2C masters.
	64	*/
	65	struct mutex lock;
2b7a5056 WS	66
	67	u8 *writebuf;
	68	unsigned write_max;
	69	unsigned num_addresses;
	70
57d15550 AL	71	struct nvmem_config nvmem_config;
	72	struct nvmem_device *nvmem;
	73
2b7a5056 WS	74	/*
	75	* Some chips tie up multiple I2C addresses; dummy devices reserve
	76	* them for us, and we'll use them with SMBus calls.
	77	*/
	78	struct i2c_client *client[];
	79	};
	80
	81	/*
	82	* This parameter is to help this driver avoid blocking other drivers out
	83	* of I2C for potentially troublesome amounts of time. With a 100 kHz I2C
	84	* clock, one 256 byte read takes about 1/43 second which is excessive;
	85	* but the 1/170 second it takes at 400 kHz may be quite reasonable; and
	86	* at 1 MHz (Fm+) a 1/430 second delay could easily be invisible.
	87	*
	88	* This value is forced to be a power of two so that writes align on pages.
	89	*/
	90	static unsigned io_limit = 128;
	91	module_param(io_limit, uint, 0);
	92	MODULE_PARM_DESC(io_limit, "Maximum bytes per I/O (default 128)");
	93
	94	/*
	95	* Specs often allow 5 msec for a page write, sometimes 20 msec;
	96	* it's important to recover from write timeouts.
	97	*/
	98	static unsigned write_timeout = 25;
	99	module_param(write_timeout, uint, 0);
	100	MODULE_PARM_DESC(write_timeout, "Time (in ms) to try writes (default 25)");
	101
	102	#define AT24_SIZE_BYTELEN 5
	103	#define AT24_SIZE_FLAGS 8
	104
	105	#define AT24_BITMASK(x) (BIT(x) - 1)
	106
	107	/* create non-zero magic value for given eeprom parameters */
	108	#define AT24_DEVICE_MAGIC(_len, _flags) \
	109	((1 << AT24_SIZE_FLAGS \| (_flags)) \
	110	<< AT24_SIZE_BYTELEN \| ilog2(_len))
	111
	112	static const struct i2c_device_id at24_ids[] = {
	113	/* needs 8 addresses as A0-A2 are ignored */
	114	{ "24c00", AT24_DEVICE_MAGIC(128 / 8, AT24_FLAG_TAKE8ADDR) },
	115	/* old variants can't be handled with this generic entry! */
	116	{ "24c01", AT24_DEVICE_MAGIC(1024 / 8, 0) },
	117	{ "24c02", AT24_DEVICE_MAGIC(2048 / 8, 0) },
	118	/* spd is a 24c02 in memory DIMMs */
	119	{ "spd", AT24_DEVICE_MAGIC(2048 / 8,
	120	AT24_FLAG_READONLY \| AT24_FLAG_IRUGO) },
	121	{ "24c04", AT24_DEVICE_MAGIC(4096 / 8, 0) },
	122	/* 24rf08 quirk is handled at i2c-core */
	123	{ "24c08", AT24_DEVICE_MAGIC(8192 / 8, 0) },
	124	{ "24c16", AT24_DEVICE_MAGIC(16384 / 8, 0) },
	125	{ "24c32", AT24_DEVICE_MAGIC(32768 / 8, AT24_FLAG_ADDR16) },
	126	{ "24c64", AT24_DEVICE_MAGIC(65536 / 8, AT24_FLAG_ADDR16) },
	127	{ "24c128", AT24_DEVICE_MAGIC(131072 / 8, AT24_FLAG_ADDR16) },
	128	{ "24c256", AT24_DEVICE_MAGIC(262144 / 8, AT24_FLAG_ADDR16) },
	129	{ "24c512", AT24_DEVICE_MAGIC(524288 / 8, AT24_FLAG_ADDR16) },
	130	{ "24c1024", AT24_DEVICE_MAGIC(1048576 / 8, AT24_FLAG_ADDR16) },
	131	{ "at24", 0 },
	132	{ /* END OF LIST */ }
	133	};
	134	MODULE_DEVICE_TABLE(i2c, at24_ids);
	135
40d8edc9 AS	136	static const struct acpi_device_id at24_acpi_ids[] = {
	137	{ "INT3499", AT24_DEVICE_MAGIC(8192 / 8, 0) },
	138	{ }
	139	};
	140	MODULE_DEVICE_TABLE(acpi, at24_acpi_ids);
	141
2b7a5056 WS	142	/-------------------------------------------------------------------------/
	143
	144	/*
	145	* This routine supports chips which consume multiple I2C addresses. It
	146	* computes the addressing information to be used for a given r/w request.
	147	* Assumes that sanity checks for offset happened at sysfs-layer.
	148	*/
	149	static struct i2c_client at24_translate_offset(struct at24_data at24,
	150	unsigned *offset)
	151	{
	152	unsigned i;
	153
	154	if (at24->chip.flags & AT24_FLAG_ADDR16) {
	155	i = *offset >> 16;
	156	*offset &= 0xffff;
	157	} else {
	158	i = *offset >> 8;
	159	*offset &= 0xff;
	160	}
	161
	162	return at24->client[i];
	163	}
	164
	165	static ssize_t at24_eeprom_read(struct at24_data at24, char buf,
	166	unsigned offset, size_t count)
	167	{
	168	struct i2c_msg msg[2];
	169	u8 msgbuf[2];
	170	struct i2c_client *client;
4d29196c	171	unsigned long timeout, read_time;
2b7a5056 WS	172	int status, i;
	173
	174	memset(msg, 0, sizeof(msg));
	175
	176	/*
	177	* REVISIT some multi-address chips don't rollover page reads to
	178	* the next slave address, so we may need to truncate the count.
	179	* Those chips might need another quirk flag.
	180	*
	181	* If the real hardware used four adjacent 24c02 chips and that
	182	* were misconfigured as one 24c08, that would be a similar effect:
	183	* one "eeprom" file not four, but larger reads would fail when
	184	* they crossed certain pages.
	185	*/
	186
	187	/*
	188	* Slave address and byte offset derive from the offset. Always
	189	* set the byte address; on a multi-master board, another master
	190	* may have changed the chip's "current" address pointer.
	191	*/
	192	client = at24_translate_offset(at24, &offset);
	193
	194	if (count > io_limit)
	195	count = io_limit;
	196
2cd9fbd0	197	if (at24->use_smbus) {
4d29196c	198	/* Smaller eeproms can work given some SMBus extension calls */
2b7a5056 WS	199	if (count > I2C_SMBUS_BLOCK_MAX)
2b7a5056 WS	200	count = I2C_SMBUS_BLOCK_MAX;
2cd9fbd0	201	} else {
4d29196c WS	202	/*
	203	* When we have a better choice than SMBus calls, use a
	204	* combined I2C message. Write address; then read up to
	205	* io_limit data bytes. Note that read page rollover helps us
	206	* here (unlike writes). msgbuf is u8 and will cast to our
	207	* needs.
	208	*/
	209	i = 0;
	210	if (at24->chip.flags & AT24_FLAG_ADDR16)
	211	msgbuf[i++] = offset >> 8;
	212	msgbuf[i++] = offset;
	213
	214	msg[0].addr = client->addr;
	215	msg[0].buf = msgbuf;
	216	msg[0].len = i;
	217
	218	msg[1].addr = client->addr;
	219	msg[1].flags = I2C_M_RD;
	220	msg[1].buf = buf;
	221	msg[1].len = count;
2b7a5056 WS	222	}
	223
	224	/*
4d29196c WS	225	* Reads fail if the previous write didn't complete yet. We may
	226	* loop a few times until this one succeeds, waiting at least
	227	* long enough for one entire page write to work.
2b7a5056	228	*/
4d29196c WS	229	timeout = jiffies + msecs_to_jiffies(write_timeout);
	230	do {
	231	read_time = jiffies;
2cd9fbd0 IT	232	if (at24->use_smbus) {
	233	status = i2c_smbus_read_i2c_block_data_or_emulated(client, offset,
	234	count, buf);
	235	} else {
4d29196c WS	236	status = i2c_transfer(client->adapter, msg, 2);
	237	if (status == 2)
	238	status = count;
	239	}
	240	dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n",
	241	count, offset, status, jiffies);
2b7a5056	242
4d29196c WS	243	if (status == count)
4d29196c WS	244	return count;
2b7a5056	245
1d98d0ec	246	usleep_range(1000, 1500);
4d29196c	247	} while (time_before(read_time, timeout));
2b7a5056	248
4d29196c	249	return -ETIMEDOUT;
2b7a5056 WS	250	}
2b7a5056 WS	251
cf0361a2	252	static int at24_read(void priv, unsigned int off, void val, size_t count)
2b7a5056	253	{
cf0361a2 SK	254	struct at24_data *at24 = priv;
cf0361a2 SK	255	char *buf = val;
2b7a5056	256
2b7a5056 WS	257	if (unlikely(!count))
	258	return count;
	259
	260	/*
	261	* Read data from chip, protecting against concurrent updates
	262	* from this host, but not from other I2C masters.
	263	*/
	264	mutex_lock(&at24->lock);
	265
	266	while (count) {
cf0361a2	267	int status;
2b7a5056 WS	268
2b7a5056 WS	269	status = at24_eeprom_read(at24, buf, off, count);
cf0361a2 SK	270	if (status < 0) {
	271	mutex_unlock(&at24->lock);
	272	return status;
2b7a5056 WS	273	}
	274	buf += status;
	275	off += status;
	276	count -= status;
2b7a5056 WS	277	}
	278
	279	mutex_unlock(&at24->lock);
	280
cf0361a2	281	return 0;
2b7a5056 WS	282	}
2b7a5056 WS	283
2b7a5056 WS	284	/*
	285	* Note that if the hardware write-protect pin is pulled high, the whole
	286	* chip is normally write protected. But there are plenty of product
	287	* variants here, including OTP fuses and partial chip protect.
	288	*
	289	* We only use page mode writes; the alternative is sloooow. This routine
	290	* writes at most one page.
	291	*/
280ca299	292	static ssize_t at24_eeprom_write(struct at24_data at24, const char buf,
2b7a5056 WS	293	unsigned offset, size_t count)
	294	{
	295	struct i2c_client *client;
	296	struct i2c_msg msg;
a839ce66	297	ssize_t status = 0;
2b7a5056 WS	298	unsigned long timeout, write_time;
	299	unsigned next_page;
	300
	301	/* Get corresponding I2C address and adjust offset */
	302	client = at24_translate_offset(at24, &offset);
	303
	304	/* write_max is at most a page */
	305	if (count > at24->write_max)
	306	count = at24->write_max;
	307
	308	/* Never roll over backwards, to the start of this page */
	309	next_page = roundup(offset + 1, at24->chip.page_size);
	310	if (offset + count > next_page)
	311	count = next_page - offset;
	312
	313	/* If we'll use I2C calls for I/O, set up the message */
	314	if (!at24->use_smbus) {
	315	int i = 0;
	316
	317	msg.addr = client->addr;
	318	msg.flags = 0;
	319
	320	/* msg.buf is u8 and casts will mask the values */
	321	msg.buf = at24->writebuf;
	322	if (at24->chip.flags & AT24_FLAG_ADDR16)
	323	msg.buf[i++] = offset >> 8;
	324
	325	msg.buf[i++] = offset;
	326	memcpy(&msg.buf[i], buf, count);
	327	msg.len = i + count;
	328	}
	329
	330	/*
	331	* Writes fail if the previous one didn't complete yet. We may
	332	* loop a few times until this one succeeds, waiting at least
	333	* long enough for one entire page write to work.
	334	*/
	335	timeout = jiffies + msecs_to_jiffies(write_timeout);
	336	do {
	337	write_time = jiffies;
a839ce66 CG	338	if (at24->use_smbus_write) {
	339	switch (at24->use_smbus_write) {
	340	case I2C_SMBUS_I2C_BLOCK_DATA:
	341	status = i2c_smbus_write_i2c_block_data(client,
	342	offset, count, buf);
	343	break;
	344	case I2C_SMBUS_BYTE_DATA:
	345	status = i2c_smbus_write_byte_data(client,
	346	offset, buf[0]);
	347	break;
	348	}
	349
2b7a5056 WS	350	if (status == 0)
	351	status = count;
	352	} else {
	353	status = i2c_transfer(client->adapter, &msg, 1);
	354	if (status == 1)
	355	status = count;
	356	}
2ce5b34f	357	dev_dbg(&client->dev, "write %zu@%d --> %zd (%ld)\n",
2b7a5056 WS	358	count, offset, status, jiffies);
	359
	360	if (status == count)
	361	return count;
	362
1d98d0ec	363	usleep_range(1000, 1500);
2b7a5056 WS	364	} while (time_before(write_time, timeout));
	365
	366	return -ETIMEDOUT;
	367	}
	368
cf0361a2	369	static int at24_write(void priv, unsigned int off, void val, size_t count)
2b7a5056	370	{
cf0361a2 SK	371	struct at24_data *at24 = priv;
cf0361a2 SK	372	char *buf = val;
2b7a5056	373
2b7a5056	374	if (unlikely(!count))
cf0361a2	375	return -EINVAL;
2b7a5056 WS	376
	377	/*
	378	* Write data to chip, protecting against concurrent updates
	379	* from this host, but not from other I2C masters.
	380	*/
	381	mutex_lock(&at24->lock);
	382
	383	while (count) {
cf0361a2	384	int status;
2b7a5056 WS	385
2b7a5056 WS	386	status = at24_eeprom_write(at24, buf, off, count);
cf0361a2 SK	387	if (status < 0) {
	388	mutex_unlock(&at24->lock);
	389	return status;
2b7a5056 WS	390	}
	391	buf += status;
	392	off += status;
	393	count -= status;
2b7a5056 WS	394	}
	395
	396	mutex_unlock(&at24->lock);
	397
57d15550 AL	398	return 0;
	399	}
	400
9ed030d7 WS	401	#ifdef CONFIG_OF
	402	static void at24_get_ofdata(struct i2c_client *client,
	403	struct at24_platform_data *chip)
	404	{
	405	const __be32 *val;
	406	struct device_node *node = client->dev.of_node;
	407
	408	if (node) {
	409	if (of_get_property(node, "read-only", NULL))
	410	chip->flags \|= AT24_FLAG_READONLY;
	411	val = of_get_property(node, "pagesize", NULL);
	412	if (val)
	413	chip->page_size = be32_to_cpup(val);
	414	}
	415	}
	416	#else
	417	static void at24_get_ofdata(struct i2c_client *client,
	418	struct at24_platform_data *chip)
	419	{ }
	420	#endif /* CONFIG_OF */
	421
2b7a5056 WS	422	static int at24_probe(struct i2c_client client, const struct i2c_device_id id)
	423	{
	424	struct at24_platform_data chip;
40d8edc9	425	kernel_ulong_t magic = 0;
2b7a5056	426	bool writable;
7aeb9664	427	int use_smbus = 0;
a839ce66	428	int use_smbus_write = 0;
2b7a5056 WS	429	struct at24_data *at24;
	430	int err;
	431	unsigned i, num_addresses;
2b7a5056 WS	432
	433	if (client->dev.platform_data) {
	434	chip = (struct at24_platform_data )client->dev.platform_data;
	435	} else {
40d8edc9 AS	436	if (id) {
	437	magic = id->driver_data;
	438	} else {
	439	const struct acpi_device_id *aid;
	440
	441	aid = acpi_match_device(at24_acpi_ids, &client->dev);
	442	if (aid)
	443	magic = aid->driver_data;
	444	}
	445	if (!magic)
f0ac2363 NB	446	return -ENODEV;
f0ac2363 NB	447
2b7a5056 WS	448	chip.byte_len = BIT(magic & AT24_BITMASK(AT24_SIZE_BYTELEN));
	449	magic >>= AT24_SIZE_BYTELEN;
	450	chip.flags = magic & AT24_BITMASK(AT24_SIZE_FLAGS);
	451	/*
	452	* This is slow, but we can't know all eeproms, so we better
	453	* play safe. Specifying custom eeprom-types via platform_data
	454	* is recommended anyhow.
	455	*/
	456	chip.page_size = 1;
7274ec8b	457
9ed030d7 WS	458	/* update chipdata if OF is present */
	459	at24_get_ofdata(client, &chip);
	460
7274ec8b KH	461	chip.setup = NULL;
7274ec8b KH	462	chip.context = NULL;
2b7a5056 WS	463	}
	464
	465	if (!is_power_of_2(chip.byte_len))
	466	dev_warn(&client->dev,
	467	"byte_len looks suspicious (no power of 2)!\n");
45efe847 WS	468	if (!chip.page_size) {
45efe847 WS	469	dev_err(&client->dev, "page_size must not be 0!\n");
f0ac2363	470	return -EINVAL;
45efe847	471	}
2b7a5056 WS	472	if (!is_power_of_2(chip.page_size))
	473	dev_warn(&client->dev,
	474	"page_size looks suspicious (no power of 2)!\n");
	475
	476	/* Use I2C operations unless we're stuck with SMBus extensions. */
	477	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
f0ac2363 NB	478	if (chip.flags & AT24_FLAG_ADDR16)
	479	return -EPFNOSUPPORT;
	480
7aeb9664	481	if (i2c_check_functionality(client->adapter,
2b7a5056	482	I2C_FUNC_SMBUS_READ_I2C_BLOCK)) {
7aeb9664 JD	483	use_smbus = I2C_SMBUS_I2C_BLOCK_DATA;
	484	} else if (i2c_check_functionality(client->adapter,
	485	I2C_FUNC_SMBUS_READ_WORD_DATA)) {
	486	use_smbus = I2C_SMBUS_WORD_DATA;
	487	} else if (i2c_check_functionality(client->adapter,
	488	I2C_FUNC_SMBUS_READ_BYTE_DATA)) {
	489	use_smbus = I2C_SMBUS_BYTE_DATA;
	490	} else {
f0ac2363	491	return -EPFNOSUPPORT;
2b7a5056	492	}
2b7a5056	493
a839ce66 CG	494	if (i2c_check_functionality(client->adapter,
	495	I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
	496	use_smbus_write = I2C_SMBUS_I2C_BLOCK_DATA;
	497	} else if (i2c_check_functionality(client->adapter,
	498	I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
	499	use_smbus_write = I2C_SMBUS_BYTE_DATA;
	500	chip.page_size = 1;
	501	}
	502	}
	503
2b7a5056 WS	504	if (chip.flags & AT24_FLAG_TAKE8ADDR)
	505	num_addresses = 8;
	506	else
	507	num_addresses = DIV_ROUND_UP(chip.byte_len,
	508	(chip.flags & AT24_FLAG_ADDR16) ? 65536 : 256);
	509
f0ac2363	510	at24 = devm_kzalloc(&client->dev, sizeof(struct at24_data) +
2b7a5056	511	num_addresses * sizeof(struct i2c_client *), GFP_KERNEL);
f0ac2363 NB	512	if (!at24)
f0ac2363 NB	513	return -ENOMEM;
2b7a5056 WS	514
	515	mutex_init(&at24->lock);
	516	at24->use_smbus = use_smbus;
a839ce66	517	at24->use_smbus_write = use_smbus_write;
2b7a5056 WS	518	at24->chip = chip;
	519	at24->num_addresses = num_addresses;
	520
2b7a5056 WS	521	writable = !(chip.flags & AT24_FLAG_READONLY);
2b7a5056 WS	522	if (writable) {
a839ce66	523	if (!use_smbus \|\| use_smbus_write) {
2b7a5056 WS	524
	525	unsigned write_max = chip.page_size;
	526
2b7a5056 WS	527	if (write_max > io_limit)
	528	write_max = io_limit;
	529	if (use_smbus && write_max > I2C_SMBUS_BLOCK_MAX)
	530	write_max = I2C_SMBUS_BLOCK_MAX;
	531	at24->write_max = write_max;
	532
	533	/* buffer (data + address at the beginning) */
f0ac2363 NB	534	at24->writebuf = devm_kzalloc(&client->dev,
	535	write_max + 2, GFP_KERNEL);
	536	if (!at24->writebuf)
	537	return -ENOMEM;
2b7a5056 WS	538	} else {
	539	dev_warn(&client->dev,
	540	"cannot write due to controller restrictions.");
	541	}
	542	}
	543
	544	at24->client[0] = client;
	545
	546	/* use dummy devices for multiple-address chips */
	547	for (i = 1; i < num_addresses; i++) {
	548	at24->client[i] = i2c_new_dummy(client->adapter,
	549	client->addr + i);
	550	if (!at24->client[i]) {
	551	dev_err(&client->dev, "address 0x%02x unavailable\n",
	552	client->addr + i);
	553	err = -EADDRINUSE;
	554	goto err_clients;
	555	}
	556	}
	557
57d15550 AL	558	at24->nvmem_config.name = dev_name(&client->dev);
	559	at24->nvmem_config.dev = &client->dev;
	560	at24->nvmem_config.read_only = !writable;
	561	at24->nvmem_config.root_only = true;
	562	at24->nvmem_config.owner = THIS_MODULE;
	563	at24->nvmem_config.compat = true;
	564	at24->nvmem_config.base_dev = &client->dev;
cf0361a2 SK	565	at24->nvmem_config.reg_read = at24_read;
	566	at24->nvmem_config.reg_write = at24_write;
	567	at24->nvmem_config.priv = at24;
	568	at24->nvmem_config.stride = 4;
	569	at24->nvmem_config.word_size = 1;
	570	at24->nvmem_config.size = chip.byte_len;
57d15550 AL	571
	572	at24->nvmem = nvmem_register(&at24->nvmem_config);
	573
	574	if (IS_ERR(at24->nvmem)) {
	575	err = PTR_ERR(at24->nvmem);
	576	goto err_clients;
	577	}
2b7a5056 WS	578
	579	i2c_set_clientdata(client, at24);
	580
57d15550 AL	581	dev_info(&client->dev, "%u byte %s EEPROM, %s, %u bytes/write\n",
57d15550 AL	582	chip.byte_len, client->name,
9ed030d7	583	writable ? "writable" : "read-only", at24->write_max);
7aeb9664 JD	584	if (use_smbus == I2C_SMBUS_WORD_DATA \|\|
	585	use_smbus == I2C_SMBUS_BYTE_DATA) {
	586	dev_notice(&client->dev, "Falling back to %s reads, "
	587	"performance will suffer\n", use_smbus ==
	588	I2C_SMBUS_WORD_DATA ? "word" : "byte");
	589	}
2b7a5056	590
7274ec8b KH	591	/* export data to kernel code */
7274ec8b KH	592	if (chip.setup)
bec3c11b	593	chip.setup(at24->nvmem, chip.context);
7274ec8b	594
2b7a5056 WS	595	return 0;
	596
	597	err_clients:
	598	for (i = 1; i < num_addresses; i++)
	599	if (at24->client[i])
	600	i2c_unregister_device(at24->client[i]);
	601
2b7a5056 WS	602	return err;
	603	}
	604
486a5c28	605	static int at24_remove(struct i2c_client *client)
2b7a5056 WS	606	{
	607	struct at24_data *at24;
	608	int i;
	609
	610	at24 = i2c_get_clientdata(client);
57d15550 AL	611
57d15550 AL	612	nvmem_unregister(at24->nvmem);
2b7a5056 WS	613
	614	for (i = 1; i < at24->num_addresses; i++)
	615	i2c_unregister_device(at24->client[i]);
	616
2b7a5056 WS	617	return 0;
	618	}
	619
	620	/-------------------------------------------------------------------------/
	621
	622	static struct i2c_driver at24_driver = {
	623	.driver = {
	624	.name = "at24",
40d8edc9	625	.acpi_match_table = ACPI_PTR(at24_acpi_ids),
2b7a5056 WS	626	},
2b7a5056 WS	627	.probe = at24_probe,
2d6bed9c	628	.remove = at24_remove,
2b7a5056 WS	629	.id_table = at24_ids,
	630	};
	631
	632	static int __init at24_init(void)
	633	{
45efe847 WS	634	if (!io_limit) {
	635	pr_err("at24: io_limit must not be 0!\n");
	636	return -EINVAL;
	637	}
	638
2b7a5056 WS	639	io_limit = rounddown_pow_of_two(io_limit);
	640	return i2c_add_driver(&at24_driver);
	641	}
	642	module_init(at24_init);
	643
	644	static void __exit at24_exit(void)
	645	{
	646	i2c_del_driver(&at24_driver);
	647	}
	648	module_exit(at24_exit);
	649
	650	MODULE_DESCRIPTION("Driver for most I2C EEPROMs");
	651	MODULE_AUTHOR("David Brownell and Wolfram Sang");
	652	MODULE_LICENSE("GPL");