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cxl: Wrap iterations over afu slices inside 'afu_list_lock'
[linux-2.6-block.git] / drivers / misc / cxl / pci.c
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/pci_regs.h>
11#include <linux/pci_ids.h>
12#include <linux/device.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/sort.h>
17#include <linux/pci.h>
18#include <linux/of.h>
19#include <linux/delay.h>
20#include <asm/opal.h>
21#include <asm/msi_bitmap.h>
f204e0b8 22#include <asm/pnv-pci.h>
62fa19d4 23#include <asm/io.h>
aa14138a 24#include <asm/reg.h>
f204e0b8
IM		 25
26#include "cxl.h"
9e8df8a2 27#include <misc/cxl.h>
f204e0b8
IM		 28
29
30#define CXL_PCI_VSEC_ID 0x1280
31#define CXL_VSEC_MIN_SIZE 0x80
32
33#define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
34 { \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
36 *dest >>= 4; \
37 }
38#define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
40
41#define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43#define CXL_STATUS_SECOND_PORT 0x80
44#define CXL_STATUS_MSI_X_FULL 0x40
45#define CXL_STATUS_MSI_X_SINGLE 0x20
46#define CXL_STATUS_FLASH_RW 0x08
47#define CXL_STATUS_FLASH_RO 0x04
48#define CXL_STATUS_LOADABLE_AFU 0x02
49#define CXL_STATUS_LOADABLE_PSL 0x01
50/* If we see these features we won't try to use the card */
51#define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54#define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56#define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
58#define CXL_VSEC_PROTOCOL_MASK 0xe0
59#define CXL_VSEC_PROTOCOL_1024TB 0x80
60#define CXL_VSEC_PROTOCOL_512TB 0x40
f24be42a 61#define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
f204e0b8
IM		 62#define CXL_VSEC_PROTOCOL_ENABLE 0x01
63
64#define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
65 pci_read_config_word(dev, vsec + 0xc, dest)
66#define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
67 pci_read_config_byte(dev, vsec + 0xe, dest)
68#define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xf, dest)
70#define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
71 pci_read_config_word(dev, vsec + 0x10, dest)
72
73#define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
74 pci_read_config_byte(dev, vsec + 0x13, dest)
75#define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
76 pci_write_config_byte(dev, vsec + 0x13, val)
77#define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
78#define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
79#define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
80
81#define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
82 pci_read_config_dword(dev, vsec + 0x20, dest)
83#define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x24, dest)
85#define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x28, dest)
87#define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x2c, dest)
89
90
91/* This works a little different than the p1/p2 register accesses to make it
92 * easier to pull out individual fields */
cbffa3a5
CL		 93#define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
94#define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
f204e0b8
IM		 95#define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
96#define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
97
98#define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
99#define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
100#define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
101#define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
102#define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
103#define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
104#define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
105#define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
106#define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
107#define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
108#define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
109#define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
110#define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
111#define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
112#define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
113#define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
114#define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
115#define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
116#define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
117#define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
118
f47f966f 119static const struct pci_device_id cxl_pci_tbl[] = {
f204e0b8
IM		 120 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
121 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
68adb7bf 123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
41e20d95
MO		 124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
f204e0b8
IM		 126 { }
127};
128MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
129
130
131/*
132 * Mostly using these wrappers to avoid confusion:
133 * priv 1 is BAR2, while priv 2 is BAR0
134 */
135static inline resource_size_t p1_base(struct pci_dev *dev)
136{
137 return pci_resource_start(dev, 2);
138}
139
140static inline resource_size_t p1_size(struct pci_dev *dev)
141{
142 return pci_resource_len(dev, 2);
143}
144
145static inline resource_size_t p2_base(struct pci_dev *dev)
146{
147 return pci_resource_start(dev, 0);
148}
149
150static inline resource_size_t p2_size(struct pci_dev *dev)
151{
152 return pci_resource_len(dev, 0);
153}
154
155static int find_cxl_vsec(struct pci_dev *dev)
156{
157 int vsec = 0;
158 u16 val;
159
160 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
161 pci_read_config_word(dev, vsec + 0x4, &val);
162 if (val == CXL_PCI_VSEC_ID)
163 return vsec;
164 }
165 return 0;
166
167}
168
169static void dump_cxl_config_space(struct pci_dev *dev)
170{
171 int vsec;
172 u32 val;
173
174 dev_info(&dev->dev, "dump_cxl_config_space\n");
175
176 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
177 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
179 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
181 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
183 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
185 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
187 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
188
189 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
190 p1_base(dev), p1_size(dev));
191 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
f2931069 192 p2_base(dev), p2_size(dev));
f204e0b8
IM		 193 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
194 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
195
196 if (!(vsec = find_cxl_vsec(dev)))
197 return;
198
199#define show_reg(name, what) \
200 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
201
202 pci_read_config_dword(dev, vsec + 0x0, &val);
203 show_reg("Cap ID", (val >> 0) & 0xffff);
204 show_reg("Cap Ver", (val >> 16) & 0xf);
205 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
206 pci_read_config_dword(dev, vsec + 0x4, &val);
207 show_reg("VSEC ID", (val >> 0) & 0xffff);
208 show_reg("VSEC Rev", (val >> 16) & 0xf);
209 show_reg("VSEC Length", (val >> 20) & 0xfff);
210 pci_read_config_dword(dev, vsec + 0x8, &val);
211 show_reg("Num AFUs", (val >> 0) & 0xff);
212 show_reg("Status", (val >> 8) & 0xff);
213 show_reg("Mode Control", (val >> 16) & 0xff);
214 show_reg("Reserved", (val >> 24) & 0xff);
215 pci_read_config_dword(dev, vsec + 0xc, &val);
216 show_reg("PSL Rev", (val >> 0) & 0xffff);
217 show_reg("CAIA Ver", (val >> 16) & 0xffff);
218 pci_read_config_dword(dev, vsec + 0x10, &val);
219 show_reg("Base Image Rev", (val >> 0) & 0xffff);
220 show_reg("Reserved", (val >> 16) & 0x0fff);
221 show_reg("Image Control", (val >> 28) & 0x3);
222 show_reg("Reserved", (val >> 30) & 0x1);
223 show_reg("Image Loaded", (val >> 31) & 0x1);
224
225 pci_read_config_dword(dev, vsec + 0x14, &val);
226 show_reg("Reserved", val);
227 pci_read_config_dword(dev, vsec + 0x18, &val);
228 show_reg("Reserved", val);
229 pci_read_config_dword(dev, vsec + 0x1c, &val);
230 show_reg("Reserved", val);
231
232 pci_read_config_dword(dev, vsec + 0x20, &val);
233 show_reg("AFU Descriptor Offset", val);
234 pci_read_config_dword(dev, vsec + 0x24, &val);
235 show_reg("AFU Descriptor Size", val);
236 pci_read_config_dword(dev, vsec + 0x28, &val);
237 show_reg("Problem State Offset", val);
238 pci_read_config_dword(dev, vsec + 0x2c, &val);
239 show_reg("Problem State Size", val);
240
241 pci_read_config_dword(dev, vsec + 0x30, &val);
242 show_reg("Reserved", val);
243 pci_read_config_dword(dev, vsec + 0x34, &val);
244 show_reg("Reserved", val);
245 pci_read_config_dword(dev, vsec + 0x38, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x3c, &val);
248 show_reg("Reserved", val);
249
250 pci_read_config_dword(dev, vsec + 0x40, &val);
251 show_reg("PSL Programming Port", val);
252 pci_read_config_dword(dev, vsec + 0x44, &val);
253 show_reg("PSL Programming Control", val);
254
255 pci_read_config_dword(dev, vsec + 0x48, &val);
256 show_reg("Reserved", val);
257 pci_read_config_dword(dev, vsec + 0x4c, &val);
258 show_reg("Reserved", val);
259
260 pci_read_config_dword(dev, vsec + 0x50, &val);
261 show_reg("Flash Address Register", val);
262 pci_read_config_dword(dev, vsec + 0x54, &val);
263 show_reg("Flash Size Register", val);
264 pci_read_config_dword(dev, vsec + 0x58, &val);
265 show_reg("Flash Status/Control Register", val);
266 pci_read_config_dword(dev, vsec + 0x58, &val);
267 show_reg("Flash Data Port", val);
268
269#undef show_reg
270}
271
272static void dump_afu_descriptor(struct cxl_afu *afu)
273{
bfcdc8ff
MN		 274 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
275 int i;
f204e0b8
IM		 276
277#define show_reg(name, what) \
278 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
279
280 val = AFUD_READ_INFO(afu);
281 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
282 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
283 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
284 show_reg("req_prog_mode", val & 0xffffULL);
bfcdc8ff 285 afu_cr_num = AFUD_NUM_CRS(val);
f204e0b8
IM		 286
287 val = AFUD_READ(afu, 0x8);
288 show_reg("Reserved", val);
289 val = AFUD_READ(afu, 0x10);
290 show_reg("Reserved", val);
291 val = AFUD_READ(afu, 0x18);
292 show_reg("Reserved", val);
293
294 val = AFUD_READ_CR(afu);
295 show_reg("Reserved", (val >> (63-7)) & 0xff);
296 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
bfcdc8ff 297 afu_cr_len = AFUD_CR_LEN(val) * 256;
f204e0b8
IM		 298
299 val = AFUD_READ_CR_OFF(afu);
bfcdc8ff 300 afu_cr_off = val;
f204e0b8
IM		 301 show_reg("AFU_CR_offset", val);
302
303 val = AFUD_READ_PPPSA(afu);
304 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
305 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
306
307 val = AFUD_READ_PPPSA_OFF(afu);
308 show_reg("PerProcessPSA_offset", val);
309
310 val = AFUD_READ_EB(afu);
311 show_reg("Reserved", (val >> (63-7)) & 0xff);
312 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
313
314 val = AFUD_READ_EB_OFF(afu);
315 show_reg("AFU_EB_offset", val);
316
bfcdc8ff
MN		 317 for (i = 0; i < afu_cr_num; i++) {
318 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
319 show_reg("CR Vendor", val & 0xffff);
320 show_reg("CR Device", (val >> 16) & 0xffff);
321 }
f204e0b8
IM		 322#undef show_reg
323}
324
abd1d99b
CL		 325#define P8_CAPP_UNIT0_ID 0xBA
326#define P8_CAPP_UNIT1_ID 0XBE
f24be42a
CL		 327#define P9_CAPP_UNIT0_ID 0xC0
328#define P9_CAPP_UNIT1_ID 0xE0
aa14138a 329
f24be42a 330static int get_phb_index(struct device_node *np, u32 *phb_index)
aa14138a 331{
f24be42a
CL		 332 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
333 return -ENODEV;
334 return 0;
335}
aa14138a 336
f24be42a
CL		 337static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
338{
aa14138a 339 /*
abd1d99b
CL		 340 * POWER 8:
341 * - For chips other than POWER8NVL, we only have CAPP 0,
342 * irrespective of which PHB is used.
343 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
344 * CAPP 1 is attached to PHB1.
aa14138a 345 */
abd1d99b
CL		 346 if (cxl_is_power8()) {
347 if (!pvr_version_is(PVR_POWER8NVL))
348 return P8_CAPP_UNIT0_ID;
aa14138a 349
abd1d99b
CL		 350 if (phb_index == 0)
351 return P8_CAPP_UNIT0_ID;
aa14138a 352
abd1d99b
CL		 353 if (phb_index == 1)
354 return P8_CAPP_UNIT1_ID;
355 }
aa14138a
PB		 356
357 /*
f24be42a
CL		 358 * POWER 9:
359 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
360 * PEC1 (PHB1 - PHB2). No capi mode
361 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
aa14138a 362 */
f24be42a
CL		 363 if (cxl_is_power9()) {
364 if (phb_index == 0)
365 return P9_CAPP_UNIT0_ID;
aa14138a 366
f24be42a
CL		 367 if (phb_index == 3)
368 return P9_CAPP_UNIT1_ID;
369 }
aa14138a
PB		 370
371 return 0;
372}
373
3ced8d73 374int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
f24be42a 375 u32 *phb_index, u64 *capp_unit_id)
f204e0b8 376{
f24be42a 377 int rc;
f204e0b8
IM		 378 struct device_node *np;
379 const __be32 *prop;
f204e0b8 380
6f963ec2 381 if (!(np = pnv_pci_get_phb_node(dev)))
f204e0b8
IM		 382 return -ENODEV;
383
384 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
385 np = of_get_next_parent(np);
386 if (!np)
387 return -ENODEV;
f24be42a 388
6d382616 389 *chipid = be32_to_cpup(prop);
f24be42a
CL		 390
391 rc = get_phb_index(np, phb_index);
392 if (rc) {
393 pr_err("cxl: invalid phb index\n");
394 return rc;
395 }
396
397 *capp_unit_id = get_capp_unit_id(np, *phb_index);
f204e0b8 398 of_node_put(np);
6d382616 399 if (!*capp_unit_id) {
56328743
CL		 400 pr_err("cxl: invalid capp unit id (phb_index: %d)\n",
401 *phb_index);
aa14138a
PB		 402 return -ENODEV;
403 }
f204e0b8 404
6d382616
FB		 405 return 0;
406}
407
9dbcbfa1
PB		 408static DEFINE_MUTEX(indications_mutex);
409
410static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
411 u64 *nbwind)
412{
413 static u64 nbw, asn, capi = 0;
414 struct device_node *np;
415 const __be32 *prop;
416
417 mutex_lock(&indications_mutex);
418 if (!capi) {
419 if (!(np = pnv_pci_get_phb_node(dev))) {
420 mutex_unlock(&indications_mutex);
421 return -ENODEV;
422 }
423
424 prop = of_get_property(np, "ibm,phb-indications", NULL);
425 if (!prop) {
426 nbw = 0x0300UL; /* legacy values */
427 asn = 0x0400UL;
428 capi = 0x0200UL;
429 } else {
430 nbw = (u64)be32_to_cpu(prop[2]);
431 asn = (u64)be32_to_cpu(prop[1]);
432 capi = (u64)be32_to_cpu(prop[0]);
433 }
434 of_node_put(np);
435 }
436 *capiind = capi;
437 *asnind = asn;
438 *nbwind = nbw;
439 mutex_unlock(&indications_mutex);
440 return 0;
441}
442
443int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
f24be42a 444{
3ced8d73 445 u64 xsl_dsnctl;
9dbcbfa1 446 u64 capiind, asnind, nbwind;
f24be42a
CL		 447
448 /*
449 * CAPI Identifier bits [0:7]
450 * bit 61:60 MSI bits --> 0
451 * bit 59 TVT selector --> 0
452 */
9dbcbfa1
PB		 453 if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
454 return -ENODEV;
f24be42a
CL		 455
456 /*
457 * Tell XSL where to route data to.
458 * The field chipid should match the PHB CAPI_CMPM register
459 */
9dbcbfa1 460 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
f24be42a
CL		 461 xsl_dsnctl |= (capp_unit_id << (63-15));
462
463 /* nMMU_ID Defaults to: b’000001001’*/
464 xsl_dsnctl |= ((u64)0x09 << (63-28));
465
2bf1071a
NP		 466 /*
467 * Used to identify CAPI packets which should be sorted into
468 * the Non-Blocking queues by the PHB. This field should match
469 * the PHB PBL_NBW_CMPM register
470 * nbwind=0x03, bits [57:58], must include capi indicator.
471 * Not supported on P9 DD1.
472 */
473 xsl_dsnctl |= (nbwind << (63-55));
474
475 /*
476 * Upper 16b address bits of ASB_Notify messages sent to the
477 * system. Need to match the PHB’s ASN Compare/Mask Register.
478 * Not supported on P9 DD1.
479 */
480 xsl_dsnctl |= asnind;
f24be42a 481
3ced8d73
CL		 482 *reg = xsl_dsnctl;
483 return 0;
484}
485
486static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
487 struct pci_dev *dev)
488{
489 u64 xsl_dsnctl, psl_fircntl;
490 u64 chipid;
491 u32 phb_index;
492 u64 capp_unit_id;
94322ed8 493 u64 psl_debug;
3ced8d73
CL		 494 int rc;
495
496 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
497 if (rc)
498 return rc;
499
9dbcbfa1 500 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
3ced8d73
CL		 501 if (rc)
502 return rc;
503
f24be42a
CL		 504 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
505
506 /* Set fir_cntl to recommended value for production env */
507 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
508 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
509 psl_fircntl |= 0x1ULL; /* ce_thresh */
510 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
511
56328743 512 /* Setup the PSL to transmit packets on the PCIe before the
9a6d2022 513 * CAPP is enabled. Make sure that CAPP virtual machines are disabled
f24be42a 514 */
9a6d2022 515 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
f24be42a
CL		 516
517 /*
518 * A response to an ASB_Notify request is returned by the
519 * system as an MMIO write to the address defined in
56328743
CL		 520 * the PSL_TNR_ADDR register.
521 * keep the Reset Value: 0x00020000E0000000
f24be42a 522 */
f24be42a 523
56328743
CL		 524 /* Enable XSL rty limit */
525 cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
526
527 /* Change XSL_INV dummy read threshold */
528 cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
529
530 if (phb_index == 3) {
531 /* disable machines 31-47 and 20-27 for DMA */
532 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
533 }
f24be42a 534
56328743
CL		 535 /* Snoop machines */
536 cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
f24be42a 537
2bf1071a
NP		 538 /* Enable NORST and DD2 features */
539 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
f24be42a 540
94322ed8
VJ		 541 /*
542 * Check if PSL has data-cache. We need to flush adapter datacache
543 * when as its about to be removed.
544 */
545 psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
546 if (psl_debug & CXL_PSL_DEBUG_CDC) {
547 dev_dbg(&dev->dev, "No data-cache present\n");
548 adapter->native->no_data_cache = true;
549 }
550
f24be42a
CL		 551 return 0;
552}
553
64663f37 554static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
6d382616 555{
c6d2ee09 556 u64 psl_dsnctl, psl_fircntl;
6d382616 557 u64 chipid;
f24be42a 558 u32 phb_index;
6d382616
FB		 559 u64 capp_unit_id;
560 int rc;
561
3ced8d73 562 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
6d382616
FB		 563 if (rc)
564 return rc;
565
4aec6ec0
FB		 566 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
567 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
f204e0b8 568 /* Tell PSL where to route data to */
4aec6ec0 569 psl_dsnctl |= (chipid << (63-5));
aa14138a
PB		 570 psl_dsnctl |= (capp_unit_id << (63-13));
571
f204e0b8
IM		 572 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
573 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
574 /* snoop write mask */
575 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
c6d2ee09
FB		 576 /* set fir_cntl to recommended value for production env */
577 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
578 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
579 psl_fircntl |= 0x1ULL; /* ce_thresh */
580 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
f204e0b8
IM		 581 /* for debugging with trace arrays */
582 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
583
584 return 0;
585}
586
f3988ca4 587/* PSL */
6d382616 588#define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
390fd592 589#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
6d382616
FB		 590/* For the PSL this is a multiple for 0 < n <= 7: */
591#define PSL_2048_250MHZ_CYCLES 1
592
64663f37 593static void write_timebase_ctrl_psl8(struct cxl *adapter)
6d382616
FB		 594{
595 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
596 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
597}
598
f24be42a
CL		 599static u64 timebase_read_psl9(struct cxl *adapter)
600{
601 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
602}
603
64663f37 604static u64 timebase_read_psl8(struct cxl *adapter)
6d382616
FB		 605{
606 return cxl_p1_read(adapter, CXL_PSL_Timebase);
607}
608
e009a7e8 609static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
390fd592 610{
390fd592
PB		 611 struct device_node *np;
612
e009a7e8
FB		 613 adapter->psl_timebase_synced = false;
614
390fd592 615 if (!(np = pnv_pci_get_phb_node(dev)))
e009a7e8 616 return;
390fd592
PB		 617
618 /* Do not fail when CAPP timebase sync is not supported by OPAL */
619 of_node_get(np);
620 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
621 of_node_put(np);
e009a7e8
FB		 622 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
623 return;
390fd592
PB		 624 }
625 of_node_put(np);
626
627 /*
628 * Setup PSL Timebase Control and Status register
629 * with the recommended Timebase Sync Count value
630 */
02b63b42
VJ		 631 if (adapter->native->sl_ops->write_timebase_ctrl)
632 adapter->native->sl_ops->write_timebase_ctrl(adapter);
390fd592
PB		 633
634 /* Enable PSL Timebase */
635 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
636 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
637
e009a7e8 638 return;
390fd592
PB		 639}
640
f24be42a
CL		 641static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
642{
643 return 0;
644}
645
64663f37 646static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
f204e0b8
IM		 647{
648 /* read/write masks for this slice */
649 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
650 /* APC read/write masks for this slice */
651 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
652 /* for debugging with trace arrays */
653 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
d6a6af2c 654 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
f204e0b8
IM		 655
656 return 0;
657}
658
2b04cf31
FB		 659int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
660 unsigned int virq)
f204e0b8
IM		 661{
662 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
663
664 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
665}
666
4beb5421
RG		 667int cxl_update_image_control(struct cxl *adapter)
668{
669 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
670 int rc;
671 int vsec;
672 u8 image_state;
673
674 if (!(vsec = find_cxl_vsec(dev))) {
675 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
676 return -ENODEV;
677 }
678
679 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
680 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
681 return rc;
682 }
683
684 if (adapter->perst_loads_image)
685 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
686 else
687 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
688
689 if (adapter->perst_select_user)
690 image_state |= CXL_VSEC_PERST_SELECT_USER;
691 else
692 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
693
694 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
695 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
696 return rc;
697 }
698
699 return 0;
700}
701
2b04cf31 702int cxl_pci_alloc_one_irq(struct cxl *adapter)
f204e0b8
IM		 703{
704 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
705
706 return pnv_cxl_alloc_hwirqs(dev, 1);
707}
708
2b04cf31 709void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
f204e0b8
IM		 710{
711 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
712
713 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
714}
715
2b04cf31
FB		 716int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
717 struct cxl *adapter, unsigned int num)
f204e0b8
IM		 718{
719 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
720
721 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
722}
723
2b04cf31
FB		 724void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
725 struct cxl *adapter)
f204e0b8
IM		 726{
727 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
728
729 pnv_cxl_release_hwirq_ranges(irqs, dev);
730}
731
732static int setup_cxl_bars(struct pci_dev *dev)
733{
734 /* Safety check in case we get backported to < 3.17 without M64 */
735 if ((p1_base(dev) < 0x100000000ULL) ||
736 (p2_base(dev) < 0x100000000ULL)) {
737 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
738 return -ENODEV;
739 }
740
741 /*
742 * BAR 4/5 has a special meaning for CXL and must be programmed with a
743 * special value corresponding to the CXL protocol address range.
f24be42a 744 * For POWER 8/9 that means bits 48:49 must be set to 10
f204e0b8
IM		 745 */
746 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
747 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
748
749 return 0;
750}
751
29fea8aa
AS		 752/* pciex node: ibm,opal-m64-window = <0x3d058 0x0 0x3d058 0x0 0x8 0x0>; */
753static int switch_card_to_cxl(struct pci_dev *dev)
b0b5e591 754{
29fea8aa 755 int vsec;
f204e0b8
IM		 756 u8 val;
757 int rc;
758
29fea8aa 759 dev_info(&dev->dev, "switch card to CXL\n");
b0b5e591 760
29fea8aa
AS		 761 if (!(vsec = find_cxl_vsec(dev))) {
762 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
f204e0b8
IM		 763 return -ENODEV;
764 }
765
29fea8aa
AS		 766 if ((rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val))) {
767 dev_err(&dev->dev, "failed to read current mode control: %i", rc);
f204e0b8
IM		 768 return rc;
769 }
29fea8aa
AS		 770 val &= ~CXL_VSEC_PROTOCOL_MASK;
771 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
772 if ((rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val))) {
773 dev_err(&dev->dev, "failed to enable CXL protocol: %i", rc);
774 return rc;
b0b5e591 775 }
f204e0b8 776 /*
29fea8aa
AS		 777 * The CAIA spec (v0.12 11.6 Bi-modal Device Support) states
778 * we must wait 100ms after this mode switch before touching
779 * PCIe config space.
f204e0b8 780 */
29fea8aa 781 msleep(100);
f204e0b8
IM		 782
783 return 0;
784}
785
2b04cf31 786static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
f204e0b8
IM		 787{
788 u64 p1n_base, p2n_base, afu_desc;
789 const u64 p1n_size = 0x100;
790 const u64 p2n_size = 0x1000;
791
792 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
793 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
cbffa3a5
CL		 794 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
795 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
f204e0b8 796
cbffa3a5 797 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
f204e0b8
IM		 798 goto err;
799 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
800 goto err1;
801 if (afu_desc) {
cbffa3a5 802 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
f204e0b8
IM		 803 goto err2;
804 }
805
806 return 0;
807err2:
808 iounmap(afu->p2n_mmio);
809err1:
cbffa3a5 810 iounmap(afu->native->p1n_mmio);
f204e0b8
IM		 811err:
812 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
813 return -ENOMEM;
814}
815
2b04cf31 816static void pci_unmap_slice_regs(struct cxl_afu *afu)
f204e0b8 817{
575e6986 818 if (afu->p2n_mmio) {
f204e0b8 819 iounmap(afu->p2n_mmio);
575e6986
DA		 820 afu->p2n_mmio = NULL;
821 }
cbffa3a5
CL		 822 if (afu->native->p1n_mmio) {
823 iounmap(afu->native->p1n_mmio);
824 afu->native->p1n_mmio = NULL;
575e6986 825 }
cbffa3a5
CL		 826 if (afu->native->afu_desc_mmio) {
827 iounmap(afu->native->afu_desc_mmio);
828 afu->native->afu_desc_mmio = NULL;
575e6986 829 }
f204e0b8
IM		 830}
831
2b04cf31 832void cxl_pci_release_afu(struct device *dev)
f204e0b8
IM		 833{
834 struct cxl_afu *afu = to_cxl_afu(dev);
835
2b04cf31 836 pr_devel("%s\n", __func__);
f204e0b8 837
bd664f89 838 idr_destroy(&afu->contexts_idr);
05155772
DA		 839 cxl_release_spa(afu);
840
cbffa3a5 841 kfree(afu->native);
f204e0b8
IM		 842 kfree(afu);
843}
844
f204e0b8
IM		 845/* Expects AFU struct to have recently been zeroed out */
846static int cxl_read_afu_descriptor(struct cxl_afu *afu)
847{
848 u64 val;
849
850 val = AFUD_READ_INFO(afu);
851 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
852 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
b087e619 853 afu->crs_num = AFUD_NUM_CRS(val);
f204e0b8
IM		 854
855 if (AFUD_AFU_DIRECTED(val))
856 afu->modes_supported |= CXL_MODE_DIRECTED;
857 if (AFUD_DEDICATED_PROCESS(val))
858 afu->modes_supported |= CXL_MODE_DEDICATED;
859 if (AFUD_TIME_SLICED(val))
860 afu->modes_supported |= CXL_MODE_TIME_SLICED;
861
862 val = AFUD_READ_PPPSA(afu);
863 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
864 afu->psa = AFUD_PPPSA_PSA(val);
865 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
cbffa3a5 866 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
f204e0b8 867
b087e619
IM		 868 val = AFUD_READ_CR(afu);
869 afu->crs_len = AFUD_CR_LEN(val) * 256;
870 afu->crs_offset = AFUD_READ_CR_OFF(afu);
871
e36f6fe1
VJ		 872
873 /* eb_len is in multiple of 4K */
874 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
875 afu->eb_offset = AFUD_READ_EB_OFF(afu);
876
877 /* eb_off is 4K aligned so lower 12 bits are always zero */
878 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
879 dev_warn(&afu->dev,
880 "Invalid AFU error buffer offset %Lx\n",
881 afu->eb_offset);
882 dev_info(&afu->dev,
883 "Ignoring AFU error buffer in the descriptor\n");
884 /* indicate that no afu buffer exists */
885 afu->eb_len = 0;
886 }
887
f204e0b8
IM		 888 return 0;
889}
890
891static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
892{
5be587b1
FB		 893 int i, rc;
894 u32 val;
3d5be039 895
f204e0b8 896 if (afu->psa && afu->adapter->ps_size <
cbffa3a5 897 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
f204e0b8
IM		 898 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
899 return -ENODEV;
900 }
901
902 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
abd1d99b 903 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
f204e0b8 904
3d5be039 905 for (i = 0; i < afu->crs_num; i++) {
5be587b1
FB		 906 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
907 if (rc || val == 0) {
3d5be039
IM		 908 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
909 return -EINVAL;
910 }
911 }
49e9c99f
IM		 912
913 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
914 /*
915 * We could also check this for the dedicated process model
916 * since the architecture indicates it should be set to 1, but
917 * in that case we ignore the value and I'd rather not risk
918 * breaking any existing dedicated process AFUs that left it as
919 * 0 (not that I'm aware of any). It is clearly an error for an
920 * AFU directed AFU to set this to 0, and would have previously
921 * triggered a bug resulting in the maximum not being enforced
922 * at all since idr_alloc treats 0 as no maximum.
923 */
924 dev_err(&afu->dev, "AFU does not support any processes\n");
925 return -EINVAL;
926 }
3d5be039 927
f204e0b8
IM		 928 return 0;
929}
930
f24be42a
CL		 931static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
932{
933 u64 reg;
934
935 /*
936 * Clear out any regs that contain either an IVTE or address or may be
937 * waiting on an acknowledgment to try to be a bit safer as we bring
938 * it online
939 */
940 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
941 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
942 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
943 if (cxl_ops->afu_reset(afu))
944 return -EIO;
945 if (cxl_afu_disable(afu))
946 return -EIO;
947 if (cxl_psl_purge(afu))
948 return -EIO;
949 }
950 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
951 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
952 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
953 if (reg) {
954 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
955 if (reg & CXL_PSL9_DSISR_An_TF)
956 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
957 else
958 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
959 }
960 if (afu->adapter->native->sl_ops->register_serr_irq) {
961 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
962 if (reg) {
963 if (reg & ~0x000000007fffffff)
964 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
965 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
966 }
967 }
968 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
969 if (reg) {
970 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
971 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
972 }
973
974 return 0;
975}
976
64663f37 977static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
f204e0b8
IM		 978{
979 u64 reg;
980
981 /*
982 * Clear out any regs that contain either an IVTE or address or may be
983 * waiting on an acknowledgement to try to be a bit safer as we bring
984 * it online
985 */
986 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
987 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
de369538 988 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
5be587b1 989 if (cxl_ops->afu_reset(afu))
f204e0b8
IM		 990 return -EIO;
991 if (cxl_afu_disable(afu))
992 return -EIO;
993 if (cxl_psl_purge(afu))
994 return -EIO;
995 }
996 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
997 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
998 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
999 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1000 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1001 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1002 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1003 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1004 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1005 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1006 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1007 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1008 if (reg) {
de369538 1009 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
f204e0b8
IM		 1010 if (reg & CXL_PSL_DSISR_TRANS)
1011 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1012 else
1013 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1014 }
6d382616
FB		 1015 if (afu->adapter->native->sl_ops->register_serr_irq) {
1016 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1017 if (reg) {
1018 if (reg & ~0xffff)
1019 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1020 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1021 }
f204e0b8
IM		 1022 }
1023 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1024 if (reg) {
de369538 1025 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
f204e0b8
IM		 1026 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1027 }
1028
1029 return 0;
1030}
1031
e36f6fe1
VJ		 1032#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1033/*
1034 * afu_eb_read:
1035 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1036 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1037 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1038 */
2b04cf31 1039ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
e36f6fe1
VJ		 1040 loff_t off, size_t count)
1041{
1042 loff_t aligned_start, aligned_end;
1043 size_t aligned_length;
1044 void *tbuf;
cbffa3a5 1045 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
e36f6fe1
VJ		 1046
1047 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1048 return 0;
1049
1050 /* calculate aligned read window */
1051 count = min((size_t)(afu->eb_len - off), count);
1052 aligned_start = round_down(off, 8);
1053 aligned_end = round_up(off + count, 8);
1054 aligned_length = aligned_end - aligned_start;
1055
1056 /* max we can copy in one read is PAGE_SIZE */
1057 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1058 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1059 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1060 }
1061
1062 /* use bounce buffer for copy */
0ee931c4 1063 tbuf = (void *)__get_free_page(GFP_KERNEL);
e36f6fe1
VJ		 1064 if (!tbuf)
1065 return -ENOMEM;
1066
1067 /* perform aligned read from the mmio region */
1068 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1069 memcpy(buf, tbuf + (off & 0x7), count);
1070
1071 free_page((unsigned long)tbuf);
1072
1073 return count;
1074}
1075
2b04cf31 1076static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
f204e0b8 1077{
f204e0b8
IM		 1078 int rc;
1079
2b04cf31 1080 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
d76427b0 1081 return rc;
f204e0b8 1082
bdd2e715
CL		 1083 if (adapter->native->sl_ops->sanitise_afu_regs) {
1084 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1085 if (rc)
1086 goto err1;
1087 }
f204e0b8
IM		 1088
1089 /* We need to reset the AFU before we can read the AFU descriptor */
5be587b1 1090 if ((rc = cxl_ops->afu_reset(afu)))
d76427b0 1091 goto err1;
f204e0b8
IM		 1092
1093 if (cxl_verbose)
1094 dump_afu_descriptor(afu);
1095
1096 if ((rc = cxl_read_afu_descriptor(afu)))
d76427b0 1097 goto err1;
f204e0b8
IM		 1098
1099 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
d76427b0 1100 goto err1;
f204e0b8 1101
6d382616
FB		 1102 if (adapter->native->sl_ops->afu_regs_init)
1103 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1104 goto err1;
f204e0b8 1105
6d382616
FB		 1106 if (adapter->native->sl_ops->register_serr_irq)
1107 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1108 goto err1;
f204e0b8 1109
2b04cf31 1110 if ((rc = cxl_native_register_psl_irq(afu)))
d76427b0
DA		 1111 goto err2;
1112
171ed0fc 1113 atomic_set(&afu->configured_state, 0);
d76427b0
DA		 1114 return 0;
1115
1116err2:
6d382616
FB		 1117 if (adapter->native->sl_ops->release_serr_irq)
1118 adapter->native->sl_ops->release_serr_irq(afu);
d76427b0 1119err1:
2b04cf31 1120 pci_unmap_slice_regs(afu);
d76427b0
DA		 1121 return rc;
1122}
1123
2b04cf31 1124static void pci_deconfigure_afu(struct cxl_afu *afu)
d76427b0 1125{
171ed0fc
AD		 1126 /*
1127 * It's okay to deconfigure when AFU is already locked, otherwise wait
1128 * until there are no readers
1129 */
1130 if (atomic_read(&afu->configured_state) != -1) {
1131 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1132 schedule();
1133 }
2b04cf31 1134 cxl_native_release_psl_irq(afu);
6d382616
FB		 1135 if (afu->adapter->native->sl_ops->release_serr_irq)
1136 afu->adapter->native->sl_ops->release_serr_irq(afu);
2b04cf31 1137 pci_unmap_slice_regs(afu);
d76427b0
DA		 1138}
1139
2b04cf31 1140static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
d76427b0
DA		 1141{
1142 struct cxl_afu *afu;
cbffa3a5 1143 int rc = -ENOMEM;
d76427b0
DA		 1144
1145 afu = cxl_alloc_afu(adapter, slice);
1146 if (!afu)
1147 return -ENOMEM;
1148
cbffa3a5
CL		 1149 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1150 if (!afu->native)
1151 goto err_free_afu;
1152
1153 mutex_init(&afu->native->spa_mutex);
1154
d76427b0
DA		 1155 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1156 if (rc)
cbffa3a5 1157 goto err_free_native;
d76427b0 1158
2b04cf31 1159 rc = pci_configure_afu(afu, adapter, dev);
d76427b0 1160 if (rc)
cbffa3a5 1161 goto err_free_native;
f204e0b8
IM		 1162
1163 /* Don't care if this fails */
1164 cxl_debugfs_afu_add(afu);
1165
1166 /*
1167 * After we call this function we must not free the afu directly, even
1168 * if it returns an error!
1169 */
1170 if ((rc = cxl_register_afu(afu)))
1171 goto err_put1;
1172
1173 if ((rc = cxl_sysfs_afu_add(afu)))
1174 goto err_put1;
1175
f204e0b8
IM		 1176 adapter->afu[afu->slice] = afu;
1177
6f7f0b3d
MN		 1178 if ((rc = cxl_pci_vphb_add(afu)))
1179 dev_info(&afu->dev, "Can't register vPHB\n");
1180
f204e0b8
IM		 1181 return 0;
1182
f204e0b8 1183err_put1:
2b04cf31 1184 pci_deconfigure_afu(afu);
f204e0b8 1185 cxl_debugfs_afu_remove(afu);
d76427b0 1186 device_unregister(&afu->dev);
f204e0b8 1187 return rc;
d76427b0 1188
cbffa3a5
CL		 1189err_free_native:
1190 kfree(afu->native);
1191err_free_afu:
d76427b0
DA		 1192 kfree(afu);
1193 return rc;
1194
f204e0b8
IM		 1195}
1196
2b04cf31 1197static void cxl_pci_remove_afu(struct cxl_afu *afu)
f204e0b8 1198{
2b04cf31 1199 pr_devel("%s\n", __func__);
f204e0b8
IM		 1200
1201 if (!afu)
1202 return;
1203
d601ea91 1204 cxl_pci_vphb_remove(afu);
f204e0b8
IM		 1205 cxl_sysfs_afu_remove(afu);
1206 cxl_debugfs_afu_remove(afu);
1207
1208 spin_lock(&afu->adapter->afu_list_lock);
1209 afu->adapter->afu[afu->slice] = NULL;
1210 spin_unlock(&afu->adapter->afu_list_lock);
1211
1212 cxl_context_detach_all(afu);
5be587b1 1213 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
f204e0b8 1214
2b04cf31 1215 pci_deconfigure_afu(afu);
f204e0b8
IM		 1216 device_unregister(&afu->dev);
1217}
1218
2b04cf31 1219int cxl_pci_reset(struct cxl *adapter)
62fa19d4
RG		 1220{
1221 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1222 int rc;
62fa19d4 1223
13e68d8b
DA		 1224 if (adapter->perst_same_image) {
1225 dev_warn(&dev->dev,
1226 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1227 return -EINVAL;
1228 }
1229
62fa19d4 1230 dev_info(&dev->dev, "CXL reset\n");
aaa2245e 1231
abd1d99b
CL		 1232 /*
1233 * The adapter is about to be reset, so ignore errors.
abd1d99b 1234 */
94322ed8 1235 cxl_data_cache_flush(adapter);
62fa19d4 1236
62fa19d4
RG		 1237 /* pcie_warm_reset requests a fundamental pci reset which includes a
1238 * PERST assert/deassert. PERST triggers a loading of the image
1239 * if "user" or "factory" is selected in sysfs */
1240 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1241 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1242 return rc;
1243 }
1244
62fa19d4
RG		 1245 return rc;
1246}
f204e0b8
IM		 1247
1248static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1249{
1250 if (pci_request_region(dev, 2, "priv 2 regs"))
1251 goto err1;
1252 if (pci_request_region(dev, 0, "priv 1 regs"))
1253 goto err2;
1254
de369538 1255 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
f204e0b8
IM		 1256 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1257
cbffa3a5 1258 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
f204e0b8
IM		 1259 goto err3;
1260
cbffa3a5 1261 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
f204e0b8
IM		 1262 goto err4;
1263
1264 return 0;
1265
1266err4:
cbffa3a5
CL		 1267 iounmap(adapter->native->p1_mmio);
1268 adapter->native->p1_mmio = NULL;
f204e0b8
IM		 1269err3:
1270 pci_release_region(dev, 0);
1271err2:
1272 pci_release_region(dev, 2);
1273err1:
1274 return -ENOMEM;
1275}
1276
1277static void cxl_unmap_adapter_regs(struct cxl *adapter)
1278{
cbffa3a5
CL		 1279 if (adapter->native->p1_mmio) {
1280 iounmap(adapter->native->p1_mmio);
1281 adapter->native->p1_mmio = NULL;
575e6986
DA		 1282 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1283 }
cbffa3a5
CL		 1284 if (adapter->native->p2_mmio) {
1285 iounmap(adapter->native->p2_mmio);
1286 adapter->native->p2_mmio = NULL;
575e6986
DA		 1287 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1288 }
f204e0b8
IM		 1289}
1290
1291static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1292{
1293 int vsec;
1294 u32 afu_desc_off, afu_desc_size;
1295 u32 ps_off, ps_size;
1296 u16 vseclen;
1297 u8 image_state;
1298
1299 if (!(vsec = find_cxl_vsec(dev))) {
bee30c70 1300 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
f204e0b8
IM		 1301 return -ENODEV;
1302 }
1303
1304 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1305 if (vseclen < CXL_VSEC_MIN_SIZE) {
bee30c70 1306 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
f204e0b8
IM		 1307 return -EINVAL;
1308 }
1309
1310 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1311 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1312 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1313 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1314 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1315 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1316 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
4beb5421 1317 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
aba81433 1318 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
f204e0b8
IM		 1319
1320 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1321 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1322 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1323 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1324 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1325
1326 /* Convert everything to bytes, because there is NO WAY I'd look at the
1327 * code a month later and forget what units these are in ;-) */
cbffa3a5 1328 adapter->native->ps_off = ps_off * 64 * 1024;
f204e0b8 1329 adapter->ps_size = ps_size * 64 * 1024;
cbffa3a5
CL		 1330 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1331 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
f204e0b8
IM		 1332
1333 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1334 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1335
1336 return 0;
1337}
1338
d79e6801
PB		 1339/*
1340 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1341 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1342 * reported. Mask this error in the Uncorrectable Error Mask Register.
1343 *
1344 * The upper nibble of the PSL revision is used to distinguish between
1345 * different cards. The affected ones have it set to 0.
1346 */
1347static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1348{
1349 int aer;
1350 u32 data;
1351
1352 if (adapter->psl_rev & 0xf000)
1353 return;
1354 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1355 return;
1356 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1357 if (data & PCI_ERR_UNC_MALF_TLP)
1358 if (data & PCI_ERR_UNC_INTN)
1359 return;
1360 data |= PCI_ERR_UNC_MALF_TLP;
1361 data |= PCI_ERR_UNC_INTN;
1362 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1363}
1364
abd1d99b
CL		 1365static bool cxl_compatible_caia_version(struct cxl *adapter)
1366{
1367 if (cxl_is_power8() && (adapter->caia_major == 1))
1368 return true;
1369
f24be42a
CL		 1370 if (cxl_is_power9() && (adapter->caia_major == 2))
1371 return true;
1372
abd1d99b
CL		 1373 return false;
1374}
1375
f204e0b8
IM		 1376static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1377{
1378 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1379 return -EBUSY;
1380
1381 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
bee30c70 1382 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
f204e0b8
IM		 1383 return -EINVAL;
1384 }
1385
abd1d99b
CL		 1386 if (!cxl_compatible_caia_version(adapter)) {
1387 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1388 adapter->caia_major);
1389 return -ENODEV;
1390 }
1391
f204e0b8
IM		 1392 if (!adapter->slices) {
1393 /* Once we support dynamic reprogramming we can use the card if
1394 * it supports loadable AFUs */
bee30c70 1395 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
f204e0b8
IM		 1396 return -EINVAL;
1397 }
1398
cbffa3a5 1399 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
bee30c70 1400 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
f204e0b8
IM		 1401 return -EINVAL;
1402 }
1403
cbffa3a5 1404 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
bee30c70 1405 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
f204e0b8 1406 "available in BAR2: 0x%llx > 0x%llx\n",
cbffa3a5 1407 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
f204e0b8
IM		 1408 return -EINVAL;
1409 }
1410
1411 return 0;
1412}
1413
d601ea91
FB		 1414ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1415{
1416 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1417}
1418
f204e0b8
IM		 1419static void cxl_release_adapter(struct device *dev)
1420{
1421 struct cxl *adapter = to_cxl_adapter(dev);
1422
1423 pr_devel("cxl_release_adapter\n");
1424
c044c415
DA		 1425 cxl_remove_adapter_nr(adapter);
1426
cbffa3a5 1427 kfree(adapter->native);
f204e0b8
IM		 1428 kfree(adapter);
1429}
1430
390fd592
PB		 1431#define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1432
f204e0b8
IM		 1433static int sanitise_adapter_regs(struct cxl *adapter)
1434{
bdd2e715
CL		 1435 int rc = 0;
1436
390fd592
PB		 1437 /* Clear PSL tberror bit by writing 1 to it */
1438 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
bdd2e715 1439
f24be42a
CL		 1440 if (adapter->native->sl_ops->invalidate_all) {
1441 /* do not invalidate ERAT entries when not reloading on PERST */
1442 if (cxl_is_power9() && (adapter->perst_loads_image))
1443 return 0;
bdd2e715 1444 rc = adapter->native->sl_ops->invalidate_all(adapter);
f24be42a 1445 }
bdd2e715
CL		 1446
1447 return rc;
f204e0b8
IM		 1448}
1449
c044c415
DA		 1450/* This should contain *only* operations that can safely be done in
1451 * both creation and recovery.
1452 */
1453static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
f204e0b8 1454{
f204e0b8
IM		 1455 int rc;
1456
c044c415
DA		 1457 adapter->dev.parent = &dev->dev;
1458 adapter->dev.release = cxl_release_adapter;
1459 pci_set_drvdata(dev, adapter);
f204e0b8 1460
c044c415
DA		 1461 rc = pci_enable_device(dev);
1462 if (rc) {
1463 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1464 return rc;
1465 }
f204e0b8 1466
bee30c70 1467 if ((rc = cxl_read_vsec(adapter, dev)))
c044c415 1468 return rc;
bee30c70
IM		 1469
1470 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
c044c415 1471 return rc;
bee30c70 1472
d79e6801
PB		 1473 cxl_fixup_malformed_tlp(adapter, dev);
1474
bee30c70 1475 if ((rc = setup_cxl_bars(dev)))
c044c415 1476 return rc;
bee30c70 1477
29fea8aa 1478 if ((rc = switch_card_to_cxl(dev)))
c044c415 1479 return rc;
f204e0b8 1480
4beb5421 1481 if ((rc = cxl_update_image_control(adapter)))
c044c415 1482 return rc;
4beb5421 1483
f204e0b8 1484 if ((rc = cxl_map_adapter_regs(adapter, dev)))
c044c415 1485 return rc;
f204e0b8
IM		 1486
1487 if ((rc = sanitise_adapter_regs(adapter)))
c044c415 1488 goto err;
f204e0b8 1489
6d382616 1490 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
c044c415 1491 goto err;
f204e0b8 1492
48b3adf3
IM		 1493 /* Required for devices using CAPP DMA mode, harmless for others */
1494 pci_set_master(dev);
1495
497a0790
PB		 1496 adapter->tunneled_ops_supported = false;
1497
1498 if (cxl_is_power9()) {
401dca8c
PB		 1499 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
1500 dev_info(&dev->dev, "Tunneled operations unsupported\n");
497a0790
PB		 1501 else
1502 adapter->tunneled_ops_supported = true;
1503 }
401dca8c 1504
b385c9e9 1505 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
c044c415 1506 goto err;
f204e0b8 1507
1212aa1c
RG		 1508 /* If recovery happened, the last step is to turn on snooping.
1509 * In the non-recovery case this has no effect */
c044c415
DA		 1510 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1511 goto err;
1212aa1c 1512
e009a7e8
FB		 1513 /* Ignore error, adapter init is not dependant on timebase sync */
1514 cxl_setup_psl_timebase(adapter, dev);
390fd592 1515
2b04cf31 1516 if ((rc = cxl_native_register_psl_err_irq(adapter)))
c044c415
DA		 1517 goto err;
1518
1519 return 0;
1520
1521err:
1522 cxl_unmap_adapter_regs(adapter);
1523 return rc;
1524
1525}
1526
1527static void cxl_deconfigure_adapter(struct cxl *adapter)
1528{
1529 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1530
401dca8c
PB		 1531 if (cxl_is_power9())
1532 pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
1533
2b04cf31 1534 cxl_native_release_psl_err_irq(adapter);
c044c415
DA		 1535 cxl_unmap_adapter_regs(adapter);
1536
1537 pci_disable_device(pdev);
1538}
1539
cbb55eeb
VJ		 1540static void cxl_stop_trace_psl9(struct cxl *adapter)
1541{
1542 int traceid;
1543 u64 trace_state, trace_mask;
1544 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1545
1546 /* read each tracearray state and issue mmio to stop them is needed */
1547 for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
1548 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
1549 trace_mask = (0x3ULL << (62 - traceid * 2));
1550 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1551 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1552 traceid, trace_state);
1553
1554 /* issue mmio if the trace array isn't in FIN state */
1555 if (trace_state != CXL_PSL9_TRACESTATE_FIN)
1556 cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
1557 0x8400000000000000ULL | traceid);
1558 }
1559}
1560
1561static void cxl_stop_trace_psl8(struct cxl *adapter)
1562{
1563 int slice;
1564
1565 /* Stop the trace */
1566 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
1567
1568 /* Stop the slice traces */
1569 spin_lock(&adapter->afu_list_lock);
1570 for (slice = 0; slice < adapter->slices; slice++) {
1571 if (adapter->afu[slice])
1572 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1573 0x8000000000000000LL);
1574 }
1575 spin_unlock(&adapter->afu_list_lock);
1576}
1577
f24be42a
CL		 1578static const struct cxl_service_layer_ops psl9_ops = {
1579 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1580 .invalidate_all = cxl_invalidate_all_psl9,
1581 .afu_regs_init = init_implementation_afu_regs_psl9,
1582 .sanitise_afu_regs = sanitise_afu_regs_psl9,
6d382616
FB		 1583 .register_serr_irq = cxl_native_register_serr_irq,
1584 .release_serr_irq = cxl_native_release_serr_irq,
f24be42a
CL		 1585 .handle_interrupt = cxl_irq_psl9,
1586 .fail_irq = cxl_fail_irq_psl,
1587 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1588 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1589 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1590 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1591 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1592 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1593 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
990f19ae 1594 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
f24be42a 1595 .debugfs_stop_trace = cxl_stop_trace_psl9,
f24be42a
CL		 1596 .timebase_read = timebase_read_psl9,
1597 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1598 .needs_reset_before_disable = true,
1599};
1600
64663f37
CL		 1601static const struct cxl_service_layer_ops psl8_ops = {
1602 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1603 .invalidate_all = cxl_invalidate_all_psl8,
1604 .afu_regs_init = init_implementation_afu_regs_psl8,
1605 .sanitise_afu_regs = sanitise_afu_regs_psl8,
6d382616
FB		 1606 .register_serr_irq = cxl_native_register_serr_irq,
1607 .release_serr_irq = cxl_native_release_serr_irq,
64663f37 1608 .handle_interrupt = cxl_irq_psl8,
bdd2e715 1609 .fail_irq = cxl_fail_irq_psl,
64663f37
CL		 1610 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1611 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1612 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1613 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1614 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1615 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1616 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
990f19ae 1617 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
64663f37
CL		 1618 .debugfs_stop_trace = cxl_stop_trace_psl8,
1619 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1620 .timebase_read = timebase_read_psl8,
b385c9e9 1621 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
5e7823c9 1622 .needs_reset_before_disable = true,
6d382616
FB		 1623};
1624
6d382616
FB		 1625static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1626{
f3988ca4
FB		 1627 if (cxl_is_power8()) {
1628 dev_info(&dev->dev, "Device uses a PSL8\n");
1629 adapter->native->sl_ops = &psl8_ops;
6d382616 1630 } else {
f3988ca4
FB		 1631 dev_info(&dev->dev, "Device uses a PSL9\n");
1632 adapter->native->sl_ops = &psl9_ops;
6d382616
FB		 1633 }
1634}
1635
1636
2b04cf31 1637static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
c044c415
DA		 1638{
1639 struct cxl *adapter;
1640 int rc;
1641
1642 adapter = cxl_alloc_adapter();
1643 if (!adapter)
1644 return ERR_PTR(-ENOMEM);
1645
cbffa3a5
CL		 1646 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1647 if (!adapter->native) {
1648 rc = -ENOMEM;
1649 goto err_release;
1650 }
1651
6d382616
FB		 1652 set_sl_ops(adapter, dev);
1653
c044c415
DA		 1654 /* Set defaults for parameters which need to persist over
1655 * configure/reconfigure
1656 */
1657 adapter->perst_loads_image = true;
13e68d8b 1658 adapter->perst_same_image = false;
c044c415
DA		 1659
1660 rc = cxl_configure_adapter(adapter, dev);
1661 if (rc) {
1662 pci_disable_device(dev);
cbffa3a5 1663 goto err_release;
c044c415 1664 }
f204e0b8
IM		 1665
1666 /* Don't care if this one fails: */
1667 cxl_debugfs_adapter_add(adapter);
1668
1669 /*
1670 * After we call this function we must not free the adapter directly,
1671 * even if it returns an error!
1672 */
1673 if ((rc = cxl_register_adapter(adapter)))
1674 goto err_put1;
1675
1676 if ((rc = cxl_sysfs_adapter_add(adapter)))
1677 goto err_put1;
1678
ea9a26d1
VJ		 1679 /* Release the context lock as adapter is configured */
1680 cxl_adapter_context_unlock(adapter);
1681
f204e0b8
IM		 1682 return adapter;
1683
1684err_put1:
c044c415
DA		 1685 /* This should mirror cxl_remove_adapter, except without the
1686 * sysfs parts
1687 */
f204e0b8 1688 cxl_debugfs_adapter_remove(adapter);
c044c415
DA		 1689 cxl_deconfigure_adapter(adapter);
1690 device_unregister(&adapter->dev);
f204e0b8 1691 return ERR_PTR(rc);
cbffa3a5
CL		 1692
1693err_release:
1694 cxl_release_adapter(&adapter->dev);
1695 return ERR_PTR(rc);
f204e0b8
IM		 1696}
1697
2b04cf31 1698static void cxl_pci_remove_adapter(struct cxl *adapter)
f204e0b8 1699{
c044c415 1700 pr_devel("cxl_remove_adapter\n");
f204e0b8
IM		 1701
1702 cxl_sysfs_adapter_remove(adapter);
1703 cxl_debugfs_adapter_remove(adapter);
f204e0b8 1704
f24be42a
CL		 1705 /*
1706 * Flush adapter datacache as its about to be removed.
f24be42a 1707 */
94322ed8 1708 cxl_data_cache_flush(adapter);
d7b1946c 1709
c044c415 1710 cxl_deconfigure_adapter(adapter);
f204e0b8 1711
c044c415 1712 device_unregister(&adapter->dev);
f204e0b8
IM		 1713}
1714
3b3dcd61
PB		 1715#define CXL_MAX_PCIEX_PARENT 2
1716
3ced8d73 1717int cxl_slot_is_switched(struct pci_dev *dev)
3b3dcd61
PB		 1718{
1719 struct device_node *np;
1720 int depth = 0;
3b3dcd61
PB		 1721
1722 if (!(np = pci_device_to_OF_node(dev))) {
1723 pr_err("cxl: np = NULL\n");
1724 return -ENODEV;
1725 }
1726 of_node_get(np);
1727 while (np) {
1728 np = of_get_next_parent(np);
d2db0979 1729 if (!of_node_is_type(np, "pciex"))
3b3dcd61
PB		 1730 break;
1731 depth++;
1732 }
1733 of_node_put(np);
1734 return (depth > CXL_MAX_PCIEX_PARENT);
1735}
1736
f204e0b8
IM		 1737static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
1738{
1739 struct cxl *adapter;
1740 int slice;
1741 int rc;
1742
17eb3eef
VJ		 1743 if (cxl_pci_is_vphb_device(dev)) {
1744 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
1745 return -ENODEV;
1746 }
1747
3b3dcd61
PB		 1748 if (cxl_slot_is_switched(dev)) {
1749 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
1750 return -ENODEV;
1751 }
1752
f24be42a
CL		 1753 if (cxl_is_power9() && !radix_enabled()) {
1754 dev_info(&dev->dev, "Only Radix mode supported\n");
1755 return -ENODEV;
1756 }
1757
f204e0b8
IM		 1758 if (cxl_verbose)
1759 dump_cxl_config_space(dev);
1760
2b04cf31 1761 adapter = cxl_pci_init_adapter(dev);
f204e0b8
IM		 1762 if (IS_ERR(adapter)) {
1763 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
1764 return PTR_ERR(adapter);
1765 }
1766
1767 for (slice = 0; slice < adapter->slices; slice++) {
2b04cf31 1768 if ((rc = pci_init_afu(adapter, slice, dev))) {
f204e0b8 1769 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
d76427b0
DA		 1770 continue;
1771 }
1772
1773 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1774 if (rc)
1775 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
f204e0b8
IM		 1776 }
1777
1778 return 0;
1779}
1780
1781static void cxl_remove(struct pci_dev *dev)
1782{
1783 struct cxl *adapter = pci_get_drvdata(dev);
6f7f0b3d
MN		 1784 struct cxl_afu *afu;
1785 int i;
f204e0b8 1786
f204e0b8
IM		 1787 /*
1788 * Lock to prevent someone grabbing a ref through the adapter list as
1789 * we are removing it
1790 */
6f7f0b3d
MN		 1791 for (i = 0; i < adapter->slices; i++) {
1792 afu = adapter->afu[i];
2b04cf31 1793 cxl_pci_remove_afu(afu);
6f7f0b3d 1794 }
2b04cf31 1795 cxl_pci_remove_adapter(adapter);
f204e0b8
IM		 1796}
1797
9e8df8a2
DA		 1798static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1799 pci_channel_state_t state)
1800{
1801 struct pci_dev *afu_dev;
1802 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1803 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
1804
1805 /* There should only be one entry, but go through the list
1806 * anyway
1807 */
edeb304f 1808 if (afu == NULL || afu->phb == NULL)
12841f87
VJ		 1809 return result;
1810
9e8df8a2
DA		 1811 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1812 if (!afu_dev->driver)
1813 continue;
1814
1815 afu_dev->error_state = state;
1816
1817 if (afu_dev->driver->err_handler)
1818 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
1819 state);
1820 /* Disconnect trumps all, NONE trumps NEED_RESET */
1821 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1822 result = PCI_ERS_RESULT_DISCONNECT;
1823 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1824 (result == PCI_ERS_RESULT_NEED_RESET))
1825 result = PCI_ERS_RESULT_NONE;
1826 }
1827 return result;
1828}
1829
1830static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
1831 pci_channel_state_t state)
1832{
1833 struct cxl *adapter = pci_get_drvdata(pdev);
1834 struct cxl_afu *afu;
edeb304f
VJ		 1835 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
1836 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
9e8df8a2
DA		 1837 int i;
1838
1839 /* At this point, we could still have an interrupt pending.
1840 * Let's try to get them out of the way before they do
1841 * anything we don't like.
1842 */
1843 schedule();
1844
1845 /* If we're permanently dead, give up. */
1846 if (state == pci_channel_io_perm_failure) {
edeb304f 1847 spin_lock(&adapter->afu_list_lock);
9e8df8a2
DA		 1848 for (i = 0; i < adapter->slices; i++) {
1849 afu = adapter->afu[i];
07f5ab60
VJ		 1850 /*
1851 * Tell the AFU drivers; but we don't care what they
1852 * say, we're going away.
1853 */
12841f87 1854 cxl_vphb_error_detected(afu, state);
9e8df8a2 1855 }
edeb304f 1856 spin_unlock(&adapter->afu_list_lock);
9e8df8a2
DA		 1857 return PCI_ERS_RESULT_DISCONNECT;
1858 }
1859
1860 /* Are we reflashing?
1861 *
1862 * If we reflash, we could come back as something entirely
1863 * different, including a non-CAPI card. As such, by default
1864 * we don't participate in the process. We'll be unbound and
1865 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
1866 * us!)
1867 *
1868 * However, this isn't the entire story: for reliablity
1869 * reasons, we usually want to reflash the FPGA on PERST in
1870 * order to get back to a more reliable known-good state.
1871 *
1872 * This causes us a bit of a problem: if we reflash we can't
1873 * trust that we'll come back the same - we could have a new
1874 * image and been PERSTed in order to load that
1875 * image. However, most of the time we actually *will* come
1876 * back the same - for example a regular EEH event.
1877 *
1878 * Therefore, we allow the user to assert that the image is
1879 * indeed the same and that we should continue on into EEH
1880 * anyway.
1881 */
1882 if (adapter->perst_loads_image && !adapter->perst_same_image) {
1883 /* TODO take the PHB out of CXL mode */
1884 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
1885 return PCI_ERS_RESULT_NONE;
1886 }
1887
1888 /*
1889 * At this point, we want to try to recover. We'll always
1890 * need a complete slot reset: we don't trust any other reset.
1891 *
1892 * Now, we go through each AFU:
1893 * - We send the driver, if bound, an error_detected callback.
1894 * We expect it to clean up, but it can also tell us to give
1895 * up and permanently detach the card. To simplify things, if
1896 * any bound AFU driver doesn't support EEH, we give up on EEH.
1897 *
1898 * - We detach all contexts associated with the AFU. This
1899 * does not free them, but puts them into a CLOSED state
1900 * which causes any the associated files to return useful
1901 * errors to userland. It also unmaps, but does not free,
1902 * any IRQs.
1903 *
1904 * - We clean up our side: releasing and unmapping resources we hold
1905 * so we can wire them up again when the hardware comes back up.
1906 *
1907 * Driver authors should note:
1908 *
1909 * - Any contexts you create in your kernel driver (except
1910 * those associated with anonymous file descriptors) are
1911 * your responsibility to free and recreate. Likewise with
1912 * any attached resources.
1913 *
1914 * - We will take responsibility for re-initialising the
1915 * device context (the one set up for you in
1916 * cxl_pci_enable_device_hook and accessed through
1917 * cxl_get_context). If you've attached IRQs or other
1918 * resources to it, they remains yours to free.
1919 *
1920 * You can call the same functions to release resources as you
1921 * normally would: we make sure that these functions continue
1922 * to work when the hardware is down.
1923 *
1924 * Two examples:
1925 *
1926 * 1) If you normally free all your resources at the end of
1927 * each request, or if you use anonymous FDs, your
1928 * error_detected callback can simply set a flag to tell
1929 * your driver not to start any new calls. You can then
1930 * clear the flag in the resume callback.
1931 *
1932 * 2) If you normally allocate your resources on startup:
1933 * * Set a flag in error_detected as above.
1934 * * Let CXL detach your contexts.
1935 * * In slot_reset, free the old resources and allocate new ones.
1936 * * In resume, clear the flag to allow things to start.
1937 */
edeb304f
VJ		 1938
1939 /* Make sure no one else changes the afu list */
1940 spin_lock(&adapter->afu_list_lock);
1941
9e8df8a2
DA		 1942 for (i = 0; i < adapter->slices; i++) {
1943 afu = adapter->afu[i];
1944
edeb304f
VJ		 1945 if (afu == NULL)
1946 continue;
9e8df8a2 1947
edeb304f 1948 afu_result = cxl_vphb_error_detected(afu, state);
9e8df8a2 1949 cxl_context_detach_all(afu);
5be587b1 1950 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2b04cf31 1951 pci_deconfigure_afu(afu);
4f58f0bf
VJ		 1952
1953 /* Disconnect trumps all, NONE trumps NEED_RESET */
1954 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
1955 result = PCI_ERS_RESULT_DISCONNECT;
1956 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
1957 (result == PCI_ERS_RESULT_NEED_RESET))
1958 result = PCI_ERS_RESULT_NONE;
9e8df8a2 1959 }
edeb304f 1960 spin_unlock(&adapter->afu_list_lock);
ea9a26d1
VJ		 1961
1962 /* should take the context lock here */
1963 if (cxl_adapter_context_lock(adapter) != 0)
1964 dev_warn(&adapter->dev,
1965 "Couldn't take context lock with %d active-contexts\n",
1966 atomic_read(&adapter->contexts_num));
1967
9e8df8a2
DA		 1968 cxl_deconfigure_adapter(adapter);
1969
1970 return result;
1971}
1972
1973static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
1974{
1975 struct cxl *adapter = pci_get_drvdata(pdev);
1976 struct cxl_afu *afu;
1977 struct cxl_context *ctx;
1978 struct pci_dev *afu_dev;
1979 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
1980 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
1981 int i;
1982
1983 if (cxl_configure_adapter(adapter, pdev))
1984 goto err;
1985
ea9a26d1
VJ		 1986 /*
1987 * Unlock context activation for the adapter. Ideally this should be
1988 * done in cxl_pci_resume but cxlflash module tries to activate the
1989 * master context as part of slot_reset callback.
1990 */
1991 cxl_adapter_context_unlock(adapter);
1992
edeb304f 1993 spin_lock(&adapter->afu_list_lock);
9e8df8a2
DA		 1994 for (i = 0; i < adapter->slices; i++) {
1995 afu = adapter->afu[i];
1996
edeb304f
VJ		 1997 if (afu == NULL)
1998 continue;
1999
2b04cf31 2000 if (pci_configure_afu(afu, adapter, pdev))
edeb304f 2001 goto err_unlock;
9e8df8a2
DA		 2002
2003 if (cxl_afu_select_best_mode(afu))
edeb304f 2004 goto err_unlock;
9e8df8a2 2005
12841f87
VJ		 2006 if (afu->phb == NULL)
2007 continue;
2008
9e8df8a2
DA		 2009 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2010 /* Reset the device context.
2011 * TODO: make this less disruptive
2012 */
2013 ctx = cxl_get_context(afu_dev);
2014
2015 if (ctx && cxl_release_context(ctx))
edeb304f 2016 goto err_unlock;
9e8df8a2
DA		 2017
2018 ctx = cxl_dev_context_init(afu_dev);
bb81733d 2019 if (IS_ERR(ctx))
edeb304f 2020 goto err_unlock;
9e8df8a2
DA		 2021
2022 afu_dev->dev.archdata.cxl_ctx = ctx;
2023
5be587b1 2024 if (cxl_ops->afu_check_and_enable(afu))
edeb304f 2025 goto err_unlock;
9e8df8a2
DA		 2026
2027 afu_dev->error_state = pci_channel_io_normal;
2028
2029 /* If there's a driver attached, allow it to
2030 * chime in on recovery. Drivers should check
2031 * if everything has come back OK, but
2032 * shouldn't start new work until we call
2033 * their resume function.
2034 */
2035 if (!afu_dev->driver)
2036 continue;
2037
2038 if (afu_dev->driver->err_handler &&
2039 afu_dev->driver->err_handler->slot_reset)
2040 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2041
2042 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2043 result = PCI_ERS_RESULT_DISCONNECT;
2044 }
2045 }
edeb304f
VJ		 2046
2047 spin_unlock(&adapter->afu_list_lock);
9e8df8a2
DA		 2048 return result;
2049
edeb304f
VJ		 2050err_unlock:
2051 spin_unlock(&adapter->afu_list_lock);
2052
9e8df8a2
DA		 2053err:
2054 /* All the bits that happen in both error_detected and cxl_remove
2055 * should be idempotent, so we don't need to worry about leaving a mix
2056 * of unconfigured and reconfigured resources.
2057 */
2058 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2059 return PCI_ERS_RESULT_DISCONNECT;
2060}
2061
2062static void cxl_pci_resume(struct pci_dev *pdev)
2063{
2064 struct cxl *adapter = pci_get_drvdata(pdev);
2065 struct cxl_afu *afu;
2066 struct pci_dev *afu_dev;
2067 int i;
2068
2069 /* Everything is back now. Drivers should restart work now.
2070 * This is not the place to be checking if everything came back up
2071 * properly, because there's no return value: do that in slot_reset.
2072 */
edeb304f 2073 spin_lock(&adapter->afu_list_lock);
9e8df8a2
DA		 2074 for (i = 0; i < adapter->slices; i++) {
2075 afu = adapter->afu[i];
2076
edeb304f 2077 if (afu == NULL || afu->phb == NULL)
12841f87
VJ		 2078 continue;
2079
9e8df8a2
DA		 2080 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2081 if (afu_dev->driver && afu_dev->driver->err_handler &&
2082 afu_dev->driver->err_handler->resume)
2083 afu_dev->driver->err_handler->resume(afu_dev);
2084 }
2085 }
edeb304f 2086 spin_unlock(&adapter->afu_list_lock);
9e8df8a2
DA		 2087}
2088
2089static const struct pci_error_handlers cxl_err_handler = {
2090 .error_detected = cxl_pci_error_detected,
2091 .slot_reset = cxl_pci_slot_reset,
2092 .resume = cxl_pci_resume,
2093};
2094
f204e0b8
IM		 2095struct pci_driver cxl_pci_driver = {
2096 .name = "cxl-pci",
2097 .id_table = cxl_pci_tbl,
2098 .probe = cxl_probe,
2099 .remove = cxl_remove,
aa70775e 2100 .shutdown = cxl_remove,
9e8df8a2 2101 .err_handler = &cxl_err_handler,
f204e0b8 2102};
Linux 6.x block layer and io_uring tree(s)