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powerpc/64s: Remove POWER9 DD1 support
[linux-2.6-block.git] / drivers / misc / cxl / pci.c
CommitLineData
f204e0b8
IM		 1/*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10#include <linux/pci_regs.h>
11#include <linux/pci_ids.h>
12#include <linux/device.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/sort.h>
17#include <linux/pci.h>
18#include <linux/of.h>
19#include <linux/delay.h>
20#include <asm/opal.h>
21#include <asm/msi_bitmap.h>
f204e0b8 22#include <asm/pnv-pci.h>
62fa19d4 23#include <asm/io.h>
aa14138a 24#include <asm/reg.h>
f204e0b8
IM		 25
26#include "cxl.h"
9e8df8a2 27#include <misc/cxl.h>
f204e0b8
IM		 28
29
30#define CXL_PCI_VSEC_ID 0x1280
31#define CXL_VSEC_MIN_SIZE 0x80
32
33#define CXL_READ_VSEC_LENGTH(dev, vsec, dest) \
34 { \
35 pci_read_config_word(dev, vsec + 0x6, dest); \
36 *dest >>= 4; \
37 }
38#define CXL_READ_VSEC_NAFUS(dev, vsec, dest) \
39 pci_read_config_byte(dev, vsec + 0x8, dest)
40
41#define CXL_READ_VSEC_STATUS(dev, vsec, dest) \
42 pci_read_config_byte(dev, vsec + 0x9, dest)
43#define CXL_STATUS_SECOND_PORT 0x80
44#define CXL_STATUS_MSI_X_FULL 0x40
45#define CXL_STATUS_MSI_X_SINGLE 0x20
46#define CXL_STATUS_FLASH_RW 0x08
47#define CXL_STATUS_FLASH_RO 0x04
48#define CXL_STATUS_LOADABLE_AFU 0x02
49#define CXL_STATUS_LOADABLE_PSL 0x01
50/* If we see these features we won't try to use the card */
51#define CXL_UNSUPPORTED_FEATURES \
52 (CXL_STATUS_MSI_X_FULL | CXL_STATUS_MSI_X_SINGLE)
53
54#define CXL_READ_VSEC_MODE_CONTROL(dev, vsec, dest) \
55 pci_read_config_byte(dev, vsec + 0xa, dest)
56#define CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val) \
57 pci_write_config_byte(dev, vsec + 0xa, val)
b0b5e591
AD		 58#define CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, vsec, val) \
59 pci_bus_write_config_byte(bus, devfn, vsec + 0xa, val)
f204e0b8
IM		 60#define CXL_VSEC_PROTOCOL_MASK 0xe0
61#define CXL_VSEC_PROTOCOL_1024TB 0x80
62#define CXL_VSEC_PROTOCOL_512TB 0x40
f24be42a 63#define CXL_VSEC_PROTOCOL_256TB 0x20 /* Power 8/9 uses this */
f204e0b8
IM		 64#define CXL_VSEC_PROTOCOL_ENABLE 0x01
65
66#define CXL_READ_VSEC_PSL_REVISION(dev, vsec, dest) \
67 pci_read_config_word(dev, vsec + 0xc, dest)
68#define CXL_READ_VSEC_CAIA_MINOR(dev, vsec, dest) \
69 pci_read_config_byte(dev, vsec + 0xe, dest)
70#define CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, dest) \
71 pci_read_config_byte(dev, vsec + 0xf, dest)
72#define CXL_READ_VSEC_BASE_IMAGE(dev, vsec, dest) \
73 pci_read_config_word(dev, vsec + 0x10, dest)
74
75#define CXL_READ_VSEC_IMAGE_STATE(dev, vsec, dest) \
76 pci_read_config_byte(dev, vsec + 0x13, dest)
77#define CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, val) \
78 pci_write_config_byte(dev, vsec + 0x13, val)
79#define CXL_VSEC_USER_IMAGE_LOADED 0x80 /* RO */
80#define CXL_VSEC_PERST_LOADS_IMAGE 0x20 /* RW */
81#define CXL_VSEC_PERST_SELECT_USER 0x10 /* RW */
82
83#define CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, dest) \
84 pci_read_config_dword(dev, vsec + 0x20, dest)
85#define CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, dest) \
86 pci_read_config_dword(dev, vsec + 0x24, dest)
87#define CXL_READ_VSEC_PS_OFF(dev, vsec, dest) \
88 pci_read_config_dword(dev, vsec + 0x28, dest)
89#define CXL_READ_VSEC_PS_SIZE(dev, vsec, dest) \
90 pci_read_config_dword(dev, vsec + 0x2c, dest)
91
92
93/* This works a little different than the p1/p2 register accesses to make it
94 * easier to pull out individual fields */
cbffa3a5
CL		 95#define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
96#define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
f204e0b8
IM		 97#define EXTRACT_PPC_BIT(val, bit) (!!(val & PPC_BIT(bit)))
98#define EXTRACT_PPC_BITS(val, bs, be) ((val & PPC_BITMASK(bs, be)) >> PPC_BITLSHIFT(be))
99
100#define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
101#define AFUD_NUM_INTS_PER_PROC(val) EXTRACT_PPC_BITS(val, 0, 15)
102#define AFUD_NUM_PROCS(val) EXTRACT_PPC_BITS(val, 16, 31)
103#define AFUD_NUM_CRS(val) EXTRACT_PPC_BITS(val, 32, 47)
104#define AFUD_MULTIMODE(val) EXTRACT_PPC_BIT(val, 48)
105#define AFUD_PUSH_BLOCK_TRANSFER(val) EXTRACT_PPC_BIT(val, 55)
106#define AFUD_DEDICATED_PROCESS(val) EXTRACT_PPC_BIT(val, 59)
107#define AFUD_AFU_DIRECTED(val) EXTRACT_PPC_BIT(val, 61)
108#define AFUD_TIME_SLICED(val) EXTRACT_PPC_BIT(val, 63)
109#define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
110#define AFUD_CR_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
111#define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
112#define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
113#define AFUD_PPPSA_PP(val) EXTRACT_PPC_BIT(val, 6)
114#define AFUD_PPPSA_PSA(val) EXTRACT_PPC_BIT(val, 7)
115#define AFUD_PPPSA_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
116#define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
117#define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
118#define AFUD_EB_LEN(val) EXTRACT_PPC_BITS(val, 8, 63)
119#define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
120
f47f966f 121static const struct pci_device_id cxl_pci_tbl[] = {
f204e0b8
IM		 122 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0477), },
123 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x044b), },
124 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x04cf), },
68adb7bf 125 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0601), },
41e20d95
MO		 126 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0623), },
127 { PCI_DEVICE(PCI_VENDOR_ID_IBM, 0x0628), },
f204e0b8
IM		 128 { }
129};
130MODULE_DEVICE_TABLE(pci, cxl_pci_tbl);
131
132
133/*
134 * Mostly using these wrappers to avoid confusion:
135 * priv 1 is BAR2, while priv 2 is BAR0
136 */
137static inline resource_size_t p1_base(struct pci_dev *dev)
138{
139 return pci_resource_start(dev, 2);
140}
141
142static inline resource_size_t p1_size(struct pci_dev *dev)
143{
144 return pci_resource_len(dev, 2);
145}
146
147static inline resource_size_t p2_base(struct pci_dev *dev)
148{
149 return pci_resource_start(dev, 0);
150}
151
152static inline resource_size_t p2_size(struct pci_dev *dev)
153{
154 return pci_resource_len(dev, 0);
155}
156
157static int find_cxl_vsec(struct pci_dev *dev)
158{
159 int vsec = 0;
160 u16 val;
161
162 while ((vsec = pci_find_next_ext_capability(dev, vsec, PCI_EXT_CAP_ID_VNDR))) {
163 pci_read_config_word(dev, vsec + 0x4, &val);
164 if (val == CXL_PCI_VSEC_ID)
165 return vsec;
166 }
167 return 0;
168
169}
170
171static void dump_cxl_config_space(struct pci_dev *dev)
172{
173 int vsec;
174 u32 val;
175
176 dev_info(&dev->dev, "dump_cxl_config_space\n");
177
178 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &val);
179 dev_info(&dev->dev, "BAR0: %#.8x\n", val);
180 pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &val);
181 dev_info(&dev->dev, "BAR1: %#.8x\n", val);
182 pci_read_config_dword(dev, PCI_BASE_ADDRESS_2, &val);
183 dev_info(&dev->dev, "BAR2: %#.8x\n", val);
184 pci_read_config_dword(dev, PCI_BASE_ADDRESS_3, &val);
185 dev_info(&dev->dev, "BAR3: %#.8x\n", val);
186 pci_read_config_dword(dev, PCI_BASE_ADDRESS_4, &val);
187 dev_info(&dev->dev, "BAR4: %#.8x\n", val);
188 pci_read_config_dword(dev, PCI_BASE_ADDRESS_5, &val);
189 dev_info(&dev->dev, "BAR5: %#.8x\n", val);
190
191 dev_info(&dev->dev, "p1 regs: %#llx, len: %#llx\n",
192 p1_base(dev), p1_size(dev));
193 dev_info(&dev->dev, "p2 regs: %#llx, len: %#llx\n",
f2931069 194 p2_base(dev), p2_size(dev));
f204e0b8
IM		 195 dev_info(&dev->dev, "BAR 4/5: %#llx, len: %#llx\n",
196 pci_resource_start(dev, 4), pci_resource_len(dev, 4));
197
198 if (!(vsec = find_cxl_vsec(dev)))
199 return;
200
201#define show_reg(name, what) \
202 dev_info(&dev->dev, "cxl vsec: %30s: %#x\n", name, what)
203
204 pci_read_config_dword(dev, vsec + 0x0, &val);
205 show_reg("Cap ID", (val >> 0) & 0xffff);
206 show_reg("Cap Ver", (val >> 16) & 0xf);
207 show_reg("Next Cap Ptr", (val >> 20) & 0xfff);
208 pci_read_config_dword(dev, vsec + 0x4, &val);
209 show_reg("VSEC ID", (val >> 0) & 0xffff);
210 show_reg("VSEC Rev", (val >> 16) & 0xf);
211 show_reg("VSEC Length", (val >> 20) & 0xfff);
212 pci_read_config_dword(dev, vsec + 0x8, &val);
213 show_reg("Num AFUs", (val >> 0) & 0xff);
214 show_reg("Status", (val >> 8) & 0xff);
215 show_reg("Mode Control", (val >> 16) & 0xff);
216 show_reg("Reserved", (val >> 24) & 0xff);
217 pci_read_config_dword(dev, vsec + 0xc, &val);
218 show_reg("PSL Rev", (val >> 0) & 0xffff);
219 show_reg("CAIA Ver", (val >> 16) & 0xffff);
220 pci_read_config_dword(dev, vsec + 0x10, &val);
221 show_reg("Base Image Rev", (val >> 0) & 0xffff);
222 show_reg("Reserved", (val >> 16) & 0x0fff);
223 show_reg("Image Control", (val >> 28) & 0x3);
224 show_reg("Reserved", (val >> 30) & 0x1);
225 show_reg("Image Loaded", (val >> 31) & 0x1);
226
227 pci_read_config_dword(dev, vsec + 0x14, &val);
228 show_reg("Reserved", val);
229 pci_read_config_dword(dev, vsec + 0x18, &val);
230 show_reg("Reserved", val);
231 pci_read_config_dword(dev, vsec + 0x1c, &val);
232 show_reg("Reserved", val);
233
234 pci_read_config_dword(dev, vsec + 0x20, &val);
235 show_reg("AFU Descriptor Offset", val);
236 pci_read_config_dword(dev, vsec + 0x24, &val);
237 show_reg("AFU Descriptor Size", val);
238 pci_read_config_dword(dev, vsec + 0x28, &val);
239 show_reg("Problem State Offset", val);
240 pci_read_config_dword(dev, vsec + 0x2c, &val);
241 show_reg("Problem State Size", val);
242
243 pci_read_config_dword(dev, vsec + 0x30, &val);
244 show_reg("Reserved", val);
245 pci_read_config_dword(dev, vsec + 0x34, &val);
246 show_reg("Reserved", val);
247 pci_read_config_dword(dev, vsec + 0x38, &val);
248 show_reg("Reserved", val);
249 pci_read_config_dword(dev, vsec + 0x3c, &val);
250 show_reg("Reserved", val);
251
252 pci_read_config_dword(dev, vsec + 0x40, &val);
253 show_reg("PSL Programming Port", val);
254 pci_read_config_dword(dev, vsec + 0x44, &val);
255 show_reg("PSL Programming Control", val);
256
257 pci_read_config_dword(dev, vsec + 0x48, &val);
258 show_reg("Reserved", val);
259 pci_read_config_dword(dev, vsec + 0x4c, &val);
260 show_reg("Reserved", val);
261
262 pci_read_config_dword(dev, vsec + 0x50, &val);
263 show_reg("Flash Address Register", val);
264 pci_read_config_dword(dev, vsec + 0x54, &val);
265 show_reg("Flash Size Register", val);
266 pci_read_config_dword(dev, vsec + 0x58, &val);
267 show_reg("Flash Status/Control Register", val);
268 pci_read_config_dword(dev, vsec + 0x58, &val);
269 show_reg("Flash Data Port", val);
270
271#undef show_reg
272}
273
274static void dump_afu_descriptor(struct cxl_afu *afu)
275{
bfcdc8ff
MN		 276 u64 val, afu_cr_num, afu_cr_off, afu_cr_len;
277 int i;
f204e0b8
IM		 278
279#define show_reg(name, what) \
280 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
281
282 val = AFUD_READ_INFO(afu);
283 show_reg("num_ints_per_process", AFUD_NUM_INTS_PER_PROC(val));
284 show_reg("num_of_processes", AFUD_NUM_PROCS(val));
285 show_reg("num_of_afu_CRs", AFUD_NUM_CRS(val));
286 show_reg("req_prog_mode", val & 0xffffULL);
bfcdc8ff 287 afu_cr_num = AFUD_NUM_CRS(val);
f204e0b8
IM		 288
289 val = AFUD_READ(afu, 0x8);
290 show_reg("Reserved", val);
291 val = AFUD_READ(afu, 0x10);
292 show_reg("Reserved", val);
293 val = AFUD_READ(afu, 0x18);
294 show_reg("Reserved", val);
295
296 val = AFUD_READ_CR(afu);
297 show_reg("Reserved", (val >> (63-7)) & 0xff);
298 show_reg("AFU_CR_len", AFUD_CR_LEN(val));
bfcdc8ff 299 afu_cr_len = AFUD_CR_LEN(val) * 256;
f204e0b8
IM		 300
301 val = AFUD_READ_CR_OFF(afu);
bfcdc8ff 302 afu_cr_off = val;
f204e0b8
IM		 303 show_reg("AFU_CR_offset", val);
304
305 val = AFUD_READ_PPPSA(afu);
306 show_reg("PerProcessPSA_control", (val >> (63-7)) & 0xff);
307 show_reg("PerProcessPSA Length", AFUD_PPPSA_LEN(val));
308
309 val = AFUD_READ_PPPSA_OFF(afu);
310 show_reg("PerProcessPSA_offset", val);
311
312 val = AFUD_READ_EB(afu);
313 show_reg("Reserved", (val >> (63-7)) & 0xff);
314 show_reg("AFU_EB_len", AFUD_EB_LEN(val));
315
316 val = AFUD_READ_EB_OFF(afu);
317 show_reg("AFU_EB_offset", val);
318
bfcdc8ff
MN		 319 for (i = 0; i < afu_cr_num; i++) {
320 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
321 show_reg("CR Vendor", val & 0xffff);
322 show_reg("CR Device", (val >> 16) & 0xffff);
323 }
f204e0b8
IM		 324#undef show_reg
325}
326
abd1d99b
CL		 327#define P8_CAPP_UNIT0_ID 0xBA
328#define P8_CAPP_UNIT1_ID 0XBE
f24be42a
CL		 329#define P9_CAPP_UNIT0_ID 0xC0
330#define P9_CAPP_UNIT1_ID 0xE0
aa14138a 331
f24be42a 332static int get_phb_index(struct device_node *np, u32 *phb_index)
aa14138a 333{
f24be42a
CL		 334 if (of_property_read_u32(np, "ibm,phb-index", phb_index))
335 return -ENODEV;
336 return 0;
337}
aa14138a 338
f24be42a
CL		 339static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
340{
aa14138a 341 /*
abd1d99b
CL		 342 * POWER 8:
343 * - For chips other than POWER8NVL, we only have CAPP 0,
344 * irrespective of which PHB is used.
345 * - For POWER8NVL, assume CAPP 0 is attached to PHB0 and
346 * CAPP 1 is attached to PHB1.
aa14138a 347 */
abd1d99b
CL		 348 if (cxl_is_power8()) {
349 if (!pvr_version_is(PVR_POWER8NVL))
350 return P8_CAPP_UNIT0_ID;
aa14138a 351
abd1d99b
CL		 352 if (phb_index == 0)
353 return P8_CAPP_UNIT0_ID;
aa14138a 354
abd1d99b
CL		 355 if (phb_index == 1)
356 return P8_CAPP_UNIT1_ID;
357 }
aa14138a
PB		 358
359 /*
f24be42a
CL		 360 * POWER 9:
361 * PEC0 (PHB0). Capp ID = CAPP0 (0b1100_0000)
362 * PEC1 (PHB1 - PHB2). No capi mode
363 * PEC2 (PHB3 - PHB4 - PHB5): Capi mode on PHB3 only. Capp ID = CAPP1 (0b1110_0000)
aa14138a 364 */
f24be42a
CL		 365 if (cxl_is_power9()) {
366 if (phb_index == 0)
367 return P9_CAPP_UNIT0_ID;
aa14138a 368
f24be42a
CL		 369 if (phb_index == 3)
370 return P9_CAPP_UNIT1_ID;
371 }
aa14138a
PB		 372
373 return 0;
374}
375
3ced8d73 376int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
f24be42a 377 u32 *phb_index, u64 *capp_unit_id)
f204e0b8 378{
f24be42a 379 int rc;
f204e0b8
IM		 380 struct device_node *np;
381 const __be32 *prop;
f204e0b8 382
6f963ec2 383 if (!(np = pnv_pci_get_phb_node(dev)))
f204e0b8
IM		 384 return -ENODEV;
385
386 while (np && !(prop = of_get_property(np, "ibm,chip-id", NULL)))
387 np = of_get_next_parent(np);
388 if (!np)
389 return -ENODEV;
f24be42a 390
6d382616 391 *chipid = be32_to_cpup(prop);
f24be42a
CL		 392
393 rc = get_phb_index(np, phb_index);
394 if (rc) {
395 pr_err("cxl: invalid phb index\n");
396 return rc;
397 }
398
399 *capp_unit_id = get_capp_unit_id(np, *phb_index);
f204e0b8 400 of_node_put(np);
6d382616 401 if (!*capp_unit_id) {
56328743
CL		 402 pr_err("cxl: invalid capp unit id (phb_index: %d)\n",
403 *phb_index);
aa14138a
PB		 404 return -ENODEV;
405 }
f204e0b8 406
6d382616
FB		 407 return 0;
408}
409
9dbcbfa1
PB		 410static DEFINE_MUTEX(indications_mutex);
411
412static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
413 u64 *nbwind)
414{
415 static u64 nbw, asn, capi = 0;
416 struct device_node *np;
417 const __be32 *prop;
418
419 mutex_lock(&indications_mutex);
420 if (!capi) {
421 if (!(np = pnv_pci_get_phb_node(dev))) {
422 mutex_unlock(&indications_mutex);
423 return -ENODEV;
424 }
425
426 prop = of_get_property(np, "ibm,phb-indications", NULL);
427 if (!prop) {
428 nbw = 0x0300UL; /* legacy values */
429 asn = 0x0400UL;
430 capi = 0x0200UL;
431 } else {
432 nbw = (u64)be32_to_cpu(prop[2]);
433 asn = (u64)be32_to_cpu(prop[1]);
434 capi = (u64)be32_to_cpu(prop[0]);
435 }
436 of_node_put(np);
437 }
438 *capiind = capi;
439 *asnind = asn;
440 *nbwind = nbw;
441 mutex_unlock(&indications_mutex);
442 return 0;
443}
444
445int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
f24be42a 446{
3ced8d73 447 u64 xsl_dsnctl;
9dbcbfa1 448 u64 capiind, asnind, nbwind;
f24be42a
CL		 449
450 /*
451 * CAPI Identifier bits [0:7]
452 * bit 61:60 MSI bits --> 0
453 * bit 59 TVT selector --> 0
454 */
9dbcbfa1
PB		 455 if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
456 return -ENODEV;
f24be42a
CL		 457
458 /*
459 * Tell XSL where to route data to.
460 * The field chipid should match the PHB CAPI_CMPM register
461 */
9dbcbfa1 462 xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
f24be42a
CL		 463 xsl_dsnctl |= (capp_unit_id << (63-15));
464
465 /* nMMU_ID Defaults to: b’000001001’*/
466 xsl_dsnctl |= ((u64)0x09 << (63-28));
467
2bf1071a
NP		 468 /*
469 * Used to identify CAPI packets which should be sorted into
470 * the Non-Blocking queues by the PHB. This field should match
471 * the PHB PBL_NBW_CMPM register
472 * nbwind=0x03, bits [57:58], must include capi indicator.
473 * Not supported on P9 DD1.
474 */
475 xsl_dsnctl |= (nbwind << (63-55));
476
477 /*
478 * Upper 16b address bits of ASB_Notify messages sent to the
479 * system. Need to match the PHB’s ASN Compare/Mask Register.
480 * Not supported on P9 DD1.
481 */
482 xsl_dsnctl |= asnind;
f24be42a 483
3ced8d73
CL		 484 *reg = xsl_dsnctl;
485 return 0;
486}
487
488static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
489 struct pci_dev *dev)
490{
491 u64 xsl_dsnctl, psl_fircntl;
492 u64 chipid;
493 u32 phb_index;
494 u64 capp_unit_id;
94322ed8 495 u64 psl_debug;
3ced8d73
CL		 496 int rc;
497
498 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
499 if (rc)
500 return rc;
501
9dbcbfa1 502 rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
3ced8d73
CL		 503 if (rc)
504 return rc;
505
f24be42a
CL		 506 cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
507
508 /* Set fir_cntl to recommended value for production env */
509 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
510 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
511 psl_fircntl |= 0x1ULL; /* ce_thresh */
512 cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);
513
56328743 514 /* Setup the PSL to transmit packets on the PCIe before the
9a6d2022 515 * CAPP is enabled. Make sure that CAPP virtual machines are disabled
f24be42a 516 */
9a6d2022 517 cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000012A10ULL);
f24be42a
CL		 518
519 /*
520 * A response to an ASB_Notify request is returned by the
521 * system as an MMIO write to the address defined in
56328743
CL		 522 * the PSL_TNR_ADDR register.
523 * keep the Reset Value: 0x00020000E0000000
f24be42a 524 */
f24be42a 525
56328743
CL		 526 /* Enable XSL rty limit */
527 cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);
528
529 /* Change XSL_INV dummy read threshold */
530 cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);
531
532 if (phb_index == 3) {
533 /* disable machines 31-47 and 20-27 for DMA */
534 cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);
535 }
f24be42a 536
56328743
CL		 537 /* Snoop machines */
538 cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);
f24be42a 539
2bf1071a
NP		 540 /* Enable NORST and DD2 features */
541 cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
f24be42a 542
94322ed8
VJ		 543 /*
544 * Check if PSL has data-cache. We need to flush adapter datacache
545 * when as its about to be removed.
546 */
547 psl_debug = cxl_p1_read(adapter, CXL_PSL9_DEBUG);
548 if (psl_debug & CXL_PSL_DEBUG_CDC) {
549 dev_dbg(&dev->dev, "No data-cache present\n");
550 adapter->native->no_data_cache = true;
551 }
552
f24be42a
CL		 553 return 0;
554}
555
64663f37 556static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci_dev *dev)
6d382616 557{
c6d2ee09 558 u64 psl_dsnctl, psl_fircntl;
6d382616 559 u64 chipid;
f24be42a 560 u32 phb_index;
6d382616
FB		 561 u64 capp_unit_id;
562 int rc;
563
3ced8d73 564 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
6d382616
FB		 565 if (rc)
566 return rc;
567
4aec6ec0
FB		 568 psl_dsnctl = 0x0000900000000000ULL; /* pteupd ttype, scdone */
569 psl_dsnctl |= (0x2ULL << (63-38)); /* MMIO hang pulse: 256 us */
f204e0b8 570 /* Tell PSL where to route data to */
4aec6ec0 571 psl_dsnctl |= (chipid << (63-5));
aa14138a
PB		 572 psl_dsnctl |= (capp_unit_id << (63-13));
573
f204e0b8
IM		 574 cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
575 cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
576 /* snoop write mask */
577 cxl_p1_write(adapter, CXL_PSL_SNWRALLOC, 0x00000000FFFFFFFFULL);
c6d2ee09
FB		 578 /* set fir_cntl to recommended value for production env */
579 psl_fircntl = (0x2ULL << (63-3)); /* ce_report */
580 psl_fircntl |= (0x1ULL << (63-6)); /* FIR_report */
581 psl_fircntl |= 0x1ULL; /* ce_thresh */
582 cxl_p1_write(adapter, CXL_PSL_FIR_CNTL, psl_fircntl);
f204e0b8
IM		 583 /* for debugging with trace arrays */
584 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x0000FF7C00000000ULL);
585
586 return 0;
587}
588
bdd2e715 589static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_dev *dev)
6d382616
FB		 590{
591 u64 xsl_dsnctl;
592 u64 chipid;
f24be42a 593 u32 phb_index;
6d382616
FB		 594 u64 capp_unit_id;
595 int rc;
596
3ced8d73 597 rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
6d382616
FB		 598 if (rc)
599 return rc;
600
601 /* Tell XSL where to route data to */
602 xsl_dsnctl = 0x0000600000000000ULL | (chipid << (63-5));
603 xsl_dsnctl |= (capp_unit_id << (63-13));
604 cxl_p1_write(adapter, CXL_XSL_DSNCTL, xsl_dsnctl);
605
606 return 0;
607}
608
609/* PSL & XSL */
610#define TBSYNC_CAL(n) (((u64)n & 0x7) << (63-3))
390fd592 611#define TBSYNC_CNT(n) (((u64)n & 0x7) << (63-6))
6d382616
FB		 612/* For the PSL this is a multiple for 0 < n <= 7: */
613#define PSL_2048_250MHZ_CYCLES 1
614
64663f37 615static void write_timebase_ctrl_psl8(struct cxl *adapter)
6d382616
FB		 616{
617 cxl_p1_write(adapter, CXL_PSL_TB_CTLSTAT,
618 TBSYNC_CNT(2 * PSL_2048_250MHZ_CYCLES));
619}
620
621/* XSL */
622#define TBSYNC_ENA (1ULL << 63)
623/* For the XSL this is 2**n * 2000 clocks for 0 < n <= 6: */
624#define XSL_2000_CLOCKS 1
625#define XSL_4000_CLOCKS 2
626#define XSL_8000_CLOCKS 3
627
628static void write_timebase_ctrl_xsl(struct cxl *adapter)
629{
630 cxl_p1_write(adapter, CXL_XSL_TB_CTLSTAT,
631 TBSYNC_ENA |
632 TBSYNC_CAL(3) |
633 TBSYNC_CNT(XSL_4000_CLOCKS));
634}
635
f24be42a
CL		 636static u64 timebase_read_psl9(struct cxl *adapter)
637{
638 return cxl_p1_read(adapter, CXL_PSL9_Timebase);
639}
640
64663f37 641static u64 timebase_read_psl8(struct cxl *adapter)
6d382616
FB		 642{
643 return cxl_p1_read(adapter, CXL_PSL_Timebase);
644}
645
646static u64 timebase_read_xsl(struct cxl *adapter)
647{
648 return cxl_p1_read(adapter, CXL_XSL_Timebase);
649}
390fd592 650
e009a7e8 651static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
390fd592 652{
390fd592
PB		 653 struct device_node *np;
654
e009a7e8
FB		 655 adapter->psl_timebase_synced = false;
656
390fd592 657 if (!(np = pnv_pci_get_phb_node(dev)))
e009a7e8 658 return;
390fd592
PB		 659
660 /* Do not fail when CAPP timebase sync is not supported by OPAL */
661 of_node_get(np);
662 if (! of_get_property(np, "ibm,capp-timebase-sync", NULL)) {
663 of_node_put(np);
e009a7e8
FB		 664 dev_info(&dev->dev, "PSL timebase inactive: OPAL support missing\n");
665 return;
390fd592
PB		 666 }
667 of_node_put(np);
668
669 /*
670 * Setup PSL Timebase Control and Status register
671 * with the recommended Timebase Sync Count value
672 */
02b63b42
VJ		 673 if (adapter->native->sl_ops->write_timebase_ctrl)
674 adapter->native->sl_ops->write_timebase_ctrl(adapter);
390fd592
PB		 675
676 /* Enable PSL Timebase */
677 cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
678 cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
679
e009a7e8 680 return;
390fd592
PB		 681}
682
f24be42a
CL		 683static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
684{
685 return 0;
686}
687
64663f37 688static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
f204e0b8
IM		 689{
690 /* read/write masks for this slice */
691 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
692 /* APC read/write masks for this slice */
693 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
694 /* for debugging with trace arrays */
695 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
d6a6af2c 696 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
f204e0b8
IM		 697
698 return 0;
699}
700
2b04cf31
FB		 701int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq,
702 unsigned int virq)
f204e0b8
IM		 703{
704 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
705
706 return pnv_cxl_ioda_msi_setup(dev, hwirq, virq);
707}
708
4beb5421
RG		 709int cxl_update_image_control(struct cxl *adapter)
710{
711 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
712 int rc;
713 int vsec;
714 u8 image_state;
715
716 if (!(vsec = find_cxl_vsec(dev))) {
717 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
718 return -ENODEV;
719 }
720
721 if ((rc = CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state))) {
722 dev_err(&dev->dev, "failed to read image state: %i\n", rc);
723 return rc;
724 }
725
726 if (adapter->perst_loads_image)
727 image_state |= CXL_VSEC_PERST_LOADS_IMAGE;
728 else
729 image_state &= ~CXL_VSEC_PERST_LOADS_IMAGE;
730
731 if (adapter->perst_select_user)
732 image_state |= CXL_VSEC_PERST_SELECT_USER;
733 else
734 image_state &= ~CXL_VSEC_PERST_SELECT_USER;
735
736 if ((rc = CXL_WRITE_VSEC_IMAGE_STATE(dev, vsec, image_state))) {
737 dev_err(&dev->dev, "failed to update image control: %i\n", rc);
738 return rc;
739 }
740
741 return 0;
742}
743
2b04cf31 744int cxl_pci_alloc_one_irq(struct cxl *adapter)
f204e0b8
IM		 745{
746 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
747
748 return pnv_cxl_alloc_hwirqs(dev, 1);
749}
750
2b04cf31 751void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq)
f204e0b8
IM		 752{
753 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
754
755 return pnv_cxl_release_hwirqs(dev, hwirq, 1);
756}
757
2b04cf31
FB		 758int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs,
759 struct cxl *adapter, unsigned int num)
f204e0b8
IM		 760{
761 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
762
763 return pnv_cxl_alloc_hwirq_ranges(irqs, dev, num);
764}
765
2b04cf31
FB		 766void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs,
767 struct cxl *adapter)
f204e0b8
IM		 768{
769 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
770
771 pnv_cxl_release_hwirq_ranges(irqs, dev);
772}
773
774static int setup_cxl_bars(struct pci_dev *dev)
775{
776 /* Safety check in case we get backported to < 3.17 without M64 */
777 if ((p1_base(dev) < 0x100000000ULL) ||
778 (p2_base(dev) < 0x100000000ULL)) {
779 dev_err(&dev->dev, "ABORTING: M32 BAR assignment incompatible with CXL\n");
780 return -ENODEV;
781 }
782
783 /*
784 * BAR 4/5 has a special meaning for CXL and must be programmed with a
785 * special value corresponding to the CXL protocol address range.
f24be42a 786 * For POWER 8/9 that means bits 48:49 must be set to 10
f204e0b8
IM		 787 */
788 pci_write_config_dword(dev, PCI_BASE_ADDRESS_4, 0x00000000);
789 pci_write_config_dword(dev, PCI_BASE_ADDRESS_5, 0x00020000);
790
791 return 0;
792}
793
b0b5e591
AD		 794#ifdef CONFIG_CXL_BIMODAL
795
796struct cxl_switch_work {
797 struct pci_dev *dev;
798 struct work_struct work;
f204e0b8 799 int vsec;
b0b5e591
AD		 800 int mode;
801};
802
803static void switch_card_to_cxl(struct work_struct *work)
804{
805 struct cxl_switch_work *switch_work =
806 container_of(work, struct cxl_switch_work, work);
807 struct pci_dev *dev = switch_work->dev;
808 struct pci_bus *bus = dev->bus;
809 struct pci_controller *hose = pci_bus_to_host(bus);
810 struct pci_dev *bridge;
811 struct pnv_php_slot *php_slot;
812 unsigned int devfn;
f204e0b8
IM		 813 u8 val;
814 int rc;
815
b0b5e591
AD		 816 dev_info(&bus->dev, "cxl: Preparing for mode switch...\n");
817 bridge = list_first_entry_or_null(&hose->bus->devices, struct pci_dev,
818 bus_list);
819 if (!bridge) {
820 dev_WARN(&bus->dev, "cxl: Couldn't find root port!\n");
821 goto err_dev_put;
822 }
f204e0b8 823
b0b5e591
AD		 824 php_slot = pnv_php_find_slot(pci_device_to_OF_node(bridge));
825 if (!php_slot) {
826 dev_err(&bus->dev, "cxl: Failed to find slot hotplug "
827 "information. You may need to upgrade "
828 "skiboot. Aborting.\n");
829 goto err_dev_put;
830 }
831
832 rc = CXL_READ_VSEC_MODE_CONTROL(dev, switch_work->vsec, &val);
833 if (rc) {
834 dev_err(&bus->dev, "cxl: Failed to read CAPI mode control: %i\n", rc);
835 goto err_dev_put;
836 }
837 devfn = dev->devfn;
838
839 /* Release the reference obtained in cxl_check_and_switch_mode() */
840 pci_dev_put(dev);
841
842 dev_dbg(&bus->dev, "cxl: Removing PCI devices from kernel\n");
843 pci_lock_rescan_remove();
844 pci_hp_remove_devices(bridge->subordinate);
845 pci_unlock_rescan_remove();
846
847 /* Switch the CXL protocol on the card */
848 if (switch_work->mode == CXL_BIMODE_CXL) {
849 dev_info(&bus->dev, "cxl: Switching card to CXL mode\n");
850 val &= ~CXL_VSEC_PROTOCOL_MASK;
851 val |= CXL_VSEC_PROTOCOL_256TB | CXL_VSEC_PROTOCOL_ENABLE;
852 rc = pnv_cxl_enable_phb_kernel_api(hose, true);
853 if (rc) {
854 dev_err(&bus->dev, "cxl: Failed to enable kernel API"
855 " on real PHB, aborting\n");
856 goto err_free_work;
857 }
858 } else {
859 dev_WARN(&bus->dev, "cxl: Switching card to PCI mode not supported!\n");
860 goto err_free_work;
861 }
862
863 rc = CXL_WRITE_VSEC_MODE_CONTROL_BUS(bus, devfn, switch_work->vsec, val);
864 if (rc) {
865 dev_err(&bus->dev, "cxl: Failed to configure CXL protocol: %i\n", rc);
866 goto err_free_work;
867 }
868
869 /*
870 * The CAIA spec (v1.1, Section 10.6 Bi-modal Device Support) states
871 * we must wait 100ms after this mode switch before touching PCIe config
872 * space.
873 */
874 msleep(100);
875
876 /*
877 * Hot reset to cause the card to come back in cxl mode. A
878 * OPAL_RESET_PCI_LINK would be sufficient, but currently lacks support
879 * in skiboot, so we use a hot reset instead.
880 *
881 * We call pci_set_pcie_reset_state() on the bridge, as a CAPI card is
882 * guaranteed to sit directly under the root port, and setting the reset
883 * state on a device directly under the root port is equivalent to doing
884 * it on the root port iself.
885 */
886 dev_info(&bus->dev, "cxl: Configuration write complete, resetting card\n");
887 pci_set_pcie_reset_state(bridge, pcie_hot_reset);
888 pci_set_pcie_reset_state(bridge, pcie_deassert_reset);
889
890 dev_dbg(&bus->dev, "cxl: Offlining slot\n");
891 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_OFFLINE);
892 if (rc) {
893 dev_err(&bus->dev, "cxl: OPAL offlining call failed: %i\n", rc);
894 goto err_free_work;
895 }
896
897 dev_dbg(&bus->dev, "cxl: Onlining and probing slot\n");
898 rc = pnv_php_set_slot_power_state(&php_slot->slot, OPAL_PCI_SLOT_ONLINE);
899 if (rc) {
900 dev_err(&bus->dev, "cxl: OPAL onlining call failed: %i\n", rc);
901 goto err_free_work;
902 }
903
904 pci_lock_rescan_remove();
905 pci_hp_add_devices(bridge->subordinate);
906 pci_unlock_rescan_remove();
907
908 dev_info(&bus->dev, "cxl: CAPI mode switch completed\n");
909 kfree(switch_work);
910 return;
911
912err_dev_put:
913 /* Release the reference obtained in cxl_check_and_switch_mode() */
914 pci_dev_put(dev);
915err_free_work:
916 kfree(switch_work);
917}
918
919int cxl_check_and_switch_mode(struct pci_dev *dev, int mode, int vsec)
920{
921 struct cxl_switch_work *work;
922 u8 val;
923 int rc;
924
925 if (!cpu_has_feature(CPU_FTR_HVMODE))
f204e0b8 926 return -ENODEV;
b0b5e591
AD		 927
928 if (!vsec) {
929 vsec = find_cxl_vsec(dev);
930 if (!vsec) {
931 dev_info(&dev->dev, "CXL VSEC not found\n");
932 return -ENODEV;
933 }
f204e0b8
IM		 934 }
935
b0b5e591
AD		 936 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
937 if (rc) {
938 dev_err(&dev->dev, "Failed to read current mode control: %i", rc);
f204e0b8
IM		 939 return rc;
940 }
b0b5e591
AD		 941
942 if (mode == CXL_BIMODE_PCI) {
943 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
944 dev_info(&dev->dev, "Card is already in PCI mode\n");
945 return 0;
946 }
947 /*
948 * TODO: Before it's safe to switch the card back to PCI mode
949 * we need to disable the CAPP and make sure any cachelines the
950 * card holds have been flushed out. Needs skiboot support.
951 */
952 dev_WARN(&dev->dev, "CXL mode switch to PCI unsupported!\n");
953 return -EIO;
f204e0b8 954 }
b0b5e591
AD		 955
956 if (val & CXL_VSEC_PROTOCOL_ENABLE) {
957 dev_info(&dev->dev, "Card is already in CXL mode\n");
958 return 0;
959 }
960
961 dev_info(&dev->dev, "Card is in PCI mode, scheduling kernel thread "
962 "to switch to CXL mode\n");
963
964 work = kmalloc(sizeof(struct cxl_switch_work), GFP_KERNEL);
965 if (!work)
966 return -ENOMEM;
967
968 pci_dev_get(dev);
969 work->dev = dev;
970 work->vsec = vsec;
971 work->mode = mode;
972 INIT_WORK(&work->work, switch_card_to_cxl);
973
974 schedule_work(&work->work);
975
f204e0b8 976 /*
b0b5e591
AD		 977 * We return a failure now to abort the driver init. Once the
978 * link has been cycled and the card is in cxl mode we will
979 * come back (possibly using the generic cxl driver), but
980 * return success as the card should then be in cxl mode.
981 *
982 * TODO: What if the card comes back in PCI mode even after
983 * the switch? Don't want to spin endlessly.
f204e0b8 984 */
b0b5e591
AD		 985 return -EBUSY;
986}
987EXPORT_SYMBOL_GPL(cxl_check_and_switch_mode);
988
989#endif /* CONFIG_CXL_BIMODAL */
990
991static int setup_cxl_protocol_area(struct pci_dev *dev)
992{
993 u8 val;
994 int rc;
995 int vsec = find_cxl_vsec(dev);
996
997 if (!vsec) {
998 dev_info(&dev->dev, "CXL VSEC not found\n");
999 return -ENODEV;
1000 }
1001
1002 rc = CXL_READ_VSEC_MODE_CONTROL(dev, vsec, &val);
1003 if (rc) {
1004 dev_err(&dev->dev, "Failed to read current mode control: %i\n", rc);
1005 return rc;
1006 }
1007
1008 if (!(val & CXL_VSEC_PROTOCOL_ENABLE)) {
1009 dev_err(&dev->dev, "Card not in CAPI mode!\n");
1010 return -EIO;
1011 }
1012
1013 if ((val & CXL_VSEC_PROTOCOL_MASK) != CXL_VSEC_PROTOCOL_256TB) {
1014 val &= ~CXL_VSEC_PROTOCOL_MASK;
1015 val |= CXL_VSEC_PROTOCOL_256TB;
1016 rc = CXL_WRITE_VSEC_MODE_CONTROL(dev, vsec, val);
1017 if (rc) {
1018 dev_err(&dev->dev, "Failed to set CXL protocol area: %i\n", rc);
1019 return rc;
1020 }
1021 }
f204e0b8
IM		 1022
1023 return 0;
1024}
1025
2b04cf31 1026static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
f204e0b8
IM		 1027{
1028 u64 p1n_base, p2n_base, afu_desc;
1029 const u64 p1n_size = 0x100;
1030 const u64 p2n_size = 0x1000;
1031
1032 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
1033 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
cbffa3a5
CL		 1034 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
1035 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
f204e0b8 1036
cbffa3a5 1037 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
f204e0b8
IM		 1038 goto err;
1039 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
1040 goto err1;
1041 if (afu_desc) {
cbffa3a5 1042 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
f204e0b8
IM		 1043 goto err2;
1044 }
1045
1046 return 0;
1047err2:
1048 iounmap(afu->p2n_mmio);
1049err1:
cbffa3a5 1050 iounmap(afu->native->p1n_mmio);
f204e0b8
IM		 1051err:
1052 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
1053 return -ENOMEM;
1054}
1055
2b04cf31 1056static void pci_unmap_slice_regs(struct cxl_afu *afu)
f204e0b8 1057{
575e6986 1058 if (afu->p2n_mmio) {
f204e0b8 1059 iounmap(afu->p2n_mmio);
575e6986
DA		 1060 afu->p2n_mmio = NULL;
1061 }
cbffa3a5
CL		 1062 if (afu->native->p1n_mmio) {
1063 iounmap(afu->native->p1n_mmio);
1064 afu->native->p1n_mmio = NULL;
575e6986 1065 }
cbffa3a5
CL		 1066 if (afu->native->afu_desc_mmio) {
1067 iounmap(afu->native->afu_desc_mmio);
1068 afu->native->afu_desc_mmio = NULL;
575e6986 1069 }
f204e0b8
IM		 1070}
1071
2b04cf31 1072void cxl_pci_release_afu(struct device *dev)
f204e0b8
IM		 1073{
1074 struct cxl_afu *afu = to_cxl_afu(dev);
1075
2b04cf31 1076 pr_devel("%s\n", __func__);
f204e0b8 1077
bd664f89 1078 idr_destroy(&afu->contexts_idr);
05155772
DA		 1079 cxl_release_spa(afu);
1080
cbffa3a5 1081 kfree(afu->native);
f204e0b8
IM		 1082 kfree(afu);
1083}
1084
f204e0b8
IM		 1085/* Expects AFU struct to have recently been zeroed out */
1086static int cxl_read_afu_descriptor(struct cxl_afu *afu)
1087{
1088 u64 val;
1089
1090 val = AFUD_READ_INFO(afu);
1091 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
1092 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
b087e619 1093 afu->crs_num = AFUD_NUM_CRS(val);
f204e0b8
IM		 1094
1095 if (AFUD_AFU_DIRECTED(val))
1096 afu->modes_supported |= CXL_MODE_DIRECTED;
1097 if (AFUD_DEDICATED_PROCESS(val))
1098 afu->modes_supported |= CXL_MODE_DEDICATED;
1099 if (AFUD_TIME_SLICED(val))
1100 afu->modes_supported |= CXL_MODE_TIME_SLICED;
1101
1102 val = AFUD_READ_PPPSA(afu);
1103 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
1104 afu->psa = AFUD_PPPSA_PSA(val);
1105 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
cbffa3a5 1106 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
f204e0b8 1107
b087e619
IM		 1108 val = AFUD_READ_CR(afu);
1109 afu->crs_len = AFUD_CR_LEN(val) * 256;
1110 afu->crs_offset = AFUD_READ_CR_OFF(afu);
1111
e36f6fe1
VJ		 1112
1113 /* eb_len is in multiple of 4K */
1114 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
1115 afu->eb_offset = AFUD_READ_EB_OFF(afu);
1116
1117 /* eb_off is 4K aligned so lower 12 bits are always zero */
1118 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
1119 dev_warn(&afu->dev,
1120 "Invalid AFU error buffer offset %Lx\n",
1121 afu->eb_offset);
1122 dev_info(&afu->dev,
1123 "Ignoring AFU error buffer in the descriptor\n");
1124 /* indicate that no afu buffer exists */
1125 afu->eb_len = 0;
1126 }
1127
f204e0b8
IM		 1128 return 0;
1129}
1130
1131static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
1132{
5be587b1
FB		 1133 int i, rc;
1134 u32 val;
3d5be039 1135
f204e0b8 1136 if (afu->psa && afu->adapter->ps_size <
cbffa3a5 1137 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
f204e0b8
IM		 1138 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
1139 return -ENODEV;
1140 }
1141
1142 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
abd1d99b 1143 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
f204e0b8 1144
3d5be039 1145 for (i = 0; i < afu->crs_num; i++) {
5be587b1
FB		 1146 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
1147 if (rc || val == 0) {
3d5be039
IM		 1148 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
1149 return -EINVAL;
1150 }
1151 }
49e9c99f
IM		 1152
1153 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
1154 /*
1155 * We could also check this for the dedicated process model
1156 * since the architecture indicates it should be set to 1, but
1157 * in that case we ignore the value and I'd rather not risk
1158 * breaking any existing dedicated process AFUs that left it as
1159 * 0 (not that I'm aware of any). It is clearly an error for an
1160 * AFU directed AFU to set this to 0, and would have previously
1161 * triggered a bug resulting in the maximum not being enforced
1162 * at all since idr_alloc treats 0 as no maximum.
1163 */
1164 dev_err(&afu->dev, "AFU does not support any processes\n");
1165 return -EINVAL;
1166 }
3d5be039 1167
f204e0b8
IM		 1168 return 0;
1169}
1170
f24be42a
CL		 1171static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
1172{
1173 u64 reg;
1174
1175 /*
1176 * Clear out any regs that contain either an IVTE or address or may be
1177 * waiting on an acknowledgment to try to be a bit safer as we bring
1178 * it online
1179 */
1180 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1181 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
1182 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
1183 if (cxl_ops->afu_reset(afu))
1184 return -EIO;
1185 if (cxl_afu_disable(afu))
1186 return -EIO;
1187 if (cxl_psl_purge(afu))
1188 return -EIO;
1189 }
1190 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1191 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1192 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1193 if (reg) {
1194 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
1195 if (reg & CXL_PSL9_DSISR_An_TF)
1196 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1197 else
1198 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1199 }
1200 if (afu->adapter->native->sl_ops->register_serr_irq) {
1201 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1202 if (reg) {
1203 if (reg & ~0x000000007fffffff)
1204 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1205 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1206 }
1207 }
1208 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1209 if (reg) {
1210 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1211 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1212 }
1213
1214 return 0;
1215}
1216
64663f37 1217static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
f204e0b8
IM		 1218{
1219 u64 reg;
1220
1221 /*
1222 * Clear out any regs that contain either an IVTE or address or may be
1223 * waiting on an acknowledgement to try to be a bit safer as we bring
1224 * it online
1225 */
1226 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
1227 if ((reg & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) {
de369538 1228 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
5be587b1 1229 if (cxl_ops->afu_reset(afu))
f204e0b8
IM		 1230 return -EIO;
1231 if (cxl_afu_disable(afu))
1232 return -EIO;
1233 if (cxl_psl_purge(afu))
1234 return -EIO;
1235 }
1236 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
1237 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
1238 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
1239 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
1240 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
1241 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
1242 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
1243 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
1244 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
1245 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
1246 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
1247 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
1248 if (reg) {
de369538 1249 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
f204e0b8
IM		 1250 if (reg & CXL_PSL_DSISR_TRANS)
1251 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1252 else
1253 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1254 }
6d382616
FB		 1255 if (afu->adapter->native->sl_ops->register_serr_irq) {
1256 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1257 if (reg) {
1258 if (reg & ~0xffff)
1259 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1260 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1261 }
f204e0b8
IM		 1262 }
1263 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1264 if (reg) {
de369538 1265 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
f204e0b8
IM		 1266 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1267 }
1268
1269 return 0;
1270}
1271
e36f6fe1
VJ		 1272#define ERR_BUFF_MAX_COPY_SIZE PAGE_SIZE
1273/*
1274 * afu_eb_read:
1275 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1276 * 4/8 bytes aligned access. So in case the requested offset/count arent 8 byte
1277 * aligned the function uses a bounce buffer which can be max PAGE_SIZE.
1278 */
2b04cf31 1279ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
e36f6fe1
VJ		 1280 loff_t off, size_t count)
1281{
1282 loff_t aligned_start, aligned_end;
1283 size_t aligned_length;
1284 void *tbuf;
cbffa3a5 1285 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
e36f6fe1
VJ		 1286
1287 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1288 return 0;
1289
1290 /* calculate aligned read window */
1291 count = min((size_t)(afu->eb_len - off), count);
1292 aligned_start = round_down(off, 8);
1293 aligned_end = round_up(off + count, 8);
1294 aligned_length = aligned_end - aligned_start;
1295
1296 /* max we can copy in one read is PAGE_SIZE */
1297 if (aligned_length > ERR_BUFF_MAX_COPY_SIZE) {
1298 aligned_length = ERR_BUFF_MAX_COPY_SIZE;
1299 count = ERR_BUFF_MAX_COPY_SIZE - (off & 0x7);
1300 }
1301
1302 /* use bounce buffer for copy */
0ee931c4 1303 tbuf = (void *)__get_free_page(GFP_KERNEL);
e36f6fe1
VJ		 1304 if (!tbuf)
1305 return -ENOMEM;
1306
1307 /* perform aligned read from the mmio region */
1308 memcpy_fromio(tbuf, ebuf + aligned_start, aligned_length);
1309 memcpy(buf, tbuf + (off & 0x7), count);
1310
1311 free_page((unsigned long)tbuf);
1312
1313 return count;
1314}
1315
2b04cf31 1316static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
f204e0b8 1317{
f204e0b8
IM		 1318 int rc;
1319
2b04cf31 1320 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
d76427b0 1321 return rc;
f204e0b8 1322
bdd2e715
CL		 1323 if (adapter->native->sl_ops->sanitise_afu_regs) {
1324 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1325 if (rc)
1326 goto err1;
1327 }
f204e0b8
IM		 1328
1329 /* We need to reset the AFU before we can read the AFU descriptor */
5be587b1 1330 if ((rc = cxl_ops->afu_reset(afu)))
d76427b0 1331 goto err1;
f204e0b8
IM		 1332
1333 if (cxl_verbose)
1334 dump_afu_descriptor(afu);
1335
1336 if ((rc = cxl_read_afu_descriptor(afu)))
d76427b0 1337 goto err1;
f204e0b8
IM		 1338
1339 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
d76427b0 1340 goto err1;
f204e0b8 1341
6d382616
FB		 1342 if (adapter->native->sl_ops->afu_regs_init)
1343 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1344 goto err1;
f204e0b8 1345
6d382616
FB		 1346 if (adapter->native->sl_ops->register_serr_irq)
1347 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1348 goto err1;
f204e0b8 1349
2b04cf31 1350 if ((rc = cxl_native_register_psl_irq(afu)))
d76427b0
DA		 1351 goto err2;
1352
171ed0fc 1353 atomic_set(&afu->configured_state, 0);
d76427b0
DA		 1354 return 0;
1355
1356err2:
6d382616
FB		 1357 if (adapter->native->sl_ops->release_serr_irq)
1358 adapter->native->sl_ops->release_serr_irq(afu);
d76427b0 1359err1:
2b04cf31 1360 pci_unmap_slice_regs(afu);
d76427b0
DA		 1361 return rc;
1362}
1363
2b04cf31 1364static void pci_deconfigure_afu(struct cxl_afu *afu)
d76427b0 1365{
171ed0fc
AD		 1366 /*
1367 * It's okay to deconfigure when AFU is already locked, otherwise wait
1368 * until there are no readers
1369 */
1370 if (atomic_read(&afu->configured_state) != -1) {
1371 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1372 schedule();
1373 }
2b04cf31 1374 cxl_native_release_psl_irq(afu);
6d382616
FB		 1375 if (afu->adapter->native->sl_ops->release_serr_irq)
1376 afu->adapter->native->sl_ops->release_serr_irq(afu);
2b04cf31 1377 pci_unmap_slice_regs(afu);
d76427b0
DA		 1378}
1379
2b04cf31 1380static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev)
d76427b0
DA		 1381{
1382 struct cxl_afu *afu;
cbffa3a5 1383 int rc = -ENOMEM;
d76427b0
DA		 1384
1385 afu = cxl_alloc_afu(adapter, slice);
1386 if (!afu)
1387 return -ENOMEM;
1388
cbffa3a5
CL		 1389 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1390 if (!afu->native)
1391 goto err_free_afu;
1392
1393 mutex_init(&afu->native->spa_mutex);
1394
d76427b0
DA		 1395 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1396 if (rc)
cbffa3a5 1397 goto err_free_native;
d76427b0 1398
2b04cf31 1399 rc = pci_configure_afu(afu, adapter, dev);
d76427b0 1400 if (rc)
cbffa3a5 1401 goto err_free_native;
f204e0b8
IM		 1402
1403 /* Don't care if this fails */
1404 cxl_debugfs_afu_add(afu);
1405
1406 /*
1407 * After we call this function we must not free the afu directly, even
1408 * if it returns an error!
1409 */
1410 if ((rc = cxl_register_afu(afu)))
1411 goto err_put1;
1412
1413 if ((rc = cxl_sysfs_afu_add(afu)))
1414 goto err_put1;
1415
f204e0b8
IM		 1416 adapter->afu[afu->slice] = afu;
1417
6f7f0b3d
MN		 1418 if ((rc = cxl_pci_vphb_add(afu)))
1419 dev_info(&afu->dev, "Can't register vPHB\n");
1420
f204e0b8
IM		 1421 return 0;
1422
f204e0b8 1423err_put1:
2b04cf31 1424 pci_deconfigure_afu(afu);
f204e0b8 1425 cxl_debugfs_afu_remove(afu);
d76427b0 1426 device_unregister(&afu->dev);
f204e0b8 1427 return rc;
d76427b0 1428
cbffa3a5
CL		 1429err_free_native:
1430 kfree(afu->native);
1431err_free_afu:
d76427b0
DA		 1432 kfree(afu);
1433 return rc;
1434
f204e0b8
IM		 1435}
1436
2b04cf31 1437static void cxl_pci_remove_afu(struct cxl_afu *afu)
f204e0b8 1438{
2b04cf31 1439 pr_devel("%s\n", __func__);
f204e0b8
IM		 1440
1441 if (!afu)
1442 return;
1443
d601ea91 1444 cxl_pci_vphb_remove(afu);
f204e0b8
IM		 1445 cxl_sysfs_afu_remove(afu);
1446 cxl_debugfs_afu_remove(afu);
1447
1448 spin_lock(&afu->adapter->afu_list_lock);
1449 afu->adapter->afu[afu->slice] = NULL;
1450 spin_unlock(&afu->adapter->afu_list_lock);
1451
1452 cxl_context_detach_all(afu);
5be587b1 1453 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
f204e0b8 1454
2b04cf31 1455 pci_deconfigure_afu(afu);
f204e0b8
IM		 1456 device_unregister(&afu->dev);
1457}
1458
2b04cf31 1459int cxl_pci_reset(struct cxl *adapter)
62fa19d4
RG		 1460{
1461 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1462 int rc;
62fa19d4 1463
13e68d8b
DA		 1464 if (adapter->perst_same_image) {
1465 dev_warn(&dev->dev,
1466 "cxl: refusing to reset/reflash when perst_reloads_same_image is set.\n");
1467 return -EINVAL;
1468 }
1469
62fa19d4 1470 dev_info(&dev->dev, "CXL reset\n");
aaa2245e 1471
abd1d99b
CL		 1472 /*
1473 * The adapter is about to be reset, so ignore errors.
abd1d99b 1474 */
94322ed8 1475 cxl_data_cache_flush(adapter);
62fa19d4 1476
62fa19d4
RG		 1477 /* pcie_warm_reset requests a fundamental pci reset which includes a
1478 * PERST assert/deassert. PERST triggers a loading of the image
1479 * if "user" or "factory" is selected in sysfs */
1480 if ((rc = pci_set_pcie_reset_state(dev, pcie_warm_reset))) {
1481 dev_err(&dev->dev, "cxl: pcie_warm_reset failed\n");
1482 return rc;
1483 }
1484
62fa19d4
RG		 1485 return rc;
1486}
f204e0b8
IM		 1487
1488static int cxl_map_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
1489{
1490 if (pci_request_region(dev, 2, "priv 2 regs"))
1491 goto err1;
1492 if (pci_request_region(dev, 0, "priv 1 regs"))
1493 goto err2;
1494
de369538 1495 pr_devel("cxl_map_adapter_regs: p1: %#016llx %#llx, p2: %#016llx %#llx",
f204e0b8
IM		 1496 p1_base(dev), p1_size(dev), p2_base(dev), p2_size(dev));
1497
cbffa3a5 1498 if (!(adapter->native->p1_mmio = ioremap(p1_base(dev), p1_size(dev))))
f204e0b8
IM		 1499 goto err3;
1500
cbffa3a5 1501 if (!(adapter->native->p2_mmio = ioremap(p2_base(dev), p2_size(dev))))
f204e0b8
IM		 1502 goto err4;
1503
1504 return 0;
1505
1506err4:
cbffa3a5
CL		 1507 iounmap(adapter->native->p1_mmio);
1508 adapter->native->p1_mmio = NULL;
f204e0b8
IM		 1509err3:
1510 pci_release_region(dev, 0);
1511err2:
1512 pci_release_region(dev, 2);
1513err1:
1514 return -ENOMEM;
1515}
1516
1517static void cxl_unmap_adapter_regs(struct cxl *adapter)
1518{
cbffa3a5
CL		 1519 if (adapter->native->p1_mmio) {
1520 iounmap(adapter->native->p1_mmio);
1521 adapter->native->p1_mmio = NULL;
575e6986
DA		 1522 pci_release_region(to_pci_dev(adapter->dev.parent), 2);
1523 }
cbffa3a5
CL		 1524 if (adapter->native->p2_mmio) {
1525 iounmap(adapter->native->p2_mmio);
1526 adapter->native->p2_mmio = NULL;
575e6986
DA		 1527 pci_release_region(to_pci_dev(adapter->dev.parent), 0);
1528 }
f204e0b8
IM		 1529}
1530
1531static int cxl_read_vsec(struct cxl *adapter, struct pci_dev *dev)
1532{
1533 int vsec;
1534 u32 afu_desc_off, afu_desc_size;
1535 u32 ps_off, ps_size;
1536 u16 vseclen;
1537 u8 image_state;
1538
1539 if (!(vsec = find_cxl_vsec(dev))) {
bee30c70 1540 dev_err(&dev->dev, "ABORTING: CXL VSEC not found!\n");
f204e0b8
IM		 1541 return -ENODEV;
1542 }
1543
1544 CXL_READ_VSEC_LENGTH(dev, vsec, &vseclen);
1545 if (vseclen < CXL_VSEC_MIN_SIZE) {
bee30c70 1546 dev_err(&dev->dev, "ABORTING: CXL VSEC too short\n");
f204e0b8
IM		 1547 return -EINVAL;
1548 }
1549
1550 CXL_READ_VSEC_STATUS(dev, vsec, &adapter->vsec_status);
1551 CXL_READ_VSEC_PSL_REVISION(dev, vsec, &adapter->psl_rev);
1552 CXL_READ_VSEC_CAIA_MAJOR(dev, vsec, &adapter->caia_major);
1553 CXL_READ_VSEC_CAIA_MINOR(dev, vsec, &adapter->caia_minor);
1554 CXL_READ_VSEC_BASE_IMAGE(dev, vsec, &adapter->base_image);
1555 CXL_READ_VSEC_IMAGE_STATE(dev, vsec, &image_state);
1556 adapter->user_image_loaded = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
4beb5421 1557 adapter->perst_select_user = !!(image_state & CXL_VSEC_USER_IMAGE_LOADED);
aba81433 1558 adapter->perst_loads_image = !!(image_state & CXL_VSEC_PERST_LOADS_IMAGE);
f204e0b8
IM		 1559
1560 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices);
1561 CXL_READ_VSEC_AFU_DESC_OFF(dev, vsec, &afu_desc_off);
1562 CXL_READ_VSEC_AFU_DESC_SIZE(dev, vsec, &afu_desc_size);
1563 CXL_READ_VSEC_PS_OFF(dev, vsec, &ps_off);
1564 CXL_READ_VSEC_PS_SIZE(dev, vsec, &ps_size);
1565
1566 /* Convert everything to bytes, because there is NO WAY I'd look at the
1567 * code a month later and forget what units these are in ;-) */
cbffa3a5 1568 adapter->native->ps_off = ps_off * 64 * 1024;
f204e0b8 1569 adapter->ps_size = ps_size * 64 * 1024;
cbffa3a5
CL		 1570 adapter->native->afu_desc_off = afu_desc_off * 64 * 1024;
1571 adapter->native->afu_desc_size = afu_desc_size * 64 * 1024;
f204e0b8
IM		 1572
1573 /* Total IRQs - 1 PSL ERROR - #AFU*(1 slice error + 1 DSI) */
1574 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices;
1575
1576 return 0;
1577}
1578
d79e6801
PB		 1579/*
1580 * Workaround a PCIe Host Bridge defect on some cards, that can cause
1581 * malformed Transaction Layer Packet (TLP) errors to be erroneously
1582 * reported. Mask this error in the Uncorrectable Error Mask Register.
1583 *
1584 * The upper nibble of the PSL revision is used to distinguish between
1585 * different cards. The affected ones have it set to 0.
1586 */
1587static void cxl_fixup_malformed_tlp(struct cxl *adapter, struct pci_dev *dev)
1588{
1589 int aer;
1590 u32 data;
1591
1592 if (adapter->psl_rev & 0xf000)
1593 return;
1594 if (!(aer = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)))
1595 return;
1596 pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &data);
1597 if (data & PCI_ERR_UNC_MALF_TLP)
1598 if (data & PCI_ERR_UNC_INTN)
1599 return;
1600 data |= PCI_ERR_UNC_MALF_TLP;
1601 data |= PCI_ERR_UNC_INTN;
1602 pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, data);
1603}
1604
abd1d99b
CL		 1605static bool cxl_compatible_caia_version(struct cxl *adapter)
1606{
1607 if (cxl_is_power8() && (adapter->caia_major == 1))
1608 return true;
1609
f24be42a
CL		 1610 if (cxl_is_power9() && (adapter->caia_major == 2))
1611 return true;
1612
abd1d99b
CL		 1613 return false;
1614}
1615
f204e0b8
IM		 1616static int cxl_vsec_looks_ok(struct cxl *adapter, struct pci_dev *dev)
1617{
1618 if (adapter->vsec_status & CXL_STATUS_SECOND_PORT)
1619 return -EBUSY;
1620
1621 if (adapter->vsec_status & CXL_UNSUPPORTED_FEATURES) {
bee30c70 1622 dev_err(&dev->dev, "ABORTING: CXL requires unsupported features\n");
f204e0b8
IM		 1623 return -EINVAL;
1624 }
1625
abd1d99b
CL		 1626 if (!cxl_compatible_caia_version(adapter)) {
1627 dev_info(&dev->dev, "Ignoring card. PSL type is not supported (caia version: %d)\n",
1628 adapter->caia_major);
1629 return -ENODEV;
1630 }
1631
f204e0b8
IM		 1632 if (!adapter->slices) {
1633 /* Once we support dynamic reprogramming we can use the card if
1634 * it supports loadable AFUs */
bee30c70 1635 dev_err(&dev->dev, "ABORTING: Device has no AFUs\n");
f204e0b8
IM		 1636 return -EINVAL;
1637 }
1638
cbffa3a5 1639 if (!adapter->native->afu_desc_off || !adapter->native->afu_desc_size) {
bee30c70 1640 dev_err(&dev->dev, "ABORTING: VSEC shows no AFU descriptors\n");
f204e0b8
IM		 1641 return -EINVAL;
1642 }
1643
cbffa3a5 1644 if (adapter->ps_size > p2_size(dev) - adapter->native->ps_off) {
bee30c70 1645 dev_err(&dev->dev, "ABORTING: Problem state size larger than "
f204e0b8 1646 "available in BAR2: 0x%llx > 0x%llx\n",
cbffa3a5 1647 adapter->ps_size, p2_size(dev) - adapter->native->ps_off);
f204e0b8
IM		 1648 return -EINVAL;
1649 }
1650
1651 return 0;
1652}
1653
d601ea91
FB		 1654ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len)
1655{
1656 return pci_read_vpd(to_pci_dev(adapter->dev.parent), 0, len, buf);
1657}
1658
f204e0b8
IM		 1659static void cxl_release_adapter(struct device *dev)
1660{
1661 struct cxl *adapter = to_cxl_adapter(dev);
1662
1663 pr_devel("cxl_release_adapter\n");
1664
c044c415
DA		 1665 cxl_remove_adapter_nr(adapter);
1666
cbffa3a5 1667 kfree(adapter->native);
f204e0b8
IM		 1668 kfree(adapter);
1669}
1670
390fd592
PB		 1671#define CXL_PSL_ErrIVTE_tberror (0x1ull << (63-31))
1672
f204e0b8
IM		 1673static int sanitise_adapter_regs(struct cxl *adapter)
1674{
bdd2e715
CL		 1675 int rc = 0;
1676
390fd592
PB		 1677 /* Clear PSL tberror bit by writing 1 to it */
1678 cxl_p1_write(adapter, CXL_PSL_ErrIVTE, CXL_PSL_ErrIVTE_tberror);
bdd2e715 1679
f24be42a
CL		 1680 if (adapter->native->sl_ops->invalidate_all) {
1681 /* do not invalidate ERAT entries when not reloading on PERST */
1682 if (cxl_is_power9() && (adapter->perst_loads_image))
1683 return 0;
bdd2e715 1684 rc = adapter->native->sl_ops->invalidate_all(adapter);
f24be42a 1685 }
bdd2e715
CL		 1686
1687 return rc;
f204e0b8
IM		 1688}
1689
c044c415
DA		 1690/* This should contain *only* operations that can safely be done in
1691 * both creation and recovery.
1692 */
1693static int cxl_configure_adapter(struct cxl *adapter, struct pci_dev *dev)
f204e0b8 1694{
f204e0b8
IM		 1695 int rc;
1696
c044c415
DA		 1697 adapter->dev.parent = &dev->dev;
1698 adapter->dev.release = cxl_release_adapter;
1699 pci_set_drvdata(dev, adapter);
f204e0b8 1700
c044c415
DA		 1701 rc = pci_enable_device(dev);
1702 if (rc) {
1703 dev_err(&dev->dev, "pci_enable_device failed: %i\n", rc);
1704 return rc;
1705 }
f204e0b8 1706
bee30c70 1707 if ((rc = cxl_read_vsec(adapter, dev)))
c044c415 1708 return rc;
bee30c70
IM		 1709
1710 if ((rc = cxl_vsec_looks_ok(adapter, dev)))
c044c415 1711 return rc;
bee30c70 1712
d79e6801
PB		 1713 cxl_fixup_malformed_tlp(adapter, dev);
1714
bee30c70 1715 if ((rc = setup_cxl_bars(dev)))
c044c415 1716 return rc;
bee30c70 1717
b0b5e591 1718 if ((rc = setup_cxl_protocol_area(dev)))
c044c415 1719 return rc;
f204e0b8 1720
4beb5421 1721 if ((rc = cxl_update_image_control(adapter)))
c044c415 1722 return rc;
4beb5421 1723
f204e0b8 1724 if ((rc = cxl_map_adapter_regs(adapter, dev)))
c044c415 1725 return rc;
f204e0b8
IM		 1726
1727 if ((rc = sanitise_adapter_regs(adapter)))
c044c415 1728 goto err;
f204e0b8 1729
6d382616 1730 if ((rc = adapter->native->sl_ops->adapter_regs_init(adapter, dev)))
c044c415 1731 goto err;
f204e0b8 1732
48b3adf3
IM		 1733 /* Required for devices using CAPP DMA mode, harmless for others */
1734 pci_set_master(dev);
1735
497a0790
PB		 1736 adapter->tunneled_ops_supported = false;
1737
1738 if (cxl_is_power9()) {
401dca8c
PB		 1739 if (pnv_pci_set_tunnel_bar(dev, 0x00020000E0000000ull, 1))
1740 dev_info(&dev->dev, "Tunneled operations unsupported\n");
497a0790
PB		 1741 else
1742 adapter->tunneled_ops_supported = true;
1743 }
401dca8c 1744
b385c9e9 1745 if ((rc = pnv_phb_to_cxl_mode(dev, adapter->native->sl_ops->capi_mode)))
c044c415 1746 goto err;
f204e0b8 1747
1212aa1c
RG		 1748 /* If recovery happened, the last step is to turn on snooping.
1749 * In the non-recovery case this has no effect */
c044c415
DA		 1750 if ((rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON)))
1751 goto err;
1212aa1c 1752
e009a7e8
FB		 1753 /* Ignore error, adapter init is not dependant on timebase sync */
1754 cxl_setup_psl_timebase(adapter, dev);
390fd592 1755
2b04cf31 1756 if ((rc = cxl_native_register_psl_err_irq(adapter)))
c044c415
DA		 1757 goto err;
1758
1759 return 0;
1760
1761err:
1762 cxl_unmap_adapter_regs(adapter);
1763 return rc;
1764
1765}
1766
1767static void cxl_deconfigure_adapter(struct cxl *adapter)
1768{
1769 struct pci_dev *pdev = to_pci_dev(adapter->dev.parent);
1770
401dca8c
PB		 1771 if (cxl_is_power9())
1772 pnv_pci_set_tunnel_bar(pdev, 0x00020000E0000000ull, 0);
1773
2b04cf31 1774 cxl_native_release_psl_err_irq(adapter);
c044c415
DA		 1775 cxl_unmap_adapter_regs(adapter);
1776
1777 pci_disable_device(pdev);
1778}
1779
cbb55eeb
VJ		 1780static void cxl_stop_trace_psl9(struct cxl *adapter)
1781{
1782 int traceid;
1783 u64 trace_state, trace_mask;
1784 struct pci_dev *dev = to_pci_dev(adapter->dev.parent);
1785
1786 /* read each tracearray state and issue mmio to stop them is needed */
1787 for (traceid = 0; traceid <= CXL_PSL9_TRACEID_MAX; ++traceid) {
1788 trace_state = cxl_p1_read(adapter, CXL_PSL9_CTCCFG);
1789 trace_mask = (0x3ULL << (62 - traceid * 2));
1790 trace_state = (trace_state & trace_mask) >> (62 - traceid * 2);
1791 dev_dbg(&dev->dev, "cxl: Traceid-%d trace_state=0x%0llX\n",
1792 traceid, trace_state);
1793
1794 /* issue mmio if the trace array isn't in FIN state */
1795 if (trace_state != CXL_PSL9_TRACESTATE_FIN)
1796 cxl_p1_write(adapter, CXL_PSL9_TRACECFG,
1797 0x8400000000000000ULL | traceid);
1798 }
1799}
1800
1801static void cxl_stop_trace_psl8(struct cxl *adapter)
1802{
1803 int slice;
1804
1805 /* Stop the trace */
1806 cxl_p1_write(adapter, CXL_PSL_TRACE, 0x8000000000000017LL);
1807
1808 /* Stop the slice traces */
1809 spin_lock(&adapter->afu_list_lock);
1810 for (slice = 0; slice < adapter->slices; slice++) {
1811 if (adapter->afu[slice])
1812 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1813 0x8000000000000000LL);
1814 }
1815 spin_unlock(&adapter->afu_list_lock);
1816}
1817
f24be42a
CL		 1818static const struct cxl_service_layer_ops psl9_ops = {
1819 .adapter_regs_init = init_implementation_adapter_regs_psl9,
1820 .invalidate_all = cxl_invalidate_all_psl9,
1821 .afu_regs_init = init_implementation_afu_regs_psl9,
1822 .sanitise_afu_regs = sanitise_afu_regs_psl9,
6d382616
FB		 1823 .register_serr_irq = cxl_native_register_serr_irq,
1824 .release_serr_irq = cxl_native_release_serr_irq,
f24be42a
CL		 1825 .handle_interrupt = cxl_irq_psl9,
1826 .fail_irq = cxl_fail_irq_psl,
1827 .activate_dedicated_process = cxl_activate_dedicated_process_psl9,
1828 .attach_afu_directed = cxl_attach_afu_directed_psl9,
1829 .attach_dedicated_process = cxl_attach_dedicated_process_psl9,
1830 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl9,
1831 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl9,
1832 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl9,
1833 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl9,
990f19ae 1834 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl9,
f24be42a 1835 .debugfs_stop_trace = cxl_stop_trace_psl9,
f24be42a
CL		 1836 .timebase_read = timebase_read_psl9,
1837 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
1838 .needs_reset_before_disable = true,
1839};
1840
64663f37
CL		 1841static const struct cxl_service_layer_ops psl8_ops = {
1842 .adapter_regs_init = init_implementation_adapter_regs_psl8,
1843 .invalidate_all = cxl_invalidate_all_psl8,
1844 .afu_regs_init = init_implementation_afu_regs_psl8,
1845 .sanitise_afu_regs = sanitise_afu_regs_psl8,
6d382616
FB		 1846 .register_serr_irq = cxl_native_register_serr_irq,
1847 .release_serr_irq = cxl_native_release_serr_irq,
64663f37 1848 .handle_interrupt = cxl_irq_psl8,
bdd2e715 1849 .fail_irq = cxl_fail_irq_psl,
64663f37
CL		 1850 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1851 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1852 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1853 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
1854 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_psl8,
1855 .debugfs_add_afu_regs = cxl_debugfs_add_afu_regs_psl8,
1856 .psl_irq_dump_registers = cxl_native_irq_dump_regs_psl8,
990f19ae 1857 .err_irq_dump_registers = cxl_native_err_irq_dump_regs_psl8,
64663f37
CL		 1858 .debugfs_stop_trace = cxl_stop_trace_psl8,
1859 .write_timebase_ctrl = write_timebase_ctrl_psl8,
1860 .timebase_read = timebase_read_psl8,
b385c9e9 1861 .capi_mode = OPAL_PHB_CAPI_MODE_CAPI,
5e7823c9 1862 .needs_reset_before_disable = true,
6d382616
FB		 1863};
1864
1865static const struct cxl_service_layer_ops xsl_ops = {
bdd2e715 1866 .adapter_regs_init = init_implementation_adapter_regs_xsl,
64663f37
CL		 1867 .invalidate_all = cxl_invalidate_all_psl8,
1868 .sanitise_afu_regs = sanitise_afu_regs_psl8,
1869 .handle_interrupt = cxl_irq_psl8,
bdd2e715 1870 .fail_irq = cxl_fail_irq_psl,
64663f37
CL		 1871 .activate_dedicated_process = cxl_activate_dedicated_process_psl8,
1872 .attach_afu_directed = cxl_attach_afu_directed_psl8,
1873 .attach_dedicated_process = cxl_attach_dedicated_process_psl8,
1874 .update_dedicated_ivtes = cxl_update_dedicated_ivtes_psl8,
bdd2e715 1875 .debugfs_add_adapter_regs = cxl_debugfs_add_adapter_regs_xsl,
6d382616
FB		 1876 .write_timebase_ctrl = write_timebase_ctrl_xsl,
1877 .timebase_read = timebase_read_xsl,
b385c9e9 1878 .capi_mode = OPAL_PHB_CAPI_MODE_DMA,
6d382616
FB		 1879};
1880
1881static void set_sl_ops(struct cxl *adapter, struct pci_dev *dev)
1882{
1883 if (dev->vendor == PCI_VENDOR_ID_MELLANOX && dev->device == 0x1013) {
16479337 1884 /* Mellanox CX-4 */
b135077b 1885 dev_info(&dev->dev, "Device uses an XSL\n");
6d382616 1886 adapter->native->sl_ops = &xsl_ops;
16479337 1887 adapter->min_pe = 1; /* Workaround for CX-4 hardware bug */
6d382616 1888 } else {
abd1d99b
CL		 1889 if (cxl_is_power8()) {
1890 dev_info(&dev->dev, "Device uses a PSL8\n");
1891 adapter->native->sl_ops = &psl8_ops;
f24be42a
CL		 1892 } else {
1893 dev_info(&dev->dev, "Device uses a PSL9\n");
1894 adapter->native->sl_ops = &psl9_ops;
abd1d99b 1895 }
6d382616
FB		 1896 }
1897}
1898
1899
2b04cf31 1900static struct cxl *cxl_pci_init_adapter(struct pci_dev *dev)
c044c415
DA		 1901{
1902 struct cxl *adapter;
1903 int rc;
1904
1905 adapter = cxl_alloc_adapter();
1906 if (!adapter)
1907 return ERR_PTR(-ENOMEM);
1908
cbffa3a5
CL		 1909 adapter->native = kzalloc(sizeof(struct cxl_native), GFP_KERNEL);
1910 if (!adapter->native) {
1911 rc = -ENOMEM;
1912 goto err_release;
1913 }
1914
6d382616
FB		 1915 set_sl_ops(adapter, dev);
1916
c044c415
DA		 1917 /* Set defaults for parameters which need to persist over
1918 * configure/reconfigure
1919 */
1920 adapter->perst_loads_image = true;
13e68d8b 1921 adapter->perst_same_image = false;
c044c415
DA		 1922
1923 rc = cxl_configure_adapter(adapter, dev);
1924 if (rc) {
1925 pci_disable_device(dev);
cbffa3a5 1926 goto err_release;
c044c415 1927 }
f204e0b8
IM		 1928
1929 /* Don't care if this one fails: */
1930 cxl_debugfs_adapter_add(adapter);
1931
1932 /*
1933 * After we call this function we must not free the adapter directly,
1934 * even if it returns an error!
1935 */
1936 if ((rc = cxl_register_adapter(adapter)))
1937 goto err_put1;
1938
1939 if ((rc = cxl_sysfs_adapter_add(adapter)))
1940 goto err_put1;
1941
ea9a26d1
VJ		 1942 /* Release the context lock as adapter is configured */
1943 cxl_adapter_context_unlock(adapter);
1944
f204e0b8
IM		 1945 return adapter;
1946
1947err_put1:
c044c415
DA		 1948 /* This should mirror cxl_remove_adapter, except without the
1949 * sysfs parts
1950 */
f204e0b8 1951 cxl_debugfs_adapter_remove(adapter);
c044c415
DA		 1952 cxl_deconfigure_adapter(adapter);
1953 device_unregister(&adapter->dev);
f204e0b8 1954 return ERR_PTR(rc);
cbffa3a5
CL		 1955
1956err_release:
1957 cxl_release_adapter(&adapter->dev);
1958 return ERR_PTR(rc);
f204e0b8
IM		 1959}
1960
2b04cf31 1961static void cxl_pci_remove_adapter(struct cxl *adapter)
f204e0b8 1962{
c044c415 1963 pr_devel("cxl_remove_adapter\n");
f204e0b8
IM		 1964
1965 cxl_sysfs_adapter_remove(adapter);
1966 cxl_debugfs_adapter_remove(adapter);
f204e0b8 1967
f24be42a
CL		 1968 /*
1969 * Flush adapter datacache as its about to be removed.
f24be42a 1970 */
94322ed8 1971 cxl_data_cache_flush(adapter);
d7b1946c 1972
c044c415 1973 cxl_deconfigure_adapter(adapter);
f204e0b8 1974
c044c415 1975 device_unregister(&adapter->dev);
f204e0b8
IM		 1976}
1977
3b3dcd61
PB		 1978#define CXL_MAX_PCIEX_PARENT 2
1979
3ced8d73 1980int cxl_slot_is_switched(struct pci_dev *dev)
3b3dcd61
PB		 1981{
1982 struct device_node *np;
1983 int depth = 0;
1984 const __be32 *prop;
1985
1986 if (!(np = pci_device_to_OF_node(dev))) {
1987 pr_err("cxl: np = NULL\n");
1988 return -ENODEV;
1989 }
1990 of_node_get(np);
1991 while (np) {
1992 np = of_get_next_parent(np);
1993 prop = of_get_property(np, "device_type", NULL);
1994 if (!prop || strcmp((char *)prop, "pciex"))
1995 break;
1996 depth++;
1997 }
1998 of_node_put(np);
1999 return (depth > CXL_MAX_PCIEX_PARENT);
2000}
2001
4e56f858
IM		 2002bool cxl_slot_is_supported(struct pci_dev *dev, int flags)
2003{
2004 if (!cpu_has_feature(CPU_FTR_HVMODE))
2005 return false;
2006
2007 if ((flags & CXL_SLOT_FLAG_DMA) && (!pvr_version_is(PVR_POWER8NVL))) {
2008 /*
2009 * CAPP DMA mode is technically supported on regular P8, but
2010 * will EEH if the card attempts to access memory < 4GB, which
2011 * we cannot realistically avoid. We might be able to work
2012 * around the issue, but until then return unsupported:
2013 */
2014 return false;
2015 }
2016
2017 if (cxl_slot_is_switched(dev))
2018 return false;
2019
2020 /*
2021 * XXX: This gets a little tricky on regular P8 (not POWER8NVL) since
2022 * the CAPP can be connected to PHB 0, 1 or 2 on a first come first
2023 * served basis, which is racy to check from here. If we need to
2024 * support this in future we might need to consider having this
2025 * function effectively reserve it ahead of time.
2026 *
2027 * Currently, the only user of this API is the Mellanox CX4, which is
2028 * only supported on P8NVL due to the above mentioned limitation of
2029 * CAPP DMA mode and therefore does not need to worry about this. If the
2030 * issue with CAPP DMA mode is later worked around on P8 we might need
2031 * to revisit this.
2032 */
2033
2034 return true;
2035}
2036EXPORT_SYMBOL_GPL(cxl_slot_is_supported);
2037
2038
f204e0b8
IM		 2039static int cxl_probe(struct pci_dev *dev, const struct pci_device_id *id)
2040{
2041 struct cxl *adapter;
2042 int slice;
2043 int rc;
2044
17eb3eef
VJ		 2045 if (cxl_pci_is_vphb_device(dev)) {
2046 dev_dbg(&dev->dev, "cxl_init_adapter: Ignoring cxl vphb device\n");
2047 return -ENODEV;
2048 }
2049
3b3dcd61
PB		 2050 if (cxl_slot_is_switched(dev)) {
2051 dev_info(&dev->dev, "Ignoring card on incompatible PCI slot\n");
2052 return -ENODEV;
2053 }
2054
f24be42a
CL		 2055 if (cxl_is_power9() && !radix_enabled()) {
2056 dev_info(&dev->dev, "Only Radix mode supported\n");
2057 return -ENODEV;
2058 }
2059
f204e0b8
IM		 2060 if (cxl_verbose)
2061 dump_cxl_config_space(dev);
2062
2b04cf31 2063 adapter = cxl_pci_init_adapter(dev);
f204e0b8
IM		 2064 if (IS_ERR(adapter)) {
2065 dev_err(&dev->dev, "cxl_init_adapter failed: %li\n", PTR_ERR(adapter));
2066 return PTR_ERR(adapter);
2067 }
2068
2069 for (slice = 0; slice < adapter->slices; slice++) {
2b04cf31 2070 if ((rc = pci_init_afu(adapter, slice, dev))) {
f204e0b8 2071 dev_err(&dev->dev, "AFU %i failed to initialise: %i\n", slice, rc);
d76427b0
DA		 2072 continue;
2073 }
2074
2075 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
2076 if (rc)
2077 dev_err(&dev->dev, "AFU %i failed to start: %i\n", slice, rc);
f204e0b8
IM		 2078 }
2079
317f5ef1
IM		 2080 if (pnv_pci_on_cxl_phb(dev) && adapter->slices >= 1)
2081 pnv_cxl_phb_set_peer_afu(dev, adapter->afu[0]);
2082
f204e0b8
IM		 2083 return 0;
2084}
2085
2086static void cxl_remove(struct pci_dev *dev)
2087{
2088 struct cxl *adapter = pci_get_drvdata(dev);
6f7f0b3d
MN		 2089 struct cxl_afu *afu;
2090 int i;
f204e0b8 2091
f204e0b8
IM		 2092 /*
2093 * Lock to prevent someone grabbing a ref through the adapter list as
2094 * we are removing it
2095 */
6f7f0b3d
MN		 2096 for (i = 0; i < adapter->slices; i++) {
2097 afu = adapter->afu[i];
2b04cf31 2098 cxl_pci_remove_afu(afu);
6f7f0b3d 2099 }
2b04cf31 2100 cxl_pci_remove_adapter(adapter);
f204e0b8
IM		 2101}
2102
9e8df8a2
DA		 2103static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
2104 pci_channel_state_t state)
2105{
2106 struct pci_dev *afu_dev;
2107 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET;
2108 pci_ers_result_t afu_result = PCI_ERS_RESULT_NEED_RESET;
2109
2110 /* There should only be one entry, but go through the list
2111 * anyway
2112 */
12841f87
VJ		 2113 if (afu->phb == NULL)
2114 return result;
2115
9e8df8a2
DA		 2116 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2117 if (!afu_dev->driver)
2118 continue;
2119
2120 afu_dev->error_state = state;
2121
2122 if (afu_dev->driver->err_handler)
2123 afu_result = afu_dev->driver->err_handler->error_detected(afu_dev,
2124 state);
2125 /* Disconnect trumps all, NONE trumps NEED_RESET */
2126 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2127 result = PCI_ERS_RESULT_DISCONNECT;
2128 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2129 (result == PCI_ERS_RESULT_NEED_RESET))
2130 result = PCI_ERS_RESULT_NONE;
2131 }
2132 return result;
2133}
2134
2135static pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
2136 pci_channel_state_t state)
2137{
2138 struct cxl *adapter = pci_get_drvdata(pdev);
2139 struct cxl_afu *afu;
4f58f0bf 2140 pci_ers_result_t result = PCI_ERS_RESULT_NEED_RESET, afu_result;
9e8df8a2
DA		 2141 int i;
2142
2143 /* At this point, we could still have an interrupt pending.
2144 * Let's try to get them out of the way before they do
2145 * anything we don't like.
2146 */
2147 schedule();
2148
2149 /* If we're permanently dead, give up. */
2150 if (state == pci_channel_io_perm_failure) {
9e8df8a2
DA		 2151 for (i = 0; i < adapter->slices; i++) {
2152 afu = adapter->afu[i];
07f5ab60
VJ		 2153 /*
2154 * Tell the AFU drivers; but we don't care what they
2155 * say, we're going away.
2156 */
12841f87 2157 cxl_vphb_error_detected(afu, state);
9e8df8a2
DA		 2158 }
2159 return PCI_ERS_RESULT_DISCONNECT;
2160 }
2161
2162 /* Are we reflashing?
2163 *
2164 * If we reflash, we could come back as something entirely
2165 * different, including a non-CAPI card. As such, by default
2166 * we don't participate in the process. We'll be unbound and
2167 * the slot re-probed. (TODO: check EEH doesn't blindly rebind
2168 * us!)
2169 *
2170 * However, this isn't the entire story: for reliablity
2171 * reasons, we usually want to reflash the FPGA on PERST in
2172 * order to get back to a more reliable known-good state.
2173 *
2174 * This causes us a bit of a problem: if we reflash we can't
2175 * trust that we'll come back the same - we could have a new
2176 * image and been PERSTed in order to load that
2177 * image. However, most of the time we actually *will* come
2178 * back the same - for example a regular EEH event.
2179 *
2180 * Therefore, we allow the user to assert that the image is
2181 * indeed the same and that we should continue on into EEH
2182 * anyway.
2183 */
2184 if (adapter->perst_loads_image && !adapter->perst_same_image) {
2185 /* TODO take the PHB out of CXL mode */
2186 dev_info(&pdev->dev, "reflashing, so opting out of EEH!\n");
2187 return PCI_ERS_RESULT_NONE;
2188 }
2189
2190 /*
2191 * At this point, we want to try to recover. We'll always
2192 * need a complete slot reset: we don't trust any other reset.
2193 *
2194 * Now, we go through each AFU:
2195 * - We send the driver, if bound, an error_detected callback.
2196 * We expect it to clean up, but it can also tell us to give
2197 * up and permanently detach the card. To simplify things, if
2198 * any bound AFU driver doesn't support EEH, we give up on EEH.
2199 *
2200 * - We detach all contexts associated with the AFU. This
2201 * does not free them, but puts them into a CLOSED state
2202 * which causes any the associated files to return useful
2203 * errors to userland. It also unmaps, but does not free,
2204 * any IRQs.
2205 *
2206 * - We clean up our side: releasing and unmapping resources we hold
2207 * so we can wire them up again when the hardware comes back up.
2208 *
2209 * Driver authors should note:
2210 *
2211 * - Any contexts you create in your kernel driver (except
2212 * those associated with anonymous file descriptors) are
2213 * your responsibility to free and recreate. Likewise with
2214 * any attached resources.
2215 *
2216 * - We will take responsibility for re-initialising the
2217 * device context (the one set up for you in
2218 * cxl_pci_enable_device_hook and accessed through
2219 * cxl_get_context). If you've attached IRQs or other
2220 * resources to it, they remains yours to free.
2221 *
2222 * You can call the same functions to release resources as you
2223 * normally would: we make sure that these functions continue
2224 * to work when the hardware is down.
2225 *
2226 * Two examples:
2227 *
2228 * 1) If you normally free all your resources at the end of
2229 * each request, or if you use anonymous FDs, your
2230 * error_detected callback can simply set a flag to tell
2231 * your driver not to start any new calls. You can then
2232 * clear the flag in the resume callback.
2233 *
2234 * 2) If you normally allocate your resources on startup:
2235 * * Set a flag in error_detected as above.
2236 * * Let CXL detach your contexts.
2237 * * In slot_reset, free the old resources and allocate new ones.
2238 * * In resume, clear the flag to allow things to start.
2239 */
2240 for (i = 0; i < adapter->slices; i++) {
2241 afu = adapter->afu[i];
2242
4f58f0bf 2243 afu_result = cxl_vphb_error_detected(afu, state);
9e8df8a2
DA		 2244
2245 cxl_context_detach_all(afu);
5be587b1 2246 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
2b04cf31 2247 pci_deconfigure_afu(afu);
4f58f0bf
VJ		 2248
2249 /* Disconnect trumps all, NONE trumps NEED_RESET */
2250 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2251 result = PCI_ERS_RESULT_DISCONNECT;
2252 else if ((afu_result == PCI_ERS_RESULT_NONE) &&
2253 (result == PCI_ERS_RESULT_NEED_RESET))
2254 result = PCI_ERS_RESULT_NONE;
9e8df8a2 2255 }
ea9a26d1
VJ		 2256
2257 /* should take the context lock here */
2258 if (cxl_adapter_context_lock(adapter) != 0)
2259 dev_warn(&adapter->dev,
2260 "Couldn't take context lock with %d active-contexts\n",
2261 atomic_read(&adapter->contexts_num));
2262
9e8df8a2
DA		 2263 cxl_deconfigure_adapter(adapter);
2264
2265 return result;
2266}
2267
2268static pci_ers_result_t cxl_pci_slot_reset(struct pci_dev *pdev)
2269{
2270 struct cxl *adapter = pci_get_drvdata(pdev);
2271 struct cxl_afu *afu;
2272 struct cxl_context *ctx;
2273 struct pci_dev *afu_dev;
2274 pci_ers_result_t afu_result = PCI_ERS_RESULT_RECOVERED;
2275 pci_ers_result_t result = PCI_ERS_RESULT_RECOVERED;
2276 int i;
2277
2278 if (cxl_configure_adapter(adapter, pdev))
2279 goto err;
2280
ea9a26d1
VJ		 2281 /*
2282 * Unlock context activation for the adapter. Ideally this should be
2283 * done in cxl_pci_resume but cxlflash module tries to activate the
2284 * master context as part of slot_reset callback.
2285 */
2286 cxl_adapter_context_unlock(adapter);
2287
9e8df8a2
DA		 2288 for (i = 0; i < adapter->slices; i++) {
2289 afu = adapter->afu[i];
2290
2b04cf31 2291 if (pci_configure_afu(afu, adapter, pdev))
9e8df8a2
DA		 2292 goto err;
2293
2294 if (cxl_afu_select_best_mode(afu))
2295 goto err;
2296
12841f87
VJ		 2297 if (afu->phb == NULL)
2298 continue;
2299
9e8df8a2
DA		 2300 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2301 /* Reset the device context.
2302 * TODO: make this less disruptive
2303 */
2304 ctx = cxl_get_context(afu_dev);
2305
2306 if (ctx && cxl_release_context(ctx))
2307 goto err;
2308
2309 ctx = cxl_dev_context_init(afu_dev);
bb81733d 2310 if (IS_ERR(ctx))
9e8df8a2
DA		 2311 goto err;
2312
2313 afu_dev->dev.archdata.cxl_ctx = ctx;
2314
5be587b1 2315 if (cxl_ops->afu_check_and_enable(afu))
9e8df8a2
DA		 2316 goto err;
2317
2318 afu_dev->error_state = pci_channel_io_normal;
2319
2320 /* If there's a driver attached, allow it to
2321 * chime in on recovery. Drivers should check
2322 * if everything has come back OK, but
2323 * shouldn't start new work until we call
2324 * their resume function.
2325 */
2326 if (!afu_dev->driver)
2327 continue;
2328
2329 if (afu_dev->driver->err_handler &&
2330 afu_dev->driver->err_handler->slot_reset)
2331 afu_result = afu_dev->driver->err_handler->slot_reset(afu_dev);
2332
2333 if (afu_result == PCI_ERS_RESULT_DISCONNECT)
2334 result = PCI_ERS_RESULT_DISCONNECT;
2335 }
2336 }
2337 return result;
2338
2339err:
2340 /* All the bits that happen in both error_detected and cxl_remove
2341 * should be idempotent, so we don't need to worry about leaving a mix
2342 * of unconfigured and reconfigured resources.
2343 */
2344 dev_err(&pdev->dev, "EEH recovery failed. Asking to be disconnected.\n");
2345 return PCI_ERS_RESULT_DISCONNECT;
2346}
2347
2348static void cxl_pci_resume(struct pci_dev *pdev)
2349{
2350 struct cxl *adapter = pci_get_drvdata(pdev);
2351 struct cxl_afu *afu;
2352 struct pci_dev *afu_dev;
2353 int i;
2354
2355 /* Everything is back now. Drivers should restart work now.
2356 * This is not the place to be checking if everything came back up
2357 * properly, because there's no return value: do that in slot_reset.
2358 */
2359 for (i = 0; i < adapter->slices; i++) {
2360 afu = adapter->afu[i];
2361
12841f87
VJ		 2362 if (afu->phb == NULL)
2363 continue;
2364
9e8df8a2
DA		 2365 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2366 if (afu_dev->driver && afu_dev->driver->err_handler &&
2367 afu_dev->driver->err_handler->resume)
2368 afu_dev->driver->err_handler->resume(afu_dev);
2369 }
2370 }
2371}
2372
2373static const struct pci_error_handlers cxl_err_handler = {
2374 .error_detected = cxl_pci_error_detected,
2375 .slot_reset = cxl_pci_slot_reset,
2376 .resume = cxl_pci_resume,
2377};
2378
f204e0b8
IM		 2379struct pci_driver cxl_pci_driver = {
2380 .name = "cxl-pci",
2381 .id_table = cxl_pci_tbl,
2382 .probe = cxl_probe,
2383 .remove = cxl_remove,
aa70775e 2384 .shutdown = cxl_remove,
9e8df8a2 2385 .err_handler = &cxl_err_handler,
f204e0b8 2386};
Linux 6.x block layer and io_uring tree(s)