Commit | Line | Data |
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f204e0b8 IM |
1 | /* |
2 | * Copyright 2014 IBM Corp. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version | |
7 | * 2 of the License, or (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/spinlock.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/mutex.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/uaccess.h> | |
2bc79ffc | 17 | #include <linux/delay.h> |
f204e0b8 | 18 | #include <asm/synch.h> |
ec249dd8 | 19 | #include <misc/cxl-base.h> |
f204e0b8 IM |
20 | |
21 | #include "cxl.h" | |
9bcf28cd | 22 | #include "trace.h" |
f204e0b8 | 23 | |
5e7823c9 | 24 | static int afu_control(struct cxl_afu *afu, u64 command, u64 clear, |
f204e0b8 IM |
25 | u64 result, u64 mask, bool enabled) |
26 | { | |
5e7823c9 | 27 | u64 AFU_Cntl; |
f204e0b8 | 28 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd | 29 | int rc = 0; |
f204e0b8 IM |
30 | |
31 | spin_lock(&afu->afu_cntl_lock); | |
32 | pr_devel("AFU command starting: %llx\n", command); | |
33 | ||
9bcf28cd IM |
34 | trace_cxl_afu_ctrl(afu, command); |
35 | ||
5e7823c9 IM |
36 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); |
37 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, (AFU_Cntl & ~clear) | command); | |
f204e0b8 IM |
38 | |
39 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
40 | while ((AFU_Cntl & mask) != result) { | |
41 | if (time_after_eq(jiffies, timeout)) { | |
42 | dev_warn(&afu->dev, "WARNING: AFU control timed out!\n"); | |
9bcf28cd IM |
43 | rc = -EBUSY; |
44 | goto out; | |
f204e0b8 | 45 | } |
0b3f9c75 | 46 | |
0d400f77 | 47 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
48 | afu->enabled = enabled; |
49 | rc = -EIO; | |
50 | goto out; | |
51 | } | |
52 | ||
de369538 | 53 | pr_devel_ratelimited("AFU control... (0x%016llx)\n", |
f204e0b8 IM |
54 | AFU_Cntl | command); |
55 | cpu_relax(); | |
56 | AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
57 | }; | |
2a4f667a IM |
58 | |
59 | if (AFU_Cntl & CXL_AFU_Cntl_An_RA) { | |
60 | /* | |
61 | * Workaround for a bug in the XSL used in the Mellanox CX4 | |
62 | * that fails to clear the RA bit after an AFU reset, | |
63 | * preventing subsequent AFU resets from working. | |
64 | */ | |
65 | cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA); | |
66 | } | |
67 | ||
f204e0b8 IM |
68 | pr_devel("AFU command complete: %llx\n", command); |
69 | afu->enabled = enabled; | |
9bcf28cd IM |
70 | out: |
71 | trace_cxl_afu_ctrl_done(afu, command, rc); | |
f204e0b8 IM |
72 | spin_unlock(&afu->afu_cntl_lock); |
73 | ||
9bcf28cd | 74 | return rc; |
f204e0b8 IM |
75 | } |
76 | ||
77 | static int afu_enable(struct cxl_afu *afu) | |
78 | { | |
79 | pr_devel("AFU enable request\n"); | |
80 | ||
5e7823c9 | 81 | return afu_control(afu, CXL_AFU_Cntl_An_E, 0, |
f204e0b8 IM |
82 | CXL_AFU_Cntl_An_ES_Enabled, |
83 | CXL_AFU_Cntl_An_ES_MASK, true); | |
84 | } | |
85 | ||
86 | int cxl_afu_disable(struct cxl_afu *afu) | |
87 | { | |
88 | pr_devel("AFU disable request\n"); | |
89 | ||
5e7823c9 IM |
90 | return afu_control(afu, 0, CXL_AFU_Cntl_An_E, |
91 | CXL_AFU_Cntl_An_ES_Disabled, | |
f204e0b8 IM |
92 | CXL_AFU_Cntl_An_ES_MASK, false); |
93 | } | |
94 | ||
95 | /* This will disable as well as reset */ | |
2b04cf31 | 96 | static int native_afu_reset(struct cxl_afu *afu) |
f204e0b8 IM |
97 | { |
98 | pr_devel("AFU reset request\n"); | |
99 | ||
5e7823c9 | 100 | return afu_control(afu, CXL_AFU_Cntl_An_RA, 0, |
f204e0b8 IM |
101 | CXL_AFU_Cntl_An_RS_Complete | CXL_AFU_Cntl_An_ES_Disabled, |
102 | CXL_AFU_Cntl_An_RS_MASK | CXL_AFU_Cntl_An_ES_MASK, | |
103 | false); | |
104 | } | |
105 | ||
2b04cf31 | 106 | static int native_afu_check_and_enable(struct cxl_afu *afu) |
f204e0b8 | 107 | { |
0d400f77 | 108 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
109 | WARN(1, "Refusing to enable afu while link down!\n"); |
110 | return -EIO; | |
111 | } | |
f204e0b8 IM |
112 | if (afu->enabled) |
113 | return 0; | |
114 | return afu_enable(afu); | |
115 | } | |
116 | ||
117 | int cxl_psl_purge(struct cxl_afu *afu) | |
118 | { | |
119 | u64 PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
120 | u64 AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An); | |
121 | u64 dsisr, dar; | |
122 | u64 start, end; | |
123 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
9bcf28cd IM |
124 | int rc = 0; |
125 | ||
126 | trace_cxl_psl_ctrl(afu, CXL_PSL_SCNTL_An_Pc); | |
f204e0b8 IM |
127 | |
128 | pr_devel("PSL purge request\n"); | |
129 | ||
0d400f77 | 130 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
131 | dev_warn(&afu->dev, "PSL Purge called with link down, ignoring\n"); |
132 | rc = -EIO; | |
133 | goto out; | |
134 | } | |
135 | ||
f204e0b8 IM |
136 | if ((AFU_Cntl & CXL_AFU_Cntl_An_ES_MASK) != CXL_AFU_Cntl_An_ES_Disabled) { |
137 | WARN(1, "psl_purge request while AFU not disabled!\n"); | |
138 | cxl_afu_disable(afu); | |
139 | } | |
140 | ||
141 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
142 | PSL_CNTL | CXL_PSL_SCNTL_An_Pc); | |
143 | start = local_clock(); | |
144 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
145 | while ((PSL_CNTL & CXL_PSL_SCNTL_An_Ps_MASK) | |
146 | == CXL_PSL_SCNTL_An_Ps_Pending) { | |
147 | if (time_after_eq(jiffies, timeout)) { | |
148 | dev_warn(&afu->dev, "WARNING: PSL Purge timed out!\n"); | |
9bcf28cd IM |
149 | rc = -EBUSY; |
150 | goto out; | |
f204e0b8 | 151 | } |
0d400f77 | 152 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
153 | rc = -EIO; |
154 | goto out; | |
155 | } | |
156 | ||
f204e0b8 | 157 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
de369538 | 158 | pr_devel_ratelimited("PSL purging... PSL_CNTL: 0x%016llx PSL_DSISR: 0x%016llx\n", PSL_CNTL, dsisr); |
f204e0b8 IM |
159 | if (dsisr & CXL_PSL_DSISR_TRANS) { |
160 | dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
de369538 | 161 | dev_notice(&afu->dev, "PSL purge terminating pending translation, DSISR: 0x%016llx, DAR: 0x%016llx\n", dsisr, dar); |
f204e0b8 IM |
162 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); |
163 | } else if (dsisr) { | |
de369538 | 164 | dev_notice(&afu->dev, "PSL purge acknowledging pending non-translation fault, DSISR: 0x%016llx\n", dsisr); |
f204e0b8 IM |
165 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); |
166 | } else { | |
167 | cpu_relax(); | |
168 | } | |
169 | PSL_CNTL = cxl_p1n_read(afu, CXL_PSL_SCNTL_An); | |
170 | }; | |
171 | end = local_clock(); | |
172 | pr_devel("PSL purged in %lld ns\n", end - start); | |
173 | ||
174 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, | |
175 | PSL_CNTL & ~CXL_PSL_SCNTL_An_Pc); | |
9bcf28cd IM |
176 | out: |
177 | trace_cxl_psl_ctrl_done(afu, CXL_PSL_SCNTL_An_Pc, rc); | |
178 | return rc; | |
f204e0b8 IM |
179 | } |
180 | ||
181 | static int spa_max_procs(int spa_size) | |
182 | { | |
183 | /* | |
184 | * From the CAIA: | |
185 | * end_of_SPA_area = SPA_Base + ((n+4) * 128) + (( ((n*8) + 127) >> 7) * 128) + 255 | |
186 | * Most of that junk is really just an overly-complicated way of saying | |
187 | * the last 256 bytes are __aligned(128), so it's really: | |
188 | * end_of_SPA_area = end_of_PSL_queue_area + __aligned(128) 255 | |
189 | * and | |
190 | * end_of_PSL_queue_area = SPA_Base + ((n+4) * 128) + (n*8) - 1 | |
191 | * so | |
192 | * sizeof(SPA) = ((n+4) * 128) + (n*8) + __aligned(128) 256 | |
193 | * Ignore the alignment (which is safe in this case as long as we are | |
194 | * careful with our rounding) and solve for n: | |
195 | */ | |
196 | return ((spa_size / 8) - 96) / 17; | |
197 | } | |
198 | ||
05155772 | 199 | int cxl_alloc_spa(struct cxl_afu *afu) |
f204e0b8 | 200 | { |
895a7980 IM |
201 | unsigned spa_size; |
202 | ||
f204e0b8 | 203 | /* Work out how many pages to allocate */ |
2224b671 | 204 | afu->native->spa_order = -1; |
f204e0b8 | 205 | do { |
cbffa3a5 | 206 | afu->native->spa_order++; |
895a7980 IM |
207 | spa_size = (1 << afu->native->spa_order) * PAGE_SIZE; |
208 | ||
209 | if (spa_size > 0x100000) { | |
210 | dev_warn(&afu->dev, "num_of_processes too large for the SPA, limiting to %i (0x%x)\n", | |
211 | afu->native->spa_max_procs, afu->native->spa_size); | |
212 | afu->num_procs = afu->native->spa_max_procs; | |
213 | break; | |
214 | } | |
215 | ||
216 | afu->native->spa_size = spa_size; | |
cbffa3a5 CL |
217 | afu->native->spa_max_procs = spa_max_procs(afu->native->spa_size); |
218 | } while (afu->native->spa_max_procs < afu->num_procs); | |
f204e0b8 | 219 | |
cbffa3a5 CL |
220 | if (!(afu->native->spa = (struct cxl_process_element *) |
221 | __get_free_pages(GFP_KERNEL | __GFP_ZERO, afu->native->spa_order))) { | |
f204e0b8 IM |
222 | pr_err("cxl_alloc_spa: Unable to allocate scheduled process area\n"); |
223 | return -ENOMEM; | |
224 | } | |
225 | pr_devel("spa pages: %i afu->spa_max_procs: %i afu->num_procs: %i\n", | |
cbffa3a5 | 226 | 1<<afu->native->spa_order, afu->native->spa_max_procs, afu->num_procs); |
f204e0b8 | 227 | |
05155772 DA |
228 | return 0; |
229 | } | |
230 | ||
231 | static void attach_spa(struct cxl_afu *afu) | |
232 | { | |
233 | u64 spap; | |
234 | ||
cbffa3a5 CL |
235 | afu->native->sw_command_status = (__be64 *)((char *)afu->native->spa + |
236 | ((afu->native->spa_max_procs + 3) * 128)); | |
f204e0b8 | 237 | |
cbffa3a5 CL |
238 | spap = virt_to_phys(afu->native->spa) & CXL_PSL_SPAP_Addr; |
239 | spap |= ((afu->native->spa_size >> (12 - CXL_PSL_SPAP_Size_Shift)) - 1) & CXL_PSL_SPAP_Size; | |
f204e0b8 | 240 | spap |= CXL_PSL_SPAP_V; |
cbffa3a5 CL |
241 | pr_devel("cxl: SPA allocated at 0x%p. Max processes: %i, sw_command_status: 0x%p CXL_PSL_SPAP_An=0x%016llx\n", |
242 | afu->native->spa, afu->native->spa_max_procs, | |
243 | afu->native->sw_command_status, spap); | |
f204e0b8 | 244 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, spap); |
f204e0b8 IM |
245 | } |
246 | ||
05155772 | 247 | static inline void detach_spa(struct cxl_afu *afu) |
f204e0b8 | 248 | { |
db7933f3 | 249 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); |
05155772 DA |
250 | } |
251 | ||
252 | void cxl_release_spa(struct cxl_afu *afu) | |
253 | { | |
cbffa3a5 CL |
254 | if (afu->native->spa) { |
255 | free_pages((unsigned long) afu->native->spa, | |
256 | afu->native->spa_order); | |
257 | afu->native->spa = NULL; | |
05155772 | 258 | } |
f204e0b8 IM |
259 | } |
260 | ||
261 | int cxl_tlb_slb_invalidate(struct cxl *adapter) | |
262 | { | |
263 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); | |
264 | ||
265 | pr_devel("CXL adapter wide TLBIA & SLBIA\n"); | |
266 | ||
267 | cxl_p1_write(adapter, CXL_PSL_AFUSEL, CXL_PSL_AFUSEL_A); | |
268 | ||
269 | cxl_p1_write(adapter, CXL_PSL_TLBIA, CXL_TLB_SLB_IQ_ALL); | |
270 | while (cxl_p1_read(adapter, CXL_PSL_TLBIA) & CXL_TLB_SLB_P) { | |
271 | if (time_after_eq(jiffies, timeout)) { | |
272 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide TLBIA timed out!\n"); | |
273 | return -EBUSY; | |
274 | } | |
0d400f77 | 275 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 276 | return -EIO; |
f204e0b8 IM |
277 | cpu_relax(); |
278 | } | |
279 | ||
280 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_ALL); | |
281 | while (cxl_p1_read(adapter, CXL_PSL_SLBIA) & CXL_TLB_SLB_P) { | |
282 | if (time_after_eq(jiffies, timeout)) { | |
283 | dev_warn(&adapter->dev, "WARNING: CXL adapter wide SLBIA timed out!\n"); | |
284 | return -EBUSY; | |
285 | } | |
0d400f77 | 286 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 287 | return -EIO; |
f204e0b8 IM |
288 | cpu_relax(); |
289 | } | |
290 | return 0; | |
291 | } | |
292 | ||
f204e0b8 IM |
293 | static int cxl_write_sstp(struct cxl_afu *afu, u64 sstp0, u64 sstp1) |
294 | { | |
295 | int rc; | |
296 | ||
297 | /* 1. Disable SSTP by writing 0 to SSTP1[V] */ | |
298 | cxl_p2n_write(afu, CXL_SSTP1_An, 0); | |
299 | ||
300 | /* 2. Invalidate all SLB entries */ | |
301 | if ((rc = cxl_afu_slbia(afu))) | |
302 | return rc; | |
303 | ||
304 | /* 3. Set SSTP0_An */ | |
305 | cxl_p2n_write(afu, CXL_SSTP0_An, sstp0); | |
306 | ||
307 | /* 4. Set SSTP1_An */ | |
308 | cxl_p2n_write(afu, CXL_SSTP1_An, sstp1); | |
309 | ||
310 | return 0; | |
311 | } | |
312 | ||
313 | /* Using per slice version may improve performance here. (ie. SLBIA_An) */ | |
314 | static void slb_invalid(struct cxl_context *ctx) | |
315 | { | |
316 | struct cxl *adapter = ctx->afu->adapter; | |
317 | u64 slbia; | |
318 | ||
cbffa3a5 | 319 | WARN_ON(!mutex_is_locked(&ctx->afu->native->spa_mutex)); |
f204e0b8 IM |
320 | |
321 | cxl_p1_write(adapter, CXL_PSL_LBISEL, | |
322 | ((u64)be32_to_cpu(ctx->elem->common.pid) << 32) | | |
323 | be32_to_cpu(ctx->elem->lpid)); | |
324 | cxl_p1_write(adapter, CXL_PSL_SLBIA, CXL_TLB_SLB_IQ_LPIDPID); | |
325 | ||
326 | while (1) { | |
0d400f77 | 327 | if (!cxl_ops->link_ok(adapter, NULL)) |
0b3f9c75 | 328 | break; |
f204e0b8 IM |
329 | slbia = cxl_p1_read(adapter, CXL_PSL_SLBIA); |
330 | if (!(slbia & CXL_TLB_SLB_P)) | |
331 | break; | |
332 | cpu_relax(); | |
333 | } | |
334 | } | |
335 | ||
336 | static int do_process_element_cmd(struct cxl_context *ctx, | |
337 | u64 cmd, u64 pe_state) | |
338 | { | |
339 | u64 state; | |
a98e6e9f | 340 | unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT); |
9bcf28cd IM |
341 | int rc = 0; |
342 | ||
343 | trace_cxl_llcmd(ctx, cmd); | |
f204e0b8 IM |
344 | |
345 | WARN_ON(!ctx->afu->enabled); | |
346 | ||
347 | ctx->elem->software_state = cpu_to_be32(pe_state); | |
348 | smp_wmb(); | |
cbffa3a5 | 349 | *(ctx->afu->native->sw_command_status) = cpu_to_be64(cmd | 0 | ctx->pe); |
f204e0b8 IM |
350 | smp_mb(); |
351 | cxl_p1n_write(ctx->afu, CXL_PSL_LLCMD_An, cmd | ctx->pe); | |
352 | while (1) { | |
a98e6e9f IM |
353 | if (time_after_eq(jiffies, timeout)) { |
354 | dev_warn(&ctx->afu->dev, "WARNING: Process Element Command timed out!\n"); | |
9bcf28cd IM |
355 | rc = -EBUSY; |
356 | goto out; | |
a98e6e9f | 357 | } |
0d400f77 | 358 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
359 | dev_warn(&ctx->afu->dev, "WARNING: Device link down, aborting Process Element Command!\n"); |
360 | rc = -EIO; | |
361 | goto out; | |
362 | } | |
cbffa3a5 | 363 | state = be64_to_cpup(ctx->afu->native->sw_command_status); |
f204e0b8 IM |
364 | if (state == ~0ULL) { |
365 | pr_err("cxl: Error adding process element to AFU\n"); | |
9bcf28cd IM |
366 | rc = -1; |
367 | goto out; | |
f204e0b8 IM |
368 | } |
369 | if ((state & (CXL_SPA_SW_CMD_MASK | CXL_SPA_SW_STATE_MASK | CXL_SPA_SW_LINK_MASK)) == | |
370 | (cmd | (cmd >> 16) | ctx->pe)) | |
371 | break; | |
372 | /* | |
373 | * The command won't finish in the PSL if there are | |
374 | * outstanding DSIs. Hence we need to yield here in | |
375 | * case there are outstanding DSIs that we need to | |
376 | * service. Tuning possiblity: we could wait for a | |
377 | * while before sched | |
378 | */ | |
379 | schedule(); | |
380 | ||
381 | } | |
9bcf28cd IM |
382 | out: |
383 | trace_cxl_llcmd_done(ctx, cmd, rc); | |
384 | return rc; | |
f204e0b8 IM |
385 | } |
386 | ||
387 | static int add_process_element(struct cxl_context *ctx) | |
388 | { | |
389 | int rc = 0; | |
390 | ||
cbffa3a5 | 391 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
392 | pr_devel("%s Adding pe: %i started\n", __func__, ctx->pe); |
393 | if (!(rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_ADD, CXL_PE_SOFTWARE_STATE_V))) | |
394 | ctx->pe_inserted = true; | |
395 | pr_devel("%s Adding pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 396 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
397 | return rc; |
398 | } | |
399 | ||
400 | static int terminate_process_element(struct cxl_context *ctx) | |
401 | { | |
402 | int rc = 0; | |
403 | ||
404 | /* fast path terminate if it's already invalid */ | |
405 | if (!(ctx->elem->software_state & cpu_to_be32(CXL_PE_SOFTWARE_STATE_V))) | |
406 | return rc; | |
407 | ||
cbffa3a5 | 408 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 409 | pr_devel("%s Terminate pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
410 | /* We could be asked to terminate when the hw is down. That |
411 | * should always succeed: it's not running if the hw has gone | |
412 | * away and is being reset. | |
413 | */ | |
0d400f77 | 414 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
415 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_TERMINATE, |
416 | CXL_PE_SOFTWARE_STATE_V | CXL_PE_SOFTWARE_STATE_T); | |
f204e0b8 IM |
417 | ctx->elem->software_state = 0; /* Remove Valid bit */ |
418 | pr_devel("%s Terminate pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 419 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
420 | return rc; |
421 | } | |
422 | ||
423 | static int remove_process_element(struct cxl_context *ctx) | |
424 | { | |
425 | int rc = 0; | |
426 | ||
cbffa3a5 | 427 | mutex_lock(&ctx->afu->native->spa_mutex); |
f204e0b8 | 428 | pr_devel("%s Remove pe: %i started\n", __func__, ctx->pe); |
0b3f9c75 DA |
429 | |
430 | /* We could be asked to remove when the hw is down. Again, if | |
431 | * the hw is down, the PE is gone, so we succeed. | |
432 | */ | |
0d400f77 | 433 | if (cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) |
0b3f9c75 DA |
434 | rc = do_process_element_cmd(ctx, CXL_SPA_SW_CMD_REMOVE, 0); |
435 | ||
436 | if (!rc) | |
f204e0b8 IM |
437 | ctx->pe_inserted = false; |
438 | slb_invalid(ctx); | |
439 | pr_devel("%s Remove pe: %i finished\n", __func__, ctx->pe); | |
cbffa3a5 | 440 | mutex_unlock(&ctx->afu->native->spa_mutex); |
f204e0b8 IM |
441 | |
442 | return rc; | |
443 | } | |
444 | ||
1a1a94b8 | 445 | void cxl_assign_psn_space(struct cxl_context *ctx) |
f204e0b8 IM |
446 | { |
447 | if (!ctx->afu->pp_size || ctx->master) { | |
448 | ctx->psn_phys = ctx->afu->psn_phys; | |
449 | ctx->psn_size = ctx->afu->adapter->ps_size; | |
450 | } else { | |
451 | ctx->psn_phys = ctx->afu->psn_phys + | |
cbffa3a5 | 452 | (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); |
f204e0b8 IM |
453 | ctx->psn_size = ctx->afu->pp_size; |
454 | } | |
455 | } | |
456 | ||
457 | static int activate_afu_directed(struct cxl_afu *afu) | |
458 | { | |
459 | int rc; | |
460 | ||
461 | dev_info(&afu->dev, "Activating AFU directed mode\n"); | |
462 | ||
4108efb0 | 463 | afu->num_procs = afu->max_procs_virtualised; |
cbffa3a5 | 464 | if (afu->native->spa == NULL) { |
05155772 DA |
465 | if (cxl_alloc_spa(afu)) |
466 | return -ENOMEM; | |
467 | } | |
468 | attach_spa(afu); | |
f204e0b8 IM |
469 | |
470 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_AFU); | |
471 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
472 | cxl_p1n_write(afu, CXL_PSL_ID_An, CXL_PSL_ID_An_F | CXL_PSL_ID_An_L); | |
473 | ||
474 | afu->current_mode = CXL_MODE_DIRECTED; | |
f204e0b8 IM |
475 | |
476 | if ((rc = cxl_chardev_m_afu_add(afu))) | |
477 | return rc; | |
478 | ||
479 | if ((rc = cxl_sysfs_afu_m_add(afu))) | |
480 | goto err; | |
481 | ||
482 | if ((rc = cxl_chardev_s_afu_add(afu))) | |
483 | goto err1; | |
484 | ||
485 | return 0; | |
486 | err1: | |
487 | cxl_sysfs_afu_m_remove(afu); | |
488 | err: | |
489 | cxl_chardev_afu_remove(afu); | |
490 | return rc; | |
491 | } | |
492 | ||
493 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
494 | #define set_endian(sr) ((sr) |= CXL_PSL_SR_An_LE) | |
495 | #else | |
496 | #define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE)) | |
497 | #endif | |
498 | ||
2f663527 MN |
499 | static u64 calculate_sr(struct cxl_context *ctx) |
500 | { | |
501 | u64 sr = 0; | |
502 | ||
e606e035 | 503 | set_endian(sr); |
2f663527 MN |
504 | if (ctx->master) |
505 | sr |= CXL_PSL_SR_An_MP; | |
506 | if (mfspr(SPRN_LPCR) & LPCR_TC) | |
507 | sr |= CXL_PSL_SR_An_TC; | |
508 | if (ctx->kernel) { | |
7a0d85d3 IM |
509 | if (!ctx->real_mode) |
510 | sr |= CXL_PSL_SR_An_R; | |
511 | sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV; | |
2f663527 MN |
512 | } else { |
513 | sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R; | |
2f663527 MN |
514 | sr &= ~(CXL_PSL_SR_An_HV); |
515 | if (!test_tsk_thread_flag(current, TIF_32BIT)) | |
516 | sr |= CXL_PSL_SR_An_SF; | |
517 | } | |
518 | return sr; | |
519 | } | |
520 | ||
292841b0 IM |
521 | static void update_ivtes_directed(struct cxl_context *ctx) |
522 | { | |
523 | bool need_update = (ctx->status == STARTED); | |
524 | int r; | |
525 | ||
526 | if (need_update) { | |
527 | WARN_ON(terminate_process_element(ctx)); | |
528 | WARN_ON(remove_process_element(ctx)); | |
529 | } | |
530 | ||
531 | for (r = 0; r < CXL_IRQ_RANGES; r++) { | |
532 | ctx->elem->ivte_offsets[r] = cpu_to_be16(ctx->irqs.offset[r]); | |
533 | ctx->elem->ivte_ranges[r] = cpu_to_be16(ctx->irqs.range[r]); | |
534 | } | |
535 | ||
536 | /* | |
537 | * Theoretically we could use the update llcmd, instead of a | |
538 | * terminate/remove/add (or if an atomic update was required we could | |
539 | * do a suspend/update/resume), however it seems there might be issues | |
540 | * with the update llcmd on some cards (including those using an XSL on | |
541 | * an ASIC) so for now it's safest to go with the commands that are | |
542 | * known to work. In the future if we come across a situation where the | |
543 | * card may be performing transactions using the same PE while we are | |
544 | * doing this update we might need to revisit this. | |
545 | */ | |
546 | if (need_update) | |
547 | WARN_ON(add_process_element(ctx)); | |
548 | } | |
549 | ||
f204e0b8 IM |
550 | static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr) |
551 | { | |
2f663527 | 552 | u32 pid; |
292841b0 | 553 | int result; |
f204e0b8 | 554 | |
1a1a94b8 | 555 | cxl_assign_psn_space(ctx); |
f204e0b8 IM |
556 | |
557 | ctx->elem->ctxtime = 0; /* disable */ | |
558 | ctx->elem->lpid = cpu_to_be32(mfspr(SPRN_LPID)); | |
559 | ctx->elem->haurp = 0; /* disable */ | |
560 | ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1)); | |
561 | ||
2f663527 MN |
562 | pid = current->pid; |
563 | if (ctx->kernel) | |
564 | pid = 0; | |
f204e0b8 | 565 | ctx->elem->common.tid = 0; |
2f663527 MN |
566 | ctx->elem->common.pid = cpu_to_be32(pid); |
567 | ||
568 | ctx->elem->sr = cpu_to_be64(calculate_sr(ctx)); | |
f204e0b8 IM |
569 | |
570 | ctx->elem->common.csrp = 0; /* disable */ | |
571 | ctx->elem->common.aurp0 = 0; /* disable */ | |
572 | ctx->elem->common.aurp1 = 0; /* disable */ | |
573 | ||
574 | cxl_prefault(ctx, wed); | |
575 | ||
576 | ctx->elem->common.sstp0 = cpu_to_be64(ctx->sstp0); | |
577 | ctx->elem->common.sstp1 = cpu_to_be64(ctx->sstp1); | |
578 | ||
3c206fa7 IM |
579 | /* |
580 | * Ensure we have the multiplexed PSL interrupt set up to take faults | |
581 | * for kernel contexts that may not have allocated any AFU IRQs at all: | |
582 | */ | |
583 | if (ctx->irqs.range[0] == 0) { | |
584 | ctx->irqs.offset[0] = ctx->afu->native->psl_hwirq; | |
585 | ctx->irqs.range[0] = 1; | |
586 | } | |
587 | ||
292841b0 | 588 | update_ivtes_directed(ctx); |
f204e0b8 IM |
589 | |
590 | ctx->elem->common.amr = cpu_to_be64(amr); | |
591 | ctx->elem->common.wed = cpu_to_be64(wed); | |
592 | ||
593 | /* first guy needs to enable */ | |
5be587b1 | 594 | if ((result = cxl_ops->afu_check_and_enable(ctx->afu))) |
f204e0b8 IM |
595 | return result; |
596 | ||
368857c1 | 597 | return add_process_element(ctx); |
f204e0b8 IM |
598 | } |
599 | ||
600 | static int deactivate_afu_directed(struct cxl_afu *afu) | |
601 | { | |
602 | dev_info(&afu->dev, "Deactivating AFU directed mode\n"); | |
603 | ||
604 | afu->current_mode = 0; | |
605 | afu->num_procs = 0; | |
606 | ||
607 | cxl_sysfs_afu_m_remove(afu); | |
608 | cxl_chardev_afu_remove(afu); | |
609 | ||
5e7823c9 IM |
610 | /* |
611 | * The CAIA section 2.2.1 indicates that the procedure for starting and | |
612 | * stopping an AFU in AFU directed mode is AFU specific, which is not | |
613 | * ideal since this code is generic and with one exception has no | |
614 | * knowledge of the AFU. This is in contrast to the procedure for | |
615 | * disabling a dedicated process AFU, which is documented to just | |
616 | * require a reset. The architecture does indicate that both an AFU | |
617 | * reset and an AFU disable should result in the AFU being disabled and | |
618 | * we do both followed by a PSL purge for safety. | |
619 | * | |
620 | * Notably we used to have some issues with the disable sequence on PSL | |
621 | * cards, which is why we ended up using this heavy weight procedure in | |
622 | * the first place, however a bug was discovered that had rendered the | |
623 | * disable operation ineffective, so it is conceivable that was the | |
624 | * sole explanation for those difficulties. Careful regression testing | |
625 | * is recommended if anyone attempts to remove or reorder these | |
626 | * operations. | |
627 | * | |
628 | * The XSL on the Mellanox CX4 behaves a little differently from the | |
629 | * PSL based cards and will time out an AFU reset if the AFU is still | |
630 | * enabled. That card is special in that we do have a means to identify | |
631 | * it from this code, so in that case we skip the reset and just use a | |
632 | * disable/purge to avoid the timeout and corresponding noise in the | |
633 | * kernel log. | |
634 | */ | |
635 | if (afu->adapter->native->sl_ops->needs_reset_before_disable) | |
636 | cxl_ops->afu_reset(afu); | |
f204e0b8 IM |
637 | cxl_afu_disable(afu); |
638 | cxl_psl_purge(afu); | |
639 | ||
f204e0b8 IM |
640 | return 0; |
641 | } | |
642 | ||
643 | static int activate_dedicated_process(struct cxl_afu *afu) | |
644 | { | |
645 | dev_info(&afu->dev, "Activating dedicated process mode\n"); | |
646 | ||
647 | cxl_p1n_write(afu, CXL_PSL_SCNTL_An, CXL_PSL_SCNTL_An_PM_Process); | |
648 | ||
649 | cxl_p1n_write(afu, CXL_PSL_CtxTime_An, 0); /* disable */ | |
650 | cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0); /* disable */ | |
651 | cxl_p1n_write(afu, CXL_PSL_AMOR_An, 0xFFFFFFFFFFFFFFFFULL); | |
652 | cxl_p1n_write(afu, CXL_PSL_LPID_An, mfspr(SPRN_LPID)); | |
653 | cxl_p1n_write(afu, CXL_HAURP_An, 0); /* disable */ | |
654 | cxl_p1n_write(afu, CXL_PSL_SDR_An, mfspr(SPRN_SDR1)); | |
655 | ||
656 | cxl_p2n_write(afu, CXL_CSRP_An, 0); /* disable */ | |
657 | cxl_p2n_write(afu, CXL_AURP0_An, 0); /* disable */ | |
658 | cxl_p2n_write(afu, CXL_AURP1_An, 0); /* disable */ | |
659 | ||
660 | afu->current_mode = CXL_MODE_DEDICATED; | |
661 | afu->num_procs = 1; | |
662 | ||
663 | return cxl_chardev_d_afu_add(afu); | |
664 | } | |
665 | ||
292841b0 IM |
666 | static void update_ivtes_dedicated(struct cxl_context *ctx) |
667 | { | |
668 | struct cxl_afu *afu = ctx->afu; | |
669 | ||
670 | cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, | |
671 | (((u64)ctx->irqs.offset[0] & 0xffff) << 48) | | |
672 | (((u64)ctx->irqs.offset[1] & 0xffff) << 32) | | |
673 | (((u64)ctx->irqs.offset[2] & 0xffff) << 16) | | |
674 | ((u64)ctx->irqs.offset[3] & 0xffff)); | |
675 | cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, (u64) | |
676 | (((u64)ctx->irqs.range[0] & 0xffff) << 48) | | |
677 | (((u64)ctx->irqs.range[1] & 0xffff) << 32) | | |
678 | (((u64)ctx->irqs.range[2] & 0xffff) << 16) | | |
679 | ((u64)ctx->irqs.range[3] & 0xffff)); | |
680 | } | |
681 | ||
f204e0b8 IM |
682 | static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr) |
683 | { | |
684 | struct cxl_afu *afu = ctx->afu; | |
2f663527 | 685 | u64 pid; |
f204e0b8 IM |
686 | int rc; |
687 | ||
2f663527 MN |
688 | pid = (u64)current->pid << 32; |
689 | if (ctx->kernel) | |
690 | pid = 0; | |
691 | cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid); | |
692 | ||
693 | cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx)); | |
f204e0b8 IM |
694 | |
695 | if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1))) | |
696 | return rc; | |
697 | ||
698 | cxl_prefault(ctx, wed); | |
699 | ||
292841b0 | 700 | update_ivtes_dedicated(ctx); |
f204e0b8 IM |
701 | |
702 | cxl_p2n_write(afu, CXL_PSL_AMR_An, amr); | |
703 | ||
704 | /* master only context for dedicated */ | |
1a1a94b8 | 705 | cxl_assign_psn_space(ctx); |
f204e0b8 | 706 | |
5be587b1 | 707 | if ((rc = cxl_ops->afu_reset(afu))) |
f204e0b8 IM |
708 | return rc; |
709 | ||
710 | cxl_p2n_write(afu, CXL_PSL_WED_An, wed); | |
711 | ||
712 | return afu_enable(afu); | |
713 | } | |
714 | ||
715 | static int deactivate_dedicated_process(struct cxl_afu *afu) | |
716 | { | |
717 | dev_info(&afu->dev, "Deactivating dedicated process mode\n"); | |
718 | ||
719 | afu->current_mode = 0; | |
720 | afu->num_procs = 0; | |
721 | ||
722 | cxl_chardev_afu_remove(afu); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
2b04cf31 | 727 | static int native_afu_deactivate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
728 | { |
729 | if (mode == CXL_MODE_DIRECTED) | |
730 | return deactivate_afu_directed(afu); | |
731 | if (mode == CXL_MODE_DEDICATED) | |
732 | return deactivate_dedicated_process(afu); | |
733 | return 0; | |
734 | } | |
735 | ||
2b04cf31 | 736 | static int native_afu_activate_mode(struct cxl_afu *afu, int mode) |
f204e0b8 IM |
737 | { |
738 | if (!mode) | |
739 | return 0; | |
740 | if (!(mode & afu->modes_supported)) | |
741 | return -EINVAL; | |
742 | ||
0d400f77 | 743 | if (!cxl_ops->link_ok(afu->adapter, afu)) { |
0b3f9c75 DA |
744 | WARN(1, "Device link is down, refusing to activate!\n"); |
745 | return -EIO; | |
746 | } | |
747 | ||
f204e0b8 IM |
748 | if (mode == CXL_MODE_DIRECTED) |
749 | return activate_afu_directed(afu); | |
750 | if (mode == CXL_MODE_DEDICATED) | |
751 | return activate_dedicated_process(afu); | |
752 | ||
753 | return -EINVAL; | |
754 | } | |
755 | ||
2b04cf31 FB |
756 | static int native_attach_process(struct cxl_context *ctx, bool kernel, |
757 | u64 wed, u64 amr) | |
f204e0b8 | 758 | { |
0d400f77 | 759 | if (!cxl_ops->link_ok(ctx->afu->adapter, ctx->afu)) { |
0b3f9c75 DA |
760 | WARN(1, "Device link is down, refusing to attach process!\n"); |
761 | return -EIO; | |
762 | } | |
763 | ||
f204e0b8 IM |
764 | ctx->kernel = kernel; |
765 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
766 | return attach_afu_directed(ctx, wed, amr); | |
767 | ||
768 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
769 | return attach_dedicated(ctx, wed, amr); | |
770 | ||
771 | return -EINVAL; | |
772 | } | |
773 | ||
774 | static inline int detach_process_native_dedicated(struct cxl_context *ctx) | |
775 | { | |
5e7823c9 IM |
776 | /* |
777 | * The CAIA section 2.1.1 indicates that we need to do an AFU reset to | |
778 | * stop the AFU in dedicated mode (we therefore do not make that | |
779 | * optional like we do in the afu directed path). It does not indicate | |
780 | * that we need to do an explicit disable (which should occur | |
781 | * implicitly as part of the reset) or purge, but we do these as well | |
782 | * to be on the safe side. | |
783 | * | |
784 | * Notably we used to have some issues with the disable sequence | |
785 | * (before the sequence was spelled out in the architecture) which is | |
786 | * why we were so heavy weight in the first place, however a bug was | |
787 | * discovered that had rendered the disable operation ineffective, so | |
788 | * it is conceivable that was the sole explanation for those | |
789 | * difficulties. Point is, we should be careful and do some regression | |
790 | * testing if we ever attempt to remove any part of this procedure. | |
791 | */ | |
5be587b1 | 792 | cxl_ops->afu_reset(ctx->afu); |
f204e0b8 IM |
793 | cxl_afu_disable(ctx->afu); |
794 | cxl_psl_purge(ctx->afu); | |
795 | return 0; | |
796 | } | |
797 | ||
292841b0 IM |
798 | static void native_update_ivtes(struct cxl_context *ctx) |
799 | { | |
800 | if (ctx->afu->current_mode == CXL_MODE_DIRECTED) | |
801 | return update_ivtes_directed(ctx); | |
802 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) | |
803 | return update_ivtes_dedicated(ctx); | |
804 | WARN(1, "native_update_ivtes: Bad mode\n"); | |
805 | } | |
806 | ||
f204e0b8 IM |
807 | static inline int detach_process_native_afu_directed(struct cxl_context *ctx) |
808 | { | |
809 | if (!ctx->pe_inserted) | |
810 | return 0; | |
811 | if (terminate_process_element(ctx)) | |
812 | return -1; | |
813 | if (remove_process_element(ctx)) | |
814 | return -1; | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
2b04cf31 | 819 | static int native_detach_process(struct cxl_context *ctx) |
f204e0b8 | 820 | { |
9bcf28cd IM |
821 | trace_cxl_detach(ctx); |
822 | ||
f204e0b8 IM |
823 | if (ctx->afu->current_mode == CXL_MODE_DEDICATED) |
824 | return detach_process_native_dedicated(ctx); | |
825 | ||
826 | return detach_process_native_afu_directed(ctx); | |
827 | } | |
828 | ||
2b04cf31 | 829 | static int native_get_irq_info(struct cxl_afu *afu, struct cxl_irq_info *info) |
f204e0b8 IM |
830 | { |
831 | u64 pidtid; | |
832 | ||
0b3f9c75 DA |
833 | /* If the adapter has gone away, we can't get any meaningful |
834 | * information. | |
835 | */ | |
0d400f77 | 836 | if (!cxl_ops->link_ok(afu->adapter, afu)) |
0b3f9c75 DA |
837 | return -EIO; |
838 | ||
bc78b05b IM |
839 | info->dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); |
840 | info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); | |
841 | info->dsr = cxl_p2n_read(afu, CXL_PSL_DSR_An); | |
842 | pidtid = cxl_p2n_read(afu, CXL_PSL_PID_TID_An); | |
f204e0b8 IM |
843 | info->pid = pidtid >> 32; |
844 | info->tid = pidtid & 0xffffffff; | |
bc78b05b IM |
845 | info->afu_err = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
846 | info->errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
444c4ba4 | 847 | info->proc_handle = 0; |
f204e0b8 IM |
848 | |
849 | return 0; | |
850 | } | |
851 | ||
6d382616 | 852 | void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx) |
d56d301b FB |
853 | { |
854 | u64 fir1, fir2, fir_slice, serr, afu_debug; | |
855 | ||
856 | fir1 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR1); | |
857 | fir2 = cxl_p1_read(ctx->afu->adapter, CXL_PSL_FIR2); | |
858 | fir_slice = cxl_p1n_read(ctx->afu, CXL_PSL_FIR_SLICE_An); | |
d56d301b FB |
859 | afu_debug = cxl_p1n_read(ctx->afu, CXL_AFU_DEBUG_An); |
860 | ||
d56d301b FB |
861 | dev_crit(&ctx->afu->dev, "PSL_FIR1: 0x%016llx\n", fir1); |
862 | dev_crit(&ctx->afu->dev, "PSL_FIR2: 0x%016llx\n", fir2); | |
6d382616 FB |
863 | if (ctx->afu->adapter->native->sl_ops->register_serr_irq) { |
864 | serr = cxl_p1n_read(ctx->afu, CXL_PSL_SERR_An); | |
6e0c50f9 | 865 | cxl_afu_decode_psl_serr(ctx->afu, serr); |
6d382616 | 866 | } |
d56d301b FB |
867 | dev_crit(&ctx->afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
868 | dev_crit(&ctx->afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
6d382616 FB |
869 | } |
870 | ||
871 | static irqreturn_t native_handle_psl_slice_error(struct cxl_context *ctx, | |
872 | u64 dsisr, u64 errstat) | |
873 | { | |
874 | ||
875 | dev_crit(&ctx->afu->dev, "PSL ERROR STATUS: 0x%016llx\n", errstat); | |
d56d301b | 876 | |
6d382616 FB |
877 | if (ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers) |
878 | ctx->afu->adapter->native->sl_ops->psl_irq_dump_registers(ctx); | |
879 | ||
880 | if (ctx->afu->adapter->native->sl_ops->debugfs_stop_trace) { | |
881 | dev_crit(&ctx->afu->dev, "STOPPING CXL TRACE\n"); | |
882 | ctx->afu->adapter->native->sl_ops->debugfs_stop_trace(ctx->afu->adapter); | |
883 | } | |
d56d301b | 884 | |
5be587b1 | 885 | return cxl_ops->ack_irq(ctx, 0, errstat); |
d56d301b FB |
886 | } |
887 | ||
888 | static irqreturn_t fail_psl_irq(struct cxl_afu *afu, struct cxl_irq_info *irq_info) | |
889 | { | |
890 | if (irq_info->dsisr & CXL_PSL_DSISR_TRANS) | |
891 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE); | |
892 | else | |
893 | cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A); | |
894 | ||
895 | return IRQ_HANDLED; | |
896 | } | |
897 | ||
2b04cf31 | 898 | static irqreturn_t native_irq_multiplexed(int irq, void *data) |
d56d301b FB |
899 | { |
900 | struct cxl_afu *afu = data; | |
901 | struct cxl_context *ctx; | |
902 | struct cxl_irq_info irq_info; | |
903 | int ph = cxl_p2n_read(afu, CXL_PSL_PEHandle_An) & 0xffff; | |
904 | int ret; | |
905 | ||
2b04cf31 | 906 | if ((ret = native_get_irq_info(afu, &irq_info))) { |
d56d301b FB |
907 | WARN(1, "Unable to get CXL IRQ Info: %i\n", ret); |
908 | return fail_psl_irq(afu, &irq_info); | |
909 | } | |
910 | ||
911 | rcu_read_lock(); | |
912 | ctx = idr_find(&afu->contexts_idr, ph); | |
913 | if (ctx) { | |
914 | ret = cxl_irq(irq, ctx, &irq_info); | |
915 | rcu_read_unlock(); | |
916 | return ret; | |
917 | } | |
918 | rcu_read_unlock(); | |
919 | ||
920 | WARN(1, "Unable to demultiplex CXL PSL IRQ for PE %i DSISR %016llx DAR" | |
921 | " %016llx\n(Possible AFU HW issue - was a term/remove acked" | |
922 | " with outstanding transactions?)\n", ph, irq_info.dsisr, | |
923 | irq_info.dar); | |
924 | return fail_psl_irq(afu, &irq_info); | |
925 | } | |
926 | ||
6fd40f19 | 927 | static void native_irq_wait(struct cxl_context *ctx) |
2bc79ffc MN |
928 | { |
929 | u64 dsisr; | |
930 | int timeout = 1000; | |
931 | int ph; | |
932 | ||
933 | /* | |
934 | * Wait until no further interrupts are presented by the PSL | |
935 | * for this context. | |
936 | */ | |
937 | while (timeout--) { | |
938 | ph = cxl_p2n_read(ctx->afu, CXL_PSL_PEHandle_An) & 0xffff; | |
939 | if (ph != ctx->pe) | |
940 | return; | |
941 | dsisr = cxl_p2n_read(ctx->afu, CXL_PSL_DSISR_An); | |
942 | if ((dsisr & CXL_PSL_DSISR_PENDING) == 0) | |
943 | return; | |
944 | /* | |
945 | * We are waiting for the workqueue to process our | |
946 | * irq, so need to let that run here. | |
947 | */ | |
948 | msleep(1); | |
949 | } | |
950 | ||
951 | dev_warn(&ctx->afu->dev, "WARNING: waiting on DSI for PE %i" | |
952 | " DSISR %016llx!\n", ph, dsisr); | |
953 | return; | |
954 | } | |
955 | ||
2b04cf31 | 956 | static irqreturn_t native_slice_irq_err(int irq, void *data) |
d56d301b FB |
957 | { |
958 | struct cxl_afu *afu = data; | |
6e0c50f9 | 959 | u64 fir_slice, errstat, serr, afu_debug, afu_error, dsisr; |
d56d301b | 960 | |
6d382616 FB |
961 | /* |
962 | * slice err interrupt is only used with full PSL (no XSL) | |
963 | */ | |
d56d301b FB |
964 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); |
965 | fir_slice = cxl_p1n_read(afu, CXL_PSL_FIR_SLICE_An); | |
966 | errstat = cxl_p2n_read(afu, CXL_PSL_ErrStat_An); | |
967 | afu_debug = cxl_p1n_read(afu, CXL_AFU_DEBUG_An); | |
6e0c50f9 PB |
968 | afu_error = cxl_p2n_read(afu, CXL_AFU_ERR_An); |
969 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
970 | cxl_afu_decode_psl_serr(afu, serr); | |
d56d301b FB |
971 | dev_crit(&afu->dev, "PSL_FIR_SLICE_An: 0x%016llx\n", fir_slice); |
972 | dev_crit(&afu->dev, "CXL_PSL_ErrStat_An: 0x%016llx\n", errstat); | |
973 | dev_crit(&afu->dev, "CXL_PSL_AFU_DEBUG_An: 0x%016llx\n", afu_debug); | |
6e0c50f9 PB |
974 | dev_crit(&afu->dev, "AFU_ERR_An: 0x%.16llx\n", afu_error); |
975 | dev_crit(&afu->dev, "PSL_DSISR_An: 0x%.16llx\n", dsisr); | |
d56d301b FB |
976 | |
977 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
978 | ||
979 | return IRQ_HANDLED; | |
980 | } | |
981 | ||
6d382616 FB |
982 | void cxl_native_err_irq_dump_regs(struct cxl *adapter) |
983 | { | |
984 | u64 fir1, fir2; | |
985 | ||
986 | fir1 = cxl_p1_read(adapter, CXL_PSL_FIR1); | |
987 | fir2 = cxl_p1_read(adapter, CXL_PSL_FIR2); | |
988 | ||
989 | dev_crit(&adapter->dev, "PSL_FIR1: 0x%016llx\nPSL_FIR2: 0x%016llx\n", fir1, fir2); | |
990 | } | |
991 | ||
2b04cf31 | 992 | static irqreturn_t native_irq_err(int irq, void *data) |
d56d301b FB |
993 | { |
994 | struct cxl *adapter = data; | |
6d382616 | 995 | u64 err_ivte; |
d56d301b FB |
996 | |
997 | WARN(1, "CXL ERROR interrupt %i\n", irq); | |
998 | ||
999 | err_ivte = cxl_p1_read(adapter, CXL_PSL_ErrIVTE); | |
1000 | dev_crit(&adapter->dev, "PSL_ErrIVTE: 0x%016llx\n", err_ivte); | |
1001 | ||
6d382616 FB |
1002 | if (adapter->native->sl_ops->debugfs_stop_trace) { |
1003 | dev_crit(&adapter->dev, "STOPPING CXL TRACE\n"); | |
1004 | adapter->native->sl_ops->debugfs_stop_trace(adapter); | |
1005 | } | |
d56d301b | 1006 | |
6d382616 FB |
1007 | if (adapter->native->sl_ops->err_irq_dump_registers) |
1008 | adapter->native->sl_ops->err_irq_dump_registers(adapter); | |
d56d301b FB |
1009 | |
1010 | return IRQ_HANDLED; | |
1011 | } | |
1012 | ||
2b04cf31 | 1013 | int cxl_native_register_psl_err_irq(struct cxl *adapter) |
d56d301b FB |
1014 | { |
1015 | int rc; | |
1016 | ||
1017 | adapter->irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1018 | dev_name(&adapter->dev)); | |
1019 | if (!adapter->irq_name) | |
1020 | return -ENOMEM; | |
1021 | ||
2b04cf31 | 1022 | if ((rc = cxl_register_one_irq(adapter, native_irq_err, adapter, |
cbffa3a5 CL |
1023 | &adapter->native->err_hwirq, |
1024 | &adapter->native->err_virq, | |
d56d301b FB |
1025 | adapter->irq_name))) { |
1026 | kfree(adapter->irq_name); | |
1027 | adapter->irq_name = NULL; | |
1028 | return rc; | |
1029 | } | |
1030 | ||
cbffa3a5 | 1031 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, adapter->native->err_hwirq & 0xffff); |
d56d301b FB |
1032 | |
1033 | return 0; | |
1034 | } | |
1035 | ||
2b04cf31 | 1036 | void cxl_native_release_psl_err_irq(struct cxl *adapter) |
d56d301b | 1037 | { |
cbffa3a5 | 1038 | if (adapter->native->err_virq != irq_find_mapping(NULL, adapter->native->err_hwirq)) |
d56d301b FB |
1039 | return; |
1040 | ||
1041 | cxl_p1_write(adapter, CXL_PSL_ErrIVTE, 0x0000000000000000); | |
cbffa3a5 CL |
1042 | cxl_unmap_irq(adapter->native->err_virq, adapter); |
1043 | cxl_ops->release_one_irq(adapter, adapter->native->err_hwirq); | |
d56d301b FB |
1044 | kfree(adapter->irq_name); |
1045 | } | |
1046 | ||
2b04cf31 | 1047 | int cxl_native_register_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1048 | { |
1049 | u64 serr; | |
1050 | int rc; | |
1051 | ||
1052 | afu->err_irq_name = kasprintf(GFP_KERNEL, "cxl-%s-err", | |
1053 | dev_name(&afu->dev)); | |
1054 | if (!afu->err_irq_name) | |
1055 | return -ENOMEM; | |
1056 | ||
2b04cf31 | 1057 | if ((rc = cxl_register_one_irq(afu->adapter, native_slice_irq_err, afu, |
d56d301b FB |
1058 | &afu->serr_hwirq, |
1059 | &afu->serr_virq, afu->err_irq_name))) { | |
1060 | kfree(afu->err_irq_name); | |
1061 | afu->err_irq_name = NULL; | |
1062 | return rc; | |
1063 | } | |
1064 | ||
1065 | serr = cxl_p1n_read(afu, CXL_PSL_SERR_An); | |
1066 | serr = (serr & 0x00ffffffffff0000ULL) | (afu->serr_hwirq & 0xffff); | |
1067 | cxl_p1n_write(afu, CXL_PSL_SERR_An, serr); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
2b04cf31 | 1072 | void cxl_native_release_serr_irq(struct cxl_afu *afu) |
d56d301b FB |
1073 | { |
1074 | if (afu->serr_virq != irq_find_mapping(NULL, afu->serr_hwirq)) | |
1075 | return; | |
1076 | ||
1077 | cxl_p1n_write(afu, CXL_PSL_SERR_An, 0x0000000000000000); | |
1078 | cxl_unmap_irq(afu->serr_virq, afu); | |
5be587b1 | 1079 | cxl_ops->release_one_irq(afu->adapter, afu->serr_hwirq); |
d56d301b FB |
1080 | kfree(afu->err_irq_name); |
1081 | } | |
1082 | ||
2b04cf31 | 1083 | int cxl_native_register_psl_irq(struct cxl_afu *afu) |
d56d301b FB |
1084 | { |
1085 | int rc; | |
1086 | ||
1087 | afu->psl_irq_name = kasprintf(GFP_KERNEL, "cxl-%s", | |
1088 | dev_name(&afu->dev)); | |
1089 | if (!afu->psl_irq_name) | |
1090 | return -ENOMEM; | |
1091 | ||
cbffa3a5 CL |
1092 | if ((rc = cxl_register_one_irq(afu->adapter, native_irq_multiplexed, |
1093 | afu, &afu->native->psl_hwirq, &afu->native->psl_virq, | |
d56d301b FB |
1094 | afu->psl_irq_name))) { |
1095 | kfree(afu->psl_irq_name); | |
1096 | afu->psl_irq_name = NULL; | |
1097 | } | |
1098 | return rc; | |
1099 | } | |
1100 | ||
2b04cf31 | 1101 | void cxl_native_release_psl_irq(struct cxl_afu *afu) |
d56d301b | 1102 | { |
cbffa3a5 | 1103 | if (afu->native->psl_virq != irq_find_mapping(NULL, afu->native->psl_hwirq)) |
d56d301b FB |
1104 | return; |
1105 | ||
cbffa3a5 CL |
1106 | cxl_unmap_irq(afu->native->psl_virq, afu); |
1107 | cxl_ops->release_one_irq(afu->adapter, afu->native->psl_hwirq); | |
d56d301b FB |
1108 | kfree(afu->psl_irq_name); |
1109 | } | |
1110 | ||
f204e0b8 IM |
1111 | static void recover_psl_err(struct cxl_afu *afu, u64 errstat) |
1112 | { | |
1113 | u64 dsisr; | |
1114 | ||
de369538 | 1115 | pr_devel("RECOVERING FROM PSL ERROR... (0x%016llx)\n", errstat); |
f204e0b8 IM |
1116 | |
1117 | /* Clear PSL_DSISR[PE] */ | |
1118 | dsisr = cxl_p2n_read(afu, CXL_PSL_DSISR_An); | |
1119 | cxl_p2n_write(afu, CXL_PSL_DSISR_An, dsisr & ~CXL_PSL_DSISR_An_PE); | |
1120 | ||
1121 | /* Write 1s to clear error status bits */ | |
1122 | cxl_p2n_write(afu, CXL_PSL_ErrStat_An, errstat); | |
1123 | } | |
1124 | ||
2b04cf31 | 1125 | static int native_ack_irq(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask) |
f204e0b8 | 1126 | { |
9bcf28cd | 1127 | trace_cxl_psl_irq_ack(ctx, tfc); |
f204e0b8 IM |
1128 | if (tfc) |
1129 | cxl_p2n_write(ctx->afu, CXL_PSL_TFC_An, tfc); | |
1130 | if (psl_reset_mask) | |
1131 | recover_psl_err(ctx->afu, psl_reset_mask); | |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
1136 | int cxl_check_error(struct cxl_afu *afu) | |
1137 | { | |
1138 | return (cxl_p1n_read(afu, CXL_PSL_SCNTL_An) == ~0ULL); | |
1139 | } | |
d56d301b | 1140 | |
4752876c CL |
1141 | static bool native_support_attributes(const char *attr_name, |
1142 | enum cxl_attrs type) | |
1143 | { | |
1144 | return true; | |
1145 | } | |
1146 | ||
2b04cf31 | 1147 | static int native_afu_cr_read64(struct cxl_afu *afu, int cr, u64 off, u64 *out) |
d56d301b | 1148 | { |
0d400f77 | 1149 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1150 | return -EIO; |
1151 | if (unlikely(off >= afu->crs_len)) | |
1152 | return -ERANGE; | |
cbffa3a5 | 1153 | *out = in_le64(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1154 | (cr * afu->crs_len) + off); |
1155 | return 0; | |
d56d301b FB |
1156 | } |
1157 | ||
2b04cf31 | 1158 | static int native_afu_cr_read32(struct cxl_afu *afu, int cr, u64 off, u32 *out) |
d56d301b | 1159 | { |
0d400f77 | 1160 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
5be587b1 FB |
1161 | return -EIO; |
1162 | if (unlikely(off >= afu->crs_len)) | |
1163 | return -ERANGE; | |
cbffa3a5 | 1164 | *out = in_le32(afu->native->afu_desc_mmio + afu->crs_offset + |
5be587b1 FB |
1165 | (cr * afu->crs_len) + off); |
1166 | return 0; | |
d56d301b FB |
1167 | } |
1168 | ||
2b04cf31 | 1169 | static int native_afu_cr_read16(struct cxl_afu *afu, int cr, u64 off, u16 *out) |
d56d301b FB |
1170 | { |
1171 | u64 aligned_off = off & ~0x3L; | |
1172 | u32 val; | |
5be587b1 | 1173 | int rc; |
d56d301b | 1174 | |
2b04cf31 | 1175 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1176 | if (!rc) |
1177 | *out = (val >> ((off & 0x3) * 8)) & 0xffff; | |
1178 | return rc; | |
d56d301b FB |
1179 | } |
1180 | ||
2b04cf31 | 1181 | static int native_afu_cr_read8(struct cxl_afu *afu, int cr, u64 off, u8 *out) |
d56d301b FB |
1182 | { |
1183 | u64 aligned_off = off & ~0x3L; | |
1184 | u32 val; | |
5be587b1 | 1185 | int rc; |
d56d301b | 1186 | |
2b04cf31 | 1187 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val); |
5be587b1 FB |
1188 | if (!rc) |
1189 | *out = (val >> ((off & 0x3) * 8)) & 0xff; | |
1190 | return rc; | |
d56d301b | 1191 | } |
5be587b1 | 1192 | |
d601ea91 FB |
1193 | static int native_afu_cr_write32(struct cxl_afu *afu, int cr, u64 off, u32 in) |
1194 | { | |
0d400f77 | 1195 | if (unlikely(!cxl_ops->link_ok(afu->adapter, afu))) |
d601ea91 FB |
1196 | return -EIO; |
1197 | if (unlikely(off >= afu->crs_len)) | |
1198 | return -ERANGE; | |
1199 | out_le32(afu->native->afu_desc_mmio + afu->crs_offset + | |
1200 | (cr * afu->crs_len) + off, in); | |
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | static int native_afu_cr_write16(struct cxl_afu *afu, int cr, u64 off, u16 in) | |
1205 | { | |
1206 | u64 aligned_off = off & ~0x3L; | |
1207 | u32 val32, mask, shift; | |
1208 | int rc; | |
1209 | ||
1210 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1211 | if (rc) | |
1212 | return rc; | |
1213 | shift = (off & 0x3) * 8; | |
1214 | WARN_ON(shift == 24); | |
1215 | mask = 0xffff << shift; | |
1216 | val32 = (val32 & ~mask) | (in << shift); | |
1217 | ||
1218 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1219 | return rc; | |
1220 | } | |
1221 | ||
1222 | static int native_afu_cr_write8(struct cxl_afu *afu, int cr, u64 off, u8 in) | |
1223 | { | |
1224 | u64 aligned_off = off & ~0x3L; | |
1225 | u32 val32, mask, shift; | |
1226 | int rc; | |
1227 | ||
1228 | rc = native_afu_cr_read32(afu, cr, aligned_off, &val32); | |
1229 | if (rc) | |
1230 | return rc; | |
1231 | shift = (off & 0x3) * 8; | |
1232 | mask = 0xff << shift; | |
1233 | val32 = (val32 & ~mask) | (in << shift); | |
1234 | ||
1235 | rc = native_afu_cr_write32(afu, cr, aligned_off, val32); | |
1236 | return rc; | |
1237 | } | |
1238 | ||
5be587b1 FB |
1239 | const struct cxl_backend_ops cxl_native_ops = { |
1240 | .module = THIS_MODULE, | |
2b04cf31 FB |
1241 | .adapter_reset = cxl_pci_reset, |
1242 | .alloc_one_irq = cxl_pci_alloc_one_irq, | |
1243 | .release_one_irq = cxl_pci_release_one_irq, | |
1244 | .alloc_irq_ranges = cxl_pci_alloc_irq_ranges, | |
1245 | .release_irq_ranges = cxl_pci_release_irq_ranges, | |
1246 | .setup_irq = cxl_pci_setup_irq, | |
1247 | .handle_psl_slice_error = native_handle_psl_slice_error, | |
5be587b1 | 1248 | .psl_interrupt = NULL, |
2b04cf31 | 1249 | .ack_irq = native_ack_irq, |
2bc79ffc | 1250 | .irq_wait = native_irq_wait, |
2b04cf31 FB |
1251 | .attach_process = native_attach_process, |
1252 | .detach_process = native_detach_process, | |
292841b0 | 1253 | .update_ivtes = native_update_ivtes, |
4752876c | 1254 | .support_attributes = native_support_attributes, |
5be587b1 | 1255 | .link_ok = cxl_adapter_link_ok, |
2b04cf31 FB |
1256 | .release_afu = cxl_pci_release_afu, |
1257 | .afu_read_err_buffer = cxl_pci_afu_read_err_buffer, | |
1258 | .afu_check_and_enable = native_afu_check_and_enable, | |
1259 | .afu_activate_mode = native_afu_activate_mode, | |
1260 | .afu_deactivate_mode = native_afu_deactivate_mode, | |
1261 | .afu_reset = native_afu_reset, | |
1262 | .afu_cr_read8 = native_afu_cr_read8, | |
1263 | .afu_cr_read16 = native_afu_cr_read16, | |
1264 | .afu_cr_read32 = native_afu_cr_read32, | |
1265 | .afu_cr_read64 = native_afu_cr_read64, | |
d601ea91 FB |
1266 | .afu_cr_write8 = native_afu_cr_write8, |
1267 | .afu_cr_write16 = native_afu_cr_write16, | |
1268 | .afu_cr_write32 = native_afu_cr_write32, | |
1269 | .read_adapter_vpd = cxl_pci_read_adapter_vpd, | |
5be587b1 | 1270 | }; |