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0e1d715b IS |
1 | /* |
2 | * CARMA Board DATA-FPGA Programmer | |
3 | * | |
4 | * Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | */ | |
11 | ||
12 | #include <linux/dma-mapping.h> | |
5af50730 RH |
13 | #include <linux/of_address.h> |
14 | #include <linux/of_irq.h> | |
0e1d715b IS |
15 | #include <linux/of_platform.h> |
16 | #include <linux/completion.h> | |
17 | #include <linux/miscdevice.h> | |
18 | #include <linux/dmaengine.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/highmem.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/mutex.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/leds.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/kref.h> | |
29 | #include <linux/fs.h> | |
30 | #include <linux/io.h> | |
31 | ||
32 | #include <media/videobuf-dma-sg.h> | |
33 | ||
34 | /* MPC8349EMDS specific get_immrbase() */ | |
35 | #include <sysdev/fsl_soc.h> | |
36 | ||
37 | static const char drv_name[] = "carma-fpga-program"; | |
38 | ||
39 | /* | |
40 | * Firmware images are always this exact size | |
41 | * | |
42 | * 12849552 bytes for a CARMA Digitizer Board (EP2S90 FPGAs) | |
43 | * 18662880 bytes for a CARMA Correlator Board (EP2S130 FPGAs) | |
44 | */ | |
45 | #define FW_SIZE_EP2S90 12849552 | |
46 | #define FW_SIZE_EP2S130 18662880 | |
47 | ||
48 | struct fpga_dev { | |
49 | struct miscdevice miscdev; | |
50 | ||
51 | /* Reference count */ | |
52 | struct kref ref; | |
53 | ||
54 | /* Device Registers */ | |
55 | struct device *dev; | |
56 | void __iomem *regs; | |
57 | void __iomem *immr; | |
58 | ||
59 | /* Freescale DMA Device */ | |
60 | struct dma_chan *chan; | |
61 | ||
62 | /* Interrupts */ | |
63 | int irq, status; | |
64 | struct completion completion; | |
65 | ||
66 | /* FPGA Bitfile */ | |
67 | struct mutex lock; | |
68 | ||
69 | struct videobuf_dmabuf vb; | |
70 | bool vb_allocated; | |
71 | ||
72 | /* max size and written bytes */ | |
73 | size_t fw_size; | |
74 | size_t bytes; | |
75 | }; | |
76 | ||
77 | /* | |
78 | * FPGA Bitfile Helpers | |
79 | */ | |
80 | ||
81 | /** | |
82 | * fpga_drop_firmware_data() - drop the bitfile image from memory | |
83 | * @priv: the driver's private data structure | |
84 | * | |
85 | * LOCKING: must hold priv->lock | |
86 | */ | |
87 | static void fpga_drop_firmware_data(struct fpga_dev *priv) | |
88 | { | |
89 | videobuf_dma_free(&priv->vb); | |
90 | priv->vb_allocated = false; | |
91 | priv->bytes = 0; | |
92 | } | |
93 | ||
94 | /* | |
95 | * Private Data Reference Count | |
96 | */ | |
97 | ||
98 | static void fpga_dev_remove(struct kref *ref) | |
99 | { | |
100 | struct fpga_dev *priv = container_of(ref, struct fpga_dev, ref); | |
101 | ||
102 | /* free any firmware image that was not programmed */ | |
103 | fpga_drop_firmware_data(priv); | |
104 | ||
105 | mutex_destroy(&priv->lock); | |
106 | kfree(priv); | |
107 | } | |
108 | ||
109 | /* | |
110 | * LED Trigger (could be a seperate module) | |
111 | */ | |
112 | ||
113 | /* | |
114 | * NOTE: this whole thing does have the problem that whenever the led's are | |
115 | * NOTE: first set to use the fpga trigger, they could be in the wrong state | |
116 | */ | |
117 | ||
118 | DEFINE_LED_TRIGGER(ledtrig_fpga); | |
119 | ||
120 | static void ledtrig_fpga_programmed(bool enabled) | |
121 | { | |
122 | if (enabled) | |
123 | led_trigger_event(ledtrig_fpga, LED_FULL); | |
124 | else | |
125 | led_trigger_event(ledtrig_fpga, LED_OFF); | |
126 | } | |
127 | ||
128 | /* | |
129 | * FPGA Register Helpers | |
130 | */ | |
131 | ||
132 | /* Register Definitions */ | |
133 | #define FPGA_CONFIG_CONTROL 0x40 | |
134 | #define FPGA_CONFIG_STATUS 0x44 | |
135 | #define FPGA_CONFIG_FIFO_SIZE 0x48 | |
136 | #define FPGA_CONFIG_FIFO_USED 0x4C | |
137 | #define FPGA_CONFIG_TOTAL_BYTE_COUNT 0x50 | |
138 | #define FPGA_CONFIG_CUR_BYTE_COUNT 0x54 | |
139 | ||
140 | #define FPGA_FIFO_ADDRESS 0x3000 | |
141 | ||
142 | static int fpga_fifo_size(void __iomem *regs) | |
143 | { | |
144 | return ioread32be(regs + FPGA_CONFIG_FIFO_SIZE); | |
145 | } | |
146 | ||
147 | #define CFG_STATUS_ERR_MASK 0xfffe | |
148 | ||
149 | static int fpga_config_error(void __iomem *regs) | |
150 | { | |
151 | return ioread32be(regs + FPGA_CONFIG_STATUS) & CFG_STATUS_ERR_MASK; | |
152 | } | |
153 | ||
154 | static int fpga_fifo_empty(void __iomem *regs) | |
155 | { | |
156 | return ioread32be(regs + FPGA_CONFIG_FIFO_USED) == 0; | |
157 | } | |
158 | ||
159 | static void fpga_fifo_write(void __iomem *regs, u32 val) | |
160 | { | |
161 | iowrite32be(val, regs + FPGA_FIFO_ADDRESS); | |
162 | } | |
163 | ||
164 | static void fpga_set_byte_count(void __iomem *regs, u32 count) | |
165 | { | |
166 | iowrite32be(count, regs + FPGA_CONFIG_TOTAL_BYTE_COUNT); | |
167 | } | |
168 | ||
169 | #define CFG_CTL_ENABLE (1 << 0) | |
170 | #define CFG_CTL_RESET (1 << 1) | |
171 | #define CFG_CTL_DMA (1 << 2) | |
172 | ||
173 | static void fpga_programmer_enable(struct fpga_dev *priv, bool dma) | |
174 | { | |
175 | u32 val; | |
176 | ||
177 | val = (dma) ? (CFG_CTL_ENABLE | CFG_CTL_DMA) : CFG_CTL_ENABLE; | |
178 | iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL); | |
179 | } | |
180 | ||
181 | static void fpga_programmer_disable(struct fpga_dev *priv) | |
182 | { | |
183 | iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL); | |
184 | } | |
185 | ||
186 | static void fpga_dump_registers(struct fpga_dev *priv) | |
187 | { | |
188 | u32 control, status, size, used, total, curr; | |
189 | ||
190 | /* good status: do nothing */ | |
191 | if (priv->status == 0) | |
192 | return; | |
193 | ||
194 | /* Dump all status registers */ | |
195 | control = ioread32be(priv->regs + FPGA_CONFIG_CONTROL); | |
196 | status = ioread32be(priv->regs + FPGA_CONFIG_STATUS); | |
197 | size = ioread32be(priv->regs + FPGA_CONFIG_FIFO_SIZE); | |
198 | used = ioread32be(priv->regs + FPGA_CONFIG_FIFO_USED); | |
199 | total = ioread32be(priv->regs + FPGA_CONFIG_TOTAL_BYTE_COUNT); | |
200 | curr = ioread32be(priv->regs + FPGA_CONFIG_CUR_BYTE_COUNT); | |
201 | ||
202 | dev_err(priv->dev, "Configuration failed, dumping status registers\n"); | |
203 | dev_err(priv->dev, "Control: 0x%.8x\n", control); | |
204 | dev_err(priv->dev, "Status: 0x%.8x\n", status); | |
205 | dev_err(priv->dev, "FIFO Size: 0x%.8x\n", size); | |
206 | dev_err(priv->dev, "FIFO Used: 0x%.8x\n", used); | |
207 | dev_err(priv->dev, "FIFO Total: 0x%.8x\n", total); | |
208 | dev_err(priv->dev, "FIFO Curr: 0x%.8x\n", curr); | |
209 | } | |
210 | ||
211 | /* | |
212 | * FPGA Power Supply Code | |
213 | */ | |
214 | ||
215 | #define CTL_PWR_CONTROL 0x2006 | |
216 | #define CTL_PWR_STATUS 0x200A | |
217 | #define CTL_PWR_FAIL 0x200B | |
218 | ||
219 | #define PWR_CONTROL_ENABLE 0x01 | |
220 | ||
221 | #define PWR_STATUS_ERROR_MASK 0x10 | |
222 | #define PWR_STATUS_GOOD 0x0f | |
223 | ||
224 | /* | |
225 | * Determine if the FPGA power is good for all supplies | |
226 | */ | |
227 | static bool fpga_power_good(struct fpga_dev *priv) | |
228 | { | |
229 | u8 val; | |
230 | ||
231 | val = ioread8(priv->regs + CTL_PWR_STATUS); | |
232 | if (val & PWR_STATUS_ERROR_MASK) | |
233 | return false; | |
234 | ||
235 | return val == PWR_STATUS_GOOD; | |
236 | } | |
237 | ||
238 | /* | |
239 | * Disable the FPGA power supplies | |
240 | */ | |
241 | static void fpga_disable_power_supplies(struct fpga_dev *priv) | |
242 | { | |
243 | unsigned long start; | |
244 | u8 val; | |
245 | ||
246 | iowrite8(0x0, priv->regs + CTL_PWR_CONTROL); | |
247 | ||
248 | /* | |
249 | * Wait 500ms for the power rails to discharge | |
250 | * | |
251 | * Without this delay, the CTL-CPLD state machine can get into a | |
252 | * state where it is waiting for the power-goods to assert, but they | |
253 | * never do. This only happens when enabling and disabling the | |
254 | * power sequencer very rapidly. | |
255 | * | |
256 | * The loop below will also wait for the power goods to de-assert, | |
257 | * but testing has shown that they are always disabled by the time | |
258 | * the sleep completes. However, omitting the sleep and only waiting | |
259 | * for the power-goods to de-assert was not sufficient to ensure | |
260 | * that the power sequencer would not wedge itself. | |
261 | */ | |
262 | msleep(500); | |
263 | ||
264 | start = jiffies; | |
265 | while (time_before(jiffies, start + HZ)) { | |
266 | val = ioread8(priv->regs + CTL_PWR_STATUS); | |
267 | if (!(val & PWR_STATUS_GOOD)) | |
268 | break; | |
269 | ||
270 | usleep_range(5000, 10000); | |
271 | } | |
272 | ||
273 | val = ioread8(priv->regs + CTL_PWR_STATUS); | |
274 | if (val & PWR_STATUS_GOOD) { | |
275 | dev_err(priv->dev, "power disable failed: " | |
276 | "power goods: status 0x%.2x\n", val); | |
277 | } | |
278 | ||
279 | if (val & PWR_STATUS_ERROR_MASK) { | |
280 | dev_err(priv->dev, "power disable failed: " | |
281 | "alarm bit set: status 0x%.2x\n", val); | |
282 | } | |
283 | } | |
284 | ||
285 | /** | |
286 | * fpga_enable_power_supplies() - enable the DATA-FPGA power supplies | |
287 | * @priv: the driver's private data structure | |
288 | * | |
289 | * Enable the DATA-FPGA power supplies, waiting up to 1 second for | |
290 | * them to enable successfully. | |
291 | * | |
292 | * Returns 0 on success, -ERRNO otherwise | |
293 | */ | |
294 | static int fpga_enable_power_supplies(struct fpga_dev *priv) | |
295 | { | |
296 | unsigned long start = jiffies; | |
297 | ||
298 | if (fpga_power_good(priv)) { | |
299 | dev_dbg(priv->dev, "power was already good\n"); | |
300 | return 0; | |
301 | } | |
302 | ||
303 | iowrite8(PWR_CONTROL_ENABLE, priv->regs + CTL_PWR_CONTROL); | |
304 | while (time_before(jiffies, start + HZ)) { | |
305 | if (fpga_power_good(priv)) | |
306 | return 0; | |
307 | ||
308 | usleep_range(5000, 10000); | |
309 | } | |
310 | ||
311 | return fpga_power_good(priv) ? 0 : -ETIMEDOUT; | |
312 | } | |
313 | ||
314 | /* | |
315 | * Determine if the FPGA power supplies are all enabled | |
316 | */ | |
317 | static bool fpga_power_enabled(struct fpga_dev *priv) | |
318 | { | |
319 | u8 val; | |
320 | ||
321 | val = ioread8(priv->regs + CTL_PWR_CONTROL); | |
322 | if (val & PWR_CONTROL_ENABLE) | |
323 | return true; | |
324 | ||
325 | return false; | |
326 | } | |
327 | ||
328 | /* | |
329 | * Determine if the FPGA's are programmed and running correctly | |
330 | */ | |
331 | static bool fpga_running(struct fpga_dev *priv) | |
332 | { | |
333 | if (!fpga_power_good(priv)) | |
334 | return false; | |
335 | ||
336 | /* Check the config done bit */ | |
337 | return ioread32be(priv->regs + FPGA_CONFIG_STATUS) & (1 << 18); | |
338 | } | |
339 | ||
340 | /* | |
341 | * FPGA Programming Code | |
342 | */ | |
343 | ||
344 | /** | |
345 | * fpga_program_block() - put a block of data into the programmer's FIFO | |
346 | * @priv: the driver's private data structure | |
347 | * @buf: the data to program | |
348 | * @count: the length of data to program (must be a multiple of 4 bytes) | |
349 | * | |
350 | * Returns 0 on success, -ERRNO otherwise | |
351 | */ | |
352 | static int fpga_program_block(struct fpga_dev *priv, void *buf, size_t count) | |
353 | { | |
354 | u32 *data = buf; | |
355 | int size = fpga_fifo_size(priv->regs); | |
356 | int i, len; | |
357 | unsigned long timeout; | |
358 | ||
359 | /* enforce correct data length for the FIFO */ | |
360 | BUG_ON(count % 4 != 0); | |
361 | ||
362 | while (count > 0) { | |
363 | ||
364 | /* Get the size of the block to write (maximum is FIFO_SIZE) */ | |
365 | len = min_t(size_t, count, size); | |
366 | timeout = jiffies + HZ / 4; | |
367 | ||
368 | /* Write the block */ | |
369 | for (i = 0; i < len / 4; i++) | |
370 | fpga_fifo_write(priv->regs, data[i]); | |
371 | ||
372 | /* Update the amounts left */ | |
373 | count -= len; | |
374 | data += len / 4; | |
375 | ||
376 | /* Wait for the fifo to empty */ | |
377 | while (true) { | |
378 | ||
379 | if (fpga_fifo_empty(priv->regs)) { | |
380 | break; | |
381 | } else { | |
382 | dev_dbg(priv->dev, "Fifo not empty\n"); | |
383 | cpu_relax(); | |
384 | } | |
385 | ||
386 | if (fpga_config_error(priv->regs)) { | |
387 | dev_err(priv->dev, "Error detected\n"); | |
388 | return -EIO; | |
389 | } | |
390 | ||
391 | if (time_after(jiffies, timeout)) { | |
392 | dev_err(priv->dev, "Fifo drain timeout\n"); | |
393 | return -ETIMEDOUT; | |
394 | } | |
395 | ||
396 | usleep_range(5000, 10000); | |
397 | } | |
398 | } | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | /** | |
404 | * fpga_program_cpu() - program the DATA-FPGA's using the CPU | |
405 | * @priv: the driver's private data structure | |
406 | * | |
407 | * This is useful when the DMA programming method fails. It is possible to | |
408 | * wedge the Freescale DMA controller such that the DMA programming method | |
409 | * always fails. This method has always succeeded. | |
410 | * | |
411 | * Returns 0 on success, -ERRNO otherwise | |
412 | */ | |
413 | static noinline int fpga_program_cpu(struct fpga_dev *priv) | |
414 | { | |
415 | int ret; | |
416 | ||
417 | /* Disable the programmer */ | |
418 | fpga_programmer_disable(priv); | |
419 | ||
420 | /* Set the total byte count */ | |
421 | fpga_set_byte_count(priv->regs, priv->bytes); | |
422 | dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes); | |
423 | ||
424 | /* Enable the controller for programming */ | |
425 | fpga_programmer_enable(priv, false); | |
426 | dev_dbg(priv->dev, "enabled the controller\n"); | |
427 | ||
428 | /* Write each chunk of the FPGA bitfile to FPGA programmer */ | |
429 | ret = fpga_program_block(priv, priv->vb.vaddr, priv->bytes); | |
430 | if (ret) | |
431 | goto out_disable_controller; | |
432 | ||
433 | /* Wait for the interrupt handler to signal that programming finished */ | |
434 | ret = wait_for_completion_timeout(&priv->completion, 2 * HZ); | |
435 | if (!ret) { | |
436 | dev_err(priv->dev, "Timed out waiting for completion\n"); | |
437 | ret = -ETIMEDOUT; | |
438 | goto out_disable_controller; | |
439 | } | |
440 | ||
441 | /* Retrieve the status from the interrupt handler */ | |
442 | ret = priv->status; | |
443 | ||
444 | out_disable_controller: | |
445 | fpga_programmer_disable(priv); | |
446 | return ret; | |
447 | } | |
448 | ||
449 | #define FIFO_DMA_ADDRESS 0xf0003000 | |
450 | #define FIFO_MAX_LEN 4096 | |
451 | ||
452 | /** | |
453 | * fpga_program_dma() - program the DATA-FPGA's using the DMA engine | |
454 | * @priv: the driver's private data structure | |
455 | * | |
456 | * Program the DATA-FPGA's using the Freescale DMA engine. This requires that | |
457 | * the engine is programmed such that the hardware DMA request lines can | |
458 | * control the entire DMA transaction. The system controller FPGA then | |
459 | * completely offloads the programming from the CPU. | |
460 | * | |
461 | * Returns 0 on success, -ERRNO otherwise | |
462 | */ | |
463 | static noinline int fpga_program_dma(struct fpga_dev *priv) | |
464 | { | |
465 | struct videobuf_dmabuf *vb = &priv->vb; | |
466 | struct dma_chan *chan = priv->chan; | |
467 | struct dma_async_tx_descriptor *tx; | |
468 | size_t num_pages, len, avail = 0; | |
469 | struct dma_slave_config config; | |
470 | struct scatterlist *sg; | |
471 | struct sg_table table; | |
472 | dma_cookie_t cookie; | |
473 | int ret, i; | |
474 | ||
475 | /* Disable the programmer */ | |
476 | fpga_programmer_disable(priv); | |
477 | ||
478 | /* Allocate a scatterlist for the DMA destination */ | |
479 | num_pages = DIV_ROUND_UP(priv->bytes, FIFO_MAX_LEN); | |
480 | ret = sg_alloc_table(&table, num_pages, GFP_KERNEL); | |
481 | if (ret) { | |
482 | dev_err(priv->dev, "Unable to allocate dst scatterlist\n"); | |
483 | ret = -ENOMEM; | |
484 | goto out_return; | |
485 | } | |
486 | ||
487 | /* | |
488 | * This is an ugly hack | |
489 | * | |
490 | * We fill in a scatterlist as if it were mapped for DMA. This is | |
491 | * necessary because there exists no better structure for this | |
492 | * inside the kernel code. | |
493 | * | |
494 | * As an added bonus, we can use the DMAEngine API for all of this, | |
495 | * rather than inventing another extremely similar API. | |
496 | */ | |
497 | avail = priv->bytes; | |
498 | for_each_sg(table.sgl, sg, num_pages, i) { | |
499 | len = min_t(size_t, avail, FIFO_MAX_LEN); | |
500 | sg_dma_address(sg) = FIFO_DMA_ADDRESS; | |
501 | sg_dma_len(sg) = len; | |
502 | ||
503 | avail -= len; | |
504 | } | |
505 | ||
506 | /* Map the buffer for DMA */ | |
507 | ret = videobuf_dma_map(priv->dev, &priv->vb); | |
508 | if (ret) { | |
509 | dev_err(priv->dev, "Unable to map buffer for DMA\n"); | |
510 | goto out_free_table; | |
511 | } | |
512 | ||
513 | /* | |
514 | * Configure the DMA channel to transfer FIFO_SIZE / 2 bytes per | |
515 | * transaction, and then put it under external control | |
516 | */ | |
517 | memset(&config, 0, sizeof(config)); | |
1d0c81e8 | 518 | config.direction = DMA_MEM_TO_DEV; |
0e1d715b IS |
519 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
520 | config.dst_maxburst = fpga_fifo_size(priv->regs) / 2 / 4; | |
521 | ret = chan->device->device_control(chan, DMA_SLAVE_CONFIG, | |
522 | (unsigned long)&config); | |
523 | if (ret) { | |
524 | dev_err(priv->dev, "DMA slave configuration failed\n"); | |
525 | goto out_dma_unmap; | |
526 | } | |
527 | ||
528 | ret = chan->device->device_control(chan, FSLDMA_EXTERNAL_START, 1); | |
529 | if (ret) { | |
530 | dev_err(priv->dev, "DMA external control setup failed\n"); | |
531 | goto out_dma_unmap; | |
532 | } | |
533 | ||
534 | /* setup and submit the DMA transaction */ | |
535 | tx = chan->device->device_prep_dma_sg(chan, | |
536 | table.sgl, num_pages, | |
537 | vb->sglist, vb->sglen, 0); | |
538 | if (!tx) { | |
539 | dev_err(priv->dev, "Unable to prep DMA transaction\n"); | |
540 | ret = -ENOMEM; | |
541 | goto out_dma_unmap; | |
542 | } | |
543 | ||
544 | cookie = tx->tx_submit(tx); | |
545 | if (dma_submit_error(cookie)) { | |
546 | dev_err(priv->dev, "Unable to submit DMA transaction\n"); | |
547 | ret = -ENOMEM; | |
548 | goto out_dma_unmap; | |
549 | } | |
550 | ||
b9ee8683 | 551 | dma_async_issue_pending(chan); |
0e1d715b IS |
552 | |
553 | /* Set the total byte count */ | |
554 | fpga_set_byte_count(priv->regs, priv->bytes); | |
555 | dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes); | |
556 | ||
557 | /* Enable the controller for DMA programming */ | |
558 | fpga_programmer_enable(priv, true); | |
559 | dev_dbg(priv->dev, "enabled the controller\n"); | |
560 | ||
561 | /* Wait for the interrupt handler to signal that programming finished */ | |
562 | ret = wait_for_completion_timeout(&priv->completion, 2 * HZ); | |
563 | if (!ret) { | |
564 | dev_err(priv->dev, "Timed out waiting for completion\n"); | |
565 | ret = -ETIMEDOUT; | |
566 | goto out_disable_controller; | |
567 | } | |
568 | ||
569 | /* Retrieve the status from the interrupt handler */ | |
570 | ret = priv->status; | |
571 | ||
572 | out_disable_controller: | |
573 | fpga_programmer_disable(priv); | |
574 | out_dma_unmap: | |
575 | videobuf_dma_unmap(priv->dev, vb); | |
576 | out_free_table: | |
577 | sg_free_table(&table); | |
578 | out_return: | |
579 | return ret; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Interrupt Handling | |
584 | */ | |
585 | ||
586 | static irqreturn_t fpga_irq(int irq, void *dev_id) | |
587 | { | |
588 | struct fpga_dev *priv = dev_id; | |
589 | ||
590 | /* Save the status */ | |
591 | priv->status = fpga_config_error(priv->regs) ? -EIO : 0; | |
592 | dev_dbg(priv->dev, "INTERRUPT status %d\n", priv->status); | |
593 | fpga_dump_registers(priv); | |
594 | ||
595 | /* Disabling the programmer clears the interrupt */ | |
596 | fpga_programmer_disable(priv); | |
597 | ||
598 | /* Notify any waiters */ | |
599 | complete(&priv->completion); | |
600 | ||
601 | return IRQ_HANDLED; | |
602 | } | |
603 | ||
604 | /* | |
605 | * SYSFS Helpers | |
606 | */ | |
607 | ||
608 | /** | |
609 | * fpga_do_stop() - deconfigure (reset) the DATA-FPGA's | |
610 | * @priv: the driver's private data structure | |
611 | * | |
612 | * LOCKING: must hold priv->lock | |
613 | */ | |
614 | static int fpga_do_stop(struct fpga_dev *priv) | |
615 | { | |
616 | u32 val; | |
617 | ||
618 | /* Set the led to unprogrammed */ | |
619 | ledtrig_fpga_programmed(false); | |
620 | ||
621 | /* Pulse the config line to reset the FPGA's */ | |
622 | val = CFG_CTL_ENABLE | CFG_CTL_RESET; | |
623 | iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL); | |
624 | iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL); | |
625 | ||
626 | return 0; | |
627 | } | |
628 | ||
629 | static noinline int fpga_do_program(struct fpga_dev *priv) | |
630 | { | |
631 | int ret; | |
632 | ||
633 | if (priv->bytes != priv->fw_size) { | |
634 | dev_err(priv->dev, "Incorrect bitfile size: got %zu bytes, " | |
635 | "should be %zu bytes\n", | |
636 | priv->bytes, priv->fw_size); | |
637 | return -EINVAL; | |
638 | } | |
639 | ||
640 | if (!fpga_power_enabled(priv)) { | |
641 | dev_err(priv->dev, "Power not enabled\n"); | |
642 | return -EINVAL; | |
643 | } | |
644 | ||
645 | if (!fpga_power_good(priv)) { | |
646 | dev_err(priv->dev, "Power not good\n"); | |
647 | return -EINVAL; | |
648 | } | |
649 | ||
650 | /* Set the LED to unprogrammed */ | |
651 | ledtrig_fpga_programmed(false); | |
652 | ||
653 | /* Try to program the FPGA's using DMA */ | |
654 | ret = fpga_program_dma(priv); | |
655 | ||
656 | /* If DMA failed or doesn't exist, try with CPU */ | |
657 | if (ret) { | |
658 | dev_warn(priv->dev, "Falling back to CPU programming\n"); | |
659 | ret = fpga_program_cpu(priv); | |
660 | } | |
661 | ||
662 | if (ret) { | |
663 | dev_err(priv->dev, "Unable to program FPGA's\n"); | |
664 | return ret; | |
665 | } | |
666 | ||
667 | /* Drop the firmware bitfile from memory */ | |
668 | fpga_drop_firmware_data(priv); | |
669 | ||
670 | dev_dbg(priv->dev, "FPGA programming successful\n"); | |
671 | ledtrig_fpga_programmed(true); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
676 | /* | |
677 | * File Operations | |
678 | */ | |
679 | ||
680 | static int fpga_open(struct inode *inode, struct file *filp) | |
681 | { | |
682 | /* | |
683 | * The miscdevice layer puts our struct miscdevice into the | |
684 | * filp->private_data field. We use this to find our private | |
685 | * data and then overwrite it with our own private structure. | |
686 | */ | |
687 | struct fpga_dev *priv = container_of(filp->private_data, | |
688 | struct fpga_dev, miscdev); | |
689 | unsigned int nr_pages; | |
690 | int ret; | |
691 | ||
692 | /* We only allow one process at a time */ | |
693 | ret = mutex_lock_interruptible(&priv->lock); | |
694 | if (ret) | |
695 | return ret; | |
696 | ||
697 | filp->private_data = priv; | |
698 | kref_get(&priv->ref); | |
699 | ||
700 | /* Truncation: drop any existing data */ | |
701 | if (filp->f_flags & O_TRUNC) | |
702 | priv->bytes = 0; | |
703 | ||
704 | /* Check if we have already allocated a buffer */ | |
705 | if (priv->vb_allocated) | |
706 | return 0; | |
707 | ||
708 | /* Allocate a buffer to hold enough data for the bitfile */ | |
709 | nr_pages = DIV_ROUND_UP(priv->fw_size, PAGE_SIZE); | |
710 | ret = videobuf_dma_init_kernel(&priv->vb, DMA_TO_DEVICE, nr_pages); | |
711 | if (ret) { | |
712 | dev_err(priv->dev, "unable to allocate data buffer\n"); | |
713 | mutex_unlock(&priv->lock); | |
714 | kref_put(&priv->ref, fpga_dev_remove); | |
715 | return ret; | |
716 | } | |
717 | ||
718 | priv->vb_allocated = true; | |
719 | return 0; | |
720 | } | |
721 | ||
722 | static int fpga_release(struct inode *inode, struct file *filp) | |
723 | { | |
724 | struct fpga_dev *priv = filp->private_data; | |
725 | ||
726 | mutex_unlock(&priv->lock); | |
727 | kref_put(&priv->ref, fpga_dev_remove); | |
728 | return 0; | |
729 | } | |
730 | ||
731 | static ssize_t fpga_write(struct file *filp, const char __user *buf, | |
732 | size_t count, loff_t *f_pos) | |
733 | { | |
734 | struct fpga_dev *priv = filp->private_data; | |
735 | ||
736 | /* FPGA bitfiles have an exact size: disallow anything else */ | |
737 | if (priv->bytes >= priv->fw_size) | |
738 | return -ENOSPC; | |
739 | ||
740 | count = min_t(size_t, priv->fw_size - priv->bytes, count); | |
741 | if (copy_from_user(priv->vb.vaddr + priv->bytes, buf, count)) | |
742 | return -EFAULT; | |
743 | ||
744 | priv->bytes += count; | |
745 | return count; | |
746 | } | |
747 | ||
748 | static ssize_t fpga_read(struct file *filp, char __user *buf, size_t count, | |
749 | loff_t *f_pos) | |
750 | { | |
751 | struct fpga_dev *priv = filp->private_data; | |
752 | ||
753 | count = min_t(size_t, priv->bytes - *f_pos, count); | |
754 | if (copy_to_user(buf, priv->vb.vaddr + *f_pos, count)) | |
755 | return -EFAULT; | |
756 | ||
757 | *f_pos += count; | |
758 | return count; | |
759 | } | |
760 | ||
761 | static loff_t fpga_llseek(struct file *filp, loff_t offset, int origin) | |
762 | { | |
763 | struct fpga_dev *priv = filp->private_data; | |
764 | loff_t newpos; | |
765 | ||
766 | /* only read-only opens are allowed to seek */ | |
767 | if ((filp->f_flags & O_ACCMODE) != O_RDONLY) | |
768 | return -EINVAL; | |
769 | ||
770 | switch (origin) { | |
771 | case SEEK_SET: /* seek relative to the beginning of the file */ | |
772 | newpos = offset; | |
773 | break; | |
774 | case SEEK_CUR: /* seek relative to current position in the file */ | |
775 | newpos = filp->f_pos + offset; | |
776 | break; | |
777 | case SEEK_END: /* seek relative to the end of the file */ | |
778 | newpos = priv->fw_size - offset; | |
779 | break; | |
780 | default: | |
781 | return -EINVAL; | |
782 | } | |
783 | ||
784 | /* check for sanity */ | |
785 | if (newpos > priv->fw_size) | |
786 | return -EINVAL; | |
787 | ||
788 | filp->f_pos = newpos; | |
789 | return newpos; | |
790 | } | |
791 | ||
792 | static const struct file_operations fpga_fops = { | |
793 | .open = fpga_open, | |
794 | .release = fpga_release, | |
795 | .write = fpga_write, | |
796 | .read = fpga_read, | |
797 | .llseek = fpga_llseek, | |
798 | }; | |
799 | ||
800 | /* | |
801 | * Device Attributes | |
802 | */ | |
803 | ||
804 | static ssize_t pfail_show(struct device *dev, struct device_attribute *attr, | |
805 | char *buf) | |
806 | { | |
807 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
808 | u8 val; | |
809 | ||
810 | val = ioread8(priv->regs + CTL_PWR_FAIL); | |
811 | return snprintf(buf, PAGE_SIZE, "0x%.2x\n", val); | |
812 | } | |
813 | ||
814 | static ssize_t pgood_show(struct device *dev, struct device_attribute *attr, | |
815 | char *buf) | |
816 | { | |
817 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
818 | return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_good(priv)); | |
819 | } | |
820 | ||
821 | static ssize_t penable_show(struct device *dev, struct device_attribute *attr, | |
822 | char *buf) | |
823 | { | |
824 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
825 | return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_enabled(priv)); | |
826 | } | |
827 | ||
828 | static ssize_t penable_store(struct device *dev, struct device_attribute *attr, | |
829 | const char *buf, size_t count) | |
830 | { | |
831 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
832 | unsigned long val; | |
833 | int ret; | |
834 | ||
f7b41276 JH |
835 | ret = kstrtoul(buf, 0, &val); |
836 | if (ret) | |
837 | return ret; | |
0e1d715b IS |
838 | |
839 | if (val) { | |
840 | ret = fpga_enable_power_supplies(priv); | |
841 | if (ret) | |
842 | return ret; | |
843 | } else { | |
844 | fpga_do_stop(priv); | |
845 | fpga_disable_power_supplies(priv); | |
846 | } | |
847 | ||
848 | return count; | |
849 | } | |
850 | ||
851 | static ssize_t program_show(struct device *dev, struct device_attribute *attr, | |
852 | char *buf) | |
853 | { | |
854 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
855 | return snprintf(buf, PAGE_SIZE, "%d\n", fpga_running(priv)); | |
856 | } | |
857 | ||
858 | static ssize_t program_store(struct device *dev, struct device_attribute *attr, | |
859 | const char *buf, size_t count) | |
860 | { | |
861 | struct fpga_dev *priv = dev_get_drvdata(dev); | |
862 | unsigned long val; | |
863 | int ret; | |
864 | ||
f7b41276 JH |
865 | ret = kstrtoul(buf, 0, &val); |
866 | if (ret) | |
867 | return ret; | |
0e1d715b IS |
868 | |
869 | /* We can't have an image writer and be programming simultaneously */ | |
870 | if (mutex_lock_interruptible(&priv->lock)) | |
871 | return -ERESTARTSYS; | |
872 | ||
873 | /* Program or Reset the FPGA's */ | |
874 | ret = val ? fpga_do_program(priv) : fpga_do_stop(priv); | |
875 | if (ret) | |
876 | goto out_unlock; | |
877 | ||
878 | /* Success */ | |
879 | ret = count; | |
880 | ||
881 | out_unlock: | |
882 | mutex_unlock(&priv->lock); | |
883 | return ret; | |
884 | } | |
885 | ||
886 | static DEVICE_ATTR(power_fail, S_IRUGO, pfail_show, NULL); | |
887 | static DEVICE_ATTR(power_good, S_IRUGO, pgood_show, NULL); | |
888 | static DEVICE_ATTR(power_enable, S_IRUGO | S_IWUSR, | |
889 | penable_show, penable_store); | |
890 | ||
891 | static DEVICE_ATTR(program, S_IRUGO | S_IWUSR, | |
892 | program_show, program_store); | |
893 | ||
894 | static struct attribute *fpga_attributes[] = { | |
895 | &dev_attr_power_fail.attr, | |
896 | &dev_attr_power_good.attr, | |
897 | &dev_attr_power_enable.attr, | |
898 | &dev_attr_program.attr, | |
899 | NULL, | |
900 | }; | |
901 | ||
902 | static const struct attribute_group fpga_attr_group = { | |
903 | .attrs = fpga_attributes, | |
904 | }; | |
905 | ||
906 | /* | |
907 | * OpenFirmware Device Subsystem | |
908 | */ | |
909 | ||
910 | #define SYS_REG_VERSION 0x00 | |
911 | #define SYS_REG_GEOGRAPHIC 0x10 | |
912 | ||
913 | static bool dma_filter(struct dma_chan *chan, void *data) | |
914 | { | |
915 | /* | |
916 | * DMA Channel #0 is the only acceptable device | |
917 | * | |
918 | * This probably won't survive an unload/load cycle of the Freescale | |
919 | * DMAEngine driver, but that won't be a problem | |
920 | */ | |
921 | return chan->chan_id == 0 && chan->device->dev_id == 0; | |
922 | } | |
923 | ||
924 | static int fpga_of_remove(struct platform_device *op) | |
925 | { | |
9093ca88 | 926 | struct fpga_dev *priv = platform_get_drvdata(op); |
0e1d715b IS |
927 | struct device *this_device = priv->miscdev.this_device; |
928 | ||
929 | sysfs_remove_group(&this_device->kobj, &fpga_attr_group); | |
930 | misc_deregister(&priv->miscdev); | |
931 | ||
932 | free_irq(priv->irq, priv); | |
933 | irq_dispose_mapping(priv->irq); | |
934 | ||
935 | /* make sure the power supplies are off */ | |
936 | fpga_disable_power_supplies(priv); | |
937 | ||
938 | /* unmap registers */ | |
939 | iounmap(priv->immr); | |
940 | iounmap(priv->regs); | |
941 | ||
942 | dma_release_channel(priv->chan); | |
943 | ||
944 | /* drop our reference to the private data structure */ | |
945 | kref_put(&priv->ref, fpga_dev_remove); | |
946 | return 0; | |
947 | } | |
948 | ||
949 | /* CTL-CPLD Version Register */ | |
950 | #define CTL_CPLD_VERSION 0x2000 | |
951 | ||
49334020 | 952 | static int fpga_of_probe(struct platform_device *op) |
0e1d715b IS |
953 | { |
954 | struct device_node *of_node = op->dev.of_node; | |
955 | struct device *this_device; | |
956 | struct fpga_dev *priv; | |
957 | dma_cap_mask_t mask; | |
958 | u32 ver; | |
959 | int ret; | |
960 | ||
961 | /* Allocate private data */ | |
962 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
963 | if (!priv) { | |
964 | dev_err(&op->dev, "Unable to allocate private data\n"); | |
965 | ret = -ENOMEM; | |
966 | goto out_return; | |
967 | } | |
968 | ||
969 | /* Setup the miscdevice */ | |
970 | priv->miscdev.minor = MISC_DYNAMIC_MINOR; | |
971 | priv->miscdev.name = drv_name; | |
972 | priv->miscdev.fops = &fpga_fops; | |
973 | ||
974 | kref_init(&priv->ref); | |
975 | ||
9093ca88 | 976 | platform_set_drvdata(op, priv); |
0e1d715b IS |
977 | priv->dev = &op->dev; |
978 | mutex_init(&priv->lock); | |
979 | init_completion(&priv->completion); | |
980 | videobuf_dma_init(&priv->vb); | |
981 | ||
982 | dev_set_drvdata(priv->dev, priv); | |
983 | dma_cap_zero(mask); | |
984 | dma_cap_set(DMA_MEMCPY, mask); | |
0e1d715b IS |
985 | dma_cap_set(DMA_SLAVE, mask); |
986 | dma_cap_set(DMA_SG, mask); | |
987 | ||
988 | /* Get control of DMA channel #0 */ | |
989 | priv->chan = dma_request_channel(mask, dma_filter, NULL); | |
990 | if (!priv->chan) { | |
991 | dev_err(&op->dev, "Unable to acquire DMA channel #0\n"); | |
992 | ret = -ENODEV; | |
993 | goto out_free_priv; | |
994 | } | |
995 | ||
996 | /* Remap the registers for use */ | |
997 | priv->regs = of_iomap(of_node, 0); | |
998 | if (!priv->regs) { | |
999 | dev_err(&op->dev, "Unable to ioremap registers\n"); | |
1000 | ret = -ENOMEM; | |
1001 | goto out_dma_release_channel; | |
1002 | } | |
1003 | ||
1004 | /* Remap the IMMR for use */ | |
1005 | priv->immr = ioremap(get_immrbase(), 0x100000); | |
1006 | if (!priv->immr) { | |
1007 | dev_err(&op->dev, "Unable to ioremap IMMR\n"); | |
1008 | ret = -ENOMEM; | |
1009 | goto out_unmap_regs; | |
1010 | } | |
1011 | ||
1012 | /* | |
1013 | * Check that external DMA is configured | |
1014 | * | |
1015 | * U-Boot does this for us, but we should check it and bail out if | |
1016 | * there is a problem. Failing to have this register setup correctly | |
1017 | * will cause the DMA controller to transfer a single cacheline | |
1018 | * worth of data, then wedge itself. | |
1019 | */ | |
1020 | if ((ioread32be(priv->immr + 0x114) & 0xE00) != 0xE00) { | |
1021 | dev_err(&op->dev, "External DMA control not configured\n"); | |
1022 | ret = -ENODEV; | |
1023 | goto out_unmap_immr; | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * Check the CTL-CPLD version | |
1028 | * | |
1029 | * This driver uses the CTL-CPLD DATA-FPGA power sequencer, and we | |
1030 | * don't want to run on any version of the CTL-CPLD that does not use | |
1031 | * a compatible register layout. | |
1032 | * | |
1033 | * v2: changed register layout, added power sequencer | |
1034 | * v3: added glitch filter on the i2c overcurrent/overtemp outputs | |
1035 | */ | |
1036 | ver = ioread8(priv->regs + CTL_CPLD_VERSION); | |
1037 | if (ver != 0x02 && ver != 0x03) { | |
1038 | dev_err(&op->dev, "CTL-CPLD is not version 0x02 or 0x03!\n"); | |
1039 | ret = -ENODEV; | |
1040 | goto out_unmap_immr; | |
1041 | } | |
1042 | ||
1043 | /* Set the exact size that the firmware image should be */ | |
1044 | ver = ioread32be(priv->regs + SYS_REG_VERSION); | |
1045 | priv->fw_size = (ver & (1 << 18)) ? FW_SIZE_EP2S130 : FW_SIZE_EP2S90; | |
1046 | ||
1047 | /* Find the correct IRQ number */ | |
1048 | priv->irq = irq_of_parse_and_map(of_node, 0); | |
1049 | if (priv->irq == NO_IRQ) { | |
1050 | dev_err(&op->dev, "Unable to find IRQ line\n"); | |
1051 | ret = -ENODEV; | |
1052 | goto out_unmap_immr; | |
1053 | } | |
1054 | ||
1055 | /* Request the IRQ */ | |
1056 | ret = request_irq(priv->irq, fpga_irq, IRQF_SHARED, drv_name, priv); | |
1057 | if (ret) { | |
1058 | dev_err(&op->dev, "Unable to request IRQ %d\n", priv->irq); | |
1059 | ret = -ENODEV; | |
1060 | goto out_irq_dispose_mapping; | |
1061 | } | |
1062 | ||
1063 | /* Reset and stop the FPGA's, just in case */ | |
1064 | fpga_do_stop(priv); | |
1065 | ||
1066 | /* Register the miscdevice */ | |
1067 | ret = misc_register(&priv->miscdev); | |
1068 | if (ret) { | |
1069 | dev_err(&op->dev, "Unable to register miscdevice\n"); | |
1070 | goto out_free_irq; | |
1071 | } | |
1072 | ||
1073 | /* Create the sysfs files */ | |
1074 | this_device = priv->miscdev.this_device; | |
1075 | dev_set_drvdata(this_device, priv); | |
1076 | ret = sysfs_create_group(&this_device->kobj, &fpga_attr_group); | |
1077 | if (ret) { | |
1078 | dev_err(&op->dev, "Unable to create sysfs files\n"); | |
1079 | goto out_misc_deregister; | |
1080 | } | |
1081 | ||
1082 | dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n", | |
1083 | (ver & (1 << 17)) ? "Correlator" : "Digitizer", | |
1084 | (ver & (1 << 16)) ? "B" : "A", | |
1085 | (ver & (1 << 18)) ? "EP2S130" : "EP2S90"); | |
1086 | ||
1087 | return 0; | |
1088 | ||
1089 | out_misc_deregister: | |
1090 | misc_deregister(&priv->miscdev); | |
1091 | out_free_irq: | |
1092 | free_irq(priv->irq, priv); | |
1093 | out_irq_dispose_mapping: | |
1094 | irq_dispose_mapping(priv->irq); | |
1095 | out_unmap_immr: | |
1096 | iounmap(priv->immr); | |
1097 | out_unmap_regs: | |
1098 | iounmap(priv->regs); | |
1099 | out_dma_release_channel: | |
1100 | dma_release_channel(priv->chan); | |
1101 | out_free_priv: | |
1102 | kref_put(&priv->ref, fpga_dev_remove); | |
1103 | out_return: | |
1104 | return ret; | |
1105 | } | |
1106 | ||
1107 | static struct of_device_id fpga_of_match[] = { | |
1108 | { .compatible = "carma,fpga-programmer", }, | |
1109 | {}, | |
1110 | }; | |
1111 | ||
49334020 | 1112 | static struct platform_driver fpga_of_driver = { |
0e1d715b IS |
1113 | .probe = fpga_of_probe, |
1114 | .remove = fpga_of_remove, | |
1115 | .driver = { | |
1116 | .name = drv_name, | |
1117 | .of_match_table = fpga_of_match, | |
1118 | .owner = THIS_MODULE, | |
1119 | }, | |
1120 | }; | |
1121 | ||
1122 | /* | |
1123 | * Module Init / Exit | |
1124 | */ | |
1125 | ||
1126 | static int __init fpga_init(void) | |
1127 | { | |
1128 | led_trigger_register_simple("fpga", &ledtrig_fpga); | |
49334020 | 1129 | return platform_driver_register(&fpga_of_driver); |
0e1d715b IS |
1130 | } |
1131 | ||
1132 | static void __exit fpga_exit(void) | |
1133 | { | |
49334020 | 1134 | platform_driver_unregister(&fpga_of_driver); |
0e1d715b IS |
1135 | led_trigger_unregister_simple(ledtrig_fpga); |
1136 | } | |
1137 | ||
1138 | MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>"); | |
1139 | MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer"); | |
1140 | MODULE_LICENSE("GPL"); | |
1141 | ||
1142 | module_init(fpga_init); | |
1143 | module_exit(fpga_exit); |