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Merge 5.18-rc5 into char-misc-next
[linux-block.git] / drivers / misc / cardreader / rts5261.c
CommitLineData
c0e5f4e7
RF		 1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Rui FENG <rui_feng@realsil.com.cn>
8 * Wei WANG <wei_wang@realsil.com.cn>
9 */
10
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/rtsx_pci.h>
14
15#include "rts5261.h"
16#include "rtsx_pcr.h"
17
18static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
19{
20 u8 val;
21
22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
23 return val & IC_VERSION_MASK;
24}
25
26static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
27{
28 u8 driving_3v3[4][3] = {
c0e5f4e7 29 {0x96, 0x96, 0x96},
c0e5f4e7 30 {0x96, 0x96, 0x96},
6f61dd28
RF		 31 {0x7F, 0x7F, 0x7F},
32 {0x13, 0x13, 0x13},
c0e5f4e7
RF		 33 };
34 u8 driving_1v8[4][3] = {
6f61dd28 35 {0xB3, 0xB3, 0xB3},
c0e5f4e7
RF		 36 {0x3A, 0x3A, 0x3A},
37 {0xE6, 0xE6, 0xE6},
6f61dd28 38 {0x99, 0x99, 0x99},
c0e5f4e7
RF		 39 };
40 u8 (*driving)[3], drive_sel;
41
42 if (voltage == OUTPUT_3V3) {
43 driving = driving_3v3;
44 drive_sel = pcr->sd30_drive_sel_3v3;
45 } else {
46 driving = driving_1v8;
47 drive_sel = pcr->sd30_drive_sel_1v8;
48 }
49
50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
51 0xFF, driving[drive_sel][0]);
52
53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
54 0xFF, driving[drive_sel][1]);
55
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
57 0xFF, driving[drive_sel][2]);
58}
59
60static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
61{
22bf3251 62 struct pci_dev *pdev = pcr->pci;
c0e5f4e7 63 u32 reg;
22bf3251 64
c0e5f4e7 65 /* 0x814~0x817 */
22bf3251 66 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
c0e5f4e7
RF		 67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
68
69 if (!rts5261_vendor_setting_valid(reg)) {
5b0f429e
RF		 70 /* Not support MMC default */
71 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
c0e5f4e7
RF		 72 pcr_dbg(pcr, "skip fetch vendor setting\n");
73 return;
74 }
75
5b0f429e
RF		 76 if (!rts5261_reg_check_mmc_support(reg))
77 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
78
79 /* TO do: need to add rtd3 function */
80 pcr->rtd3_en = rts5261_reg_to_rtd3(reg);
81
c0e5f4e7
RF		 82 if (rts5261_reg_check_reverse_socket(reg))
83 pcr->flags |= PCR_REVERSE_SOCKET;
84
85 /* 0x724~0x727 */
22bf3251 86 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
c0e5f4e7
RF		 87 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
88
89 pcr->aspm_en = rts5261_reg_to_aspm(reg);
90 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
91 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
92}
93
71732e24 94static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
c0e5f4e7
RF		 95{
96 /* Set relink_time to 0 */
97 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
98 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
99 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
100 RELINK_TIME_MASK, 0);
101
102 if (pm_state == HOST_ENTER_S3)
103 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
104 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
105
86f4c65f
RW		 106 if (!runtime) {
107 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
108 CD_RESUME_EN_MASK, 0);
109 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
110 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
111 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
112
113 } else {
114 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
115 FORCE_PM_CONTROL | FORCE_PM_VALUE, 0);
116
117 rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
118 RTS5261_INFORM_RTD3_COLD, RTS5261_INFORM_RTD3_COLD);
119 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
120 RTS5261_FORCE_PRSNT_LOW, RTS5261_FORCE_PRSNT_LOW);
121
122 }
123
c0e5f4e7
RF		 124 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
125 SSC_POWER_DOWN, SSC_POWER_DOWN);
126}
127
128static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
129{
130 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
131 LED_SHINE_MASK, LED_SHINE_EN);
132}
133
134static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
135{
136 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
137 LED_SHINE_MASK, LED_SHINE_DISABLE);
138}
139
140static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
141{
142 return rtsx_pci_write_register(pcr, GPIO_CTL,
143 0x02, 0x02);
144}
145
146static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
147{
148 return rtsx_pci_write_register(pcr, GPIO_CTL,
149 0x02, 0x00);
150}
151
152/* SD Pull Control Enable:
153 * SD_DAT[3:0] ==> pull up
154 * SD_CD ==> pull up
155 * SD_WP ==> pull up
156 * SD_CMD ==> pull up
157 * SD_CLK ==> pull down
158 */
159static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
160 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
161 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
162 0,
163};
164
165/* SD Pull Control Disable:
166 * SD_DAT[3:0] ==> pull down
167 * SD_CD ==> pull up
168 * SD_WP ==> pull down
169 * SD_CMD ==> pull down
170 * SD_CLK ==> pull down
171 */
172static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
173 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
174 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
175 0,
176};
177
178static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
179{
180 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
181 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
182 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
183 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
184 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
185 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
186
187 return 0;
188}
189
190static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
191{
192 struct rtsx_cr_option *option = &pcr->option;
193
194 if (option->ocp_en)
195 rtsx_pci_enable_ocp(pcr);
196
1672617d
RF		 197 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
198 CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD);
c0e5f4e7
RF		 199
200 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
201 RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
202 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
203 RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
204
205 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
206 RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
207
208 msleep(20);
209
210 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
211
212 /* Initialize SD_CFG1 register */
213 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
214 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
215
216 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
217 0xFF, SD20_RX_POS_EDGE);
218 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
219 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
220 SD_STOP | SD_CLR_ERR);
221
222 /* Reset SD_CFG3 register */
223 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
224 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
225 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
226 SD30_CLK_STOP_CFG0, 0);
227
228 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
229 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
230 rts5261_sd_set_sample_push_timing_sd30(pcr);
231
232 return 0;
233}
234
235static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
236{
237 int err;
238 u16 val = 0;
239
240 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
241 RTS5261_PUPDC, RTS5261_PUPDC);
242
243 switch (voltage) {
244 case OUTPUT_3V3:
245 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
246 val |= PHY_TUNE_SDBUS_33;
247 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
248 if (err < 0)
249 return err;
250
251 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
252 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
253 rtsx_pci_write_register(pcr, SD_PAD_CTL,
254 SD_IO_USING_1V8, 0);
255 break;
256 case OUTPUT_1V8:
257 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
258 val &= ~PHY_TUNE_SDBUS_33;
259 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
260 if (err < 0)
261 return err;
262
263 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
264 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
265 rtsx_pci_write_register(pcr, SD_PAD_CTL,
266 SD_IO_USING_1V8, SD_IO_USING_1V8);
267 break;
268 default:
269 return -EINVAL;
270 }
271
272 /* set pad drive */
273 rts5261_fill_driving(pcr, voltage);
274
275 return 0;
276}
277
278static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
279{
280 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
281 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
282 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
283 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
284 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
285 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
286}
287
288static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
289{
290 rts5261_stop_cmd(pcr);
291 rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
292
293}
294
295static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
296{
297 u8 val = 0;
298
299 val = SD_OCP_INT_EN | SD_DETECT_EN;
c28e3fb2
RF		 300 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
301 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
302 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
c0e5f4e7
RF		 303 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
304
305}
306
307static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
308{
309 u8 mask = 0;
310
311 mask = SD_OCP_INT_EN | SD_DETECT_EN;
312 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
313 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
314 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
315
316}
317
318static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
319{
320 int err = 0;
321
322 rts5261_card_before_power_off(pcr);
323 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
324 RTS5261_LDO_POWERON_MASK, 0);
325
1672617d
RF		 326 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0,
327 CFG_SD_POW_AUTO_PD, 0);
c0e5f4e7
RF		 328 if (pcr->option.ocp_en)
329 rtsx_pci_disable_ocp(pcr);
330
331 return err;
332}
333
334static void rts5261_init_ocp(struct rtsx_pcr *pcr)
335{
336 struct rtsx_cr_option *option = &pcr->option;
337
338 if (option->ocp_en) {
339 u8 mask, val;
340
341 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
342 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
343 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
344
345 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
346 RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
347
348 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
349 RTS5261_LDO1_OCP_LMT_THD_MASK,
350 RTS5261_LDO1_LMT_THD_2000);
351
352 mask = SD_OCP_GLITCH_MASK;
353 val = pcr->hw_param.ocp_glitch;
354 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
355
356 rts5261_enable_ocp(pcr);
357 } else {
358 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
359 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
360 }
361}
362
363static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
364{
365 u8 mask = 0;
366 u8 val = 0;
367
368 mask = SD_OCP_INT_CLR | SD_OC_CLR;
369 val = SD_OCP_INT_CLR | SD_OC_CLR;
370
371 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
372
c28e3fb2 373 udelay(1000);
c0e5f4e7
RF		 374 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
375
376}
377
378static void rts5261_process_ocp(struct rtsx_pcr *pcr)
379{
380 if (!pcr->option.ocp_en)
381 return;
382
383 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
384
385 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
c28e3fb2 386 rts5261_clear_ocpstat(pcr);
c0e5f4e7
RF		 387 rts5261_card_power_off(pcr, RTSX_SD_CARD);
388 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
c0e5f4e7
RF		 389 pcr->ocp_stat = 0;
390 }
391
392}
393
394static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
395{
22bf3251 396 struct pci_dev *pdev = pcr->pci;
c0e5f4e7
RF		 397 int retval;
398 u32 lval, i;
399 u8 valid, efuse_valid, tmp;
400
401 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
402 REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
403 REG_EFUSE_POR | REG_EFUSE_POWERON);
404 udelay(1);
405 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
406 RTS5261_EFUSE_ADDR_MASK, 0x00);
407 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
408 RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
409 RTS5261_EFUSE_ENABLE);
410
411 /* Wait transfer end */
412 for (i = 0; i < MAX_RW_REG_CNT; i++) {
413 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
414 if ((tmp & 0x80) == 0)
415 break;
416 }
417 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
418 efuse_valid = ((tmp & 0x0C) >> 2);
419 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
420
421 if (efuse_valid == 0) {
22bf3251 422 retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
c0e5f4e7
RF		 423 if (retval != 0)
424 pcr_dbg(pcr, "read 0x814 DW fail\n");
425 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
426 /* 0x816 */
427 valid = (u8)((lval >> 16) & 0x03);
428 pcr_dbg(pcr, "0x816: %d\n", valid);
429 }
430 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
431 REG_EFUSE_POR, 0);
432 pcr_dbg(pcr, "Disable efuse por!\n");
433
22bf3251 434 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
c0e5f4e7 435 lval = lval & 0x00FFFFFF;
22bf3251 436 retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval);
c0e5f4e7
RF		 437 if (retval != 0)
438 pcr_dbg(pcr, "write config fail\n");
439
440 return retval;
441}
442
443static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
444{
22bf3251 445 struct pci_dev *pdev = pcr->pci;
ed86a987 446 int l1ss;
c0e5f4e7
RF		 447 u32 lval;
448 struct rtsx_cr_option *option = &pcr->option;
449
ed86a987
BH		 450 l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
451 if (!l1ss)
452 return;
453
454 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
c0e5f4e7 455
7a4462a9 456 if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
c0e5f4e7
RF		 457 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
458 else
459 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
460
7a4462a9 461 if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
c0e5f4e7
RF		 462 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
463 else
464 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
465
7a4462a9 466 if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
c0e5f4e7
RF		 467 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
468 else
469 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
470
7a4462a9 471 if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
c0e5f4e7
RF		 472 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
473 else
474 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
475
476 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
477 if (option->ltr_en) {
478 u16 val;
479
22bf3251 480 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
c0e5f4e7
RF		 481 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
482 option->ltr_enabled = true;
483 option->ltr_active = true;
484 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
485 } else {
486 option->ltr_enabled = false;
487 }
488 }
489
490 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
491 | PM_L1_1_EN | PM_L1_2_EN))
492 option->force_clkreq_0 = false;
493 else
494 option->force_clkreq_0 = true;
495}
496
497static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
498{
499 struct rtsx_cr_option *option = &pcr->option;
1672617d 500 u32 val;
c0e5f4e7
RF		 501
502 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
503 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
504
505 rts5261_init_from_cfg(pcr);
506 rts5261_init_from_hw(pcr);
507
508 /* power off efuse */
509 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
510 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
511 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
512 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
513 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
514
1672617d
RF		 515 if (is_version_higher_than(pcr, PID_5261, IC_VER_B)) {
516 val = rtsx_pci_readl(pcr, RTSX_DUM_REG);
517 rtsx_pci_writel(pcr, RTSX_DUM_REG, val | 0x1);
518 }
c0e5f4e7
RF		 519 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
520 RTS5261_AUX_CLK_16M_EN, 0);
521
522 /* Release PRSNT# */
523 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
524 RTS5261_FORCE_PRSNT_LOW, 0);
525 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
526 FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
527
528 rtsx_pci_write_register(pcr, PCLK_CTL,
529 PCLK_MODE_SEL, PCLK_MODE_SEL);
530
531 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
532 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
533
534 /* LED shine disabled, set initial shine cycle period */
535 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
536
537 /* Configure driving */
538 rts5261_fill_driving(pcr, OUTPUT_3V3);
539
1da3c515
RF		 540 if (pcr->flags & PCR_REVERSE_SOCKET)
541 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
542 else
543 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
544
c0e5f4e7
RF		 545 /*
546 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
547 * to drive low, and we forcibly request clock.
548 */
549 if (option->force_clkreq_0)
550 rtsx_pci_write_register(pcr, PETXCFG,
551 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
552 else
553 rtsx_pci_write_register(pcr, PETXCFG,
554 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
555
c28e3fb2 556 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
86f4c65f
RW		 557
558 if (pcr->rtd3_en) {
559 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01);
560 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
561 FORCE_PM_CONTROL | FORCE_PM_VALUE,
562 FORCE_PM_CONTROL | FORCE_PM_VALUE);
563 } else {
564 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00);
565 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
566 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
567 }
568 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00);
c0e5f4e7
RF		 569
570 /* Clear Enter RTD3_cold Information*/
571 rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
572 RTS5261_INFORM_RTD3_COLD, 0);
573
574 return 0;
575}
576
577static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
578{
0a3bbf92
RF		 579 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
580 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
581
c0e5f4e7
RF		 582 if (pcr->aspm_enabled == enable)
583 return;
584
0a3bbf92
RF		 585 val |= (pcr->aspm_en & 0x02);
586 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
3d1e7aa8
BH		 587 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
588 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
c0e5f4e7 589 pcr->aspm_enabled = enable;
c0e5f4e7
RF		 590}
591
592static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
593{
0a3bbf92
RF		 594 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
595 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
596
c0e5f4e7
RF		 597 if (pcr->aspm_enabled == enable)
598 return;
599
3d1e7aa8
BH		 600 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
601 PCI_EXP_LNKCTL_ASPMC, 0);
0a3bbf92 602 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
c0e5f4e7
RF		 603 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
604 udelay(10);
605 pcr->aspm_enabled = enable;
606}
607
608static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
609{
610 if (enable)
611 rts5261_enable_aspm(pcr, true);
612 else
613 rts5261_disable_aspm(pcr, false);
614}
615
616static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
617{
618 struct rtsx_cr_option *option = &pcr->option;
619 int aspm_L1_1, aspm_L1_2;
620 u8 val = 0;
621
622 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
623 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
624
625 if (active) {
626 /* run, latency: 60us */
627 if (aspm_L1_1)
628 val = option->ltr_l1off_snooze_sspwrgate;
629 } else {
630 /* l1off, latency: 300us */
631 if (aspm_L1_2)
632 val = option->ltr_l1off_sspwrgate;
633 }
634
635 rtsx_set_l1off_sub(pcr, val);
636}
637
638static const struct pcr_ops rts5261_pcr_ops = {
639 .fetch_vendor_settings = rtsx5261_fetch_vendor_settings,
640 .turn_on_led = rts5261_turn_on_led,
641 .turn_off_led = rts5261_turn_off_led,
642 .extra_init_hw = rts5261_extra_init_hw,
643 .enable_auto_blink = rts5261_enable_auto_blink,
644 .disable_auto_blink = rts5261_disable_auto_blink,
645 .card_power_on = rts5261_card_power_on,
646 .card_power_off = rts5261_card_power_off,
647 .switch_output_voltage = rts5261_switch_output_voltage,
648 .force_power_down = rts5261_force_power_down,
649 .stop_cmd = rts5261_stop_cmd,
650 .set_aspm = rts5261_set_aspm,
651 .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
652 .enable_ocp = rts5261_enable_ocp,
653 .disable_ocp = rts5261_disable_ocp,
654 .init_ocp = rts5261_init_ocp,
655 .process_ocp = rts5261_process_ocp,
656 .clear_ocpstat = rts5261_clear_ocpstat,
657};
658
659static inline u8 double_ssc_depth(u8 depth)
660{
661 return ((depth > 1) ? (depth - 1) : depth);
662}
663
664int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
665 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
666{
667 int err, clk;
4d616831
RF		 668 u16 n;
669 u8 clk_divider, mcu_cnt, div;
c0e5f4e7
RF		 670 static const u8 depth[] = {
671 [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
672 [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
673 [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
674 [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
675 };
676
677 if (initial_mode) {
678 /* We use 250k(around) here, in initial stage */
5eefe22d 679 if (is_version_higher_than(pcr, PID_5261, IC_VER_C)) {
c18c1f10
RF		 680 clk_divider = SD_CLK_DIVIDE_256;
681 card_clock = 60000000;
682 } else {
683 clk_divider = SD_CLK_DIVIDE_128;
684 card_clock = 30000000;
685 }
c0e5f4e7
RF		 686 } else {
687 clk_divider = SD_CLK_DIVIDE_0;
688 }
689 err = rtsx_pci_write_register(pcr, SD_CFG1,
690 SD_CLK_DIVIDE_MASK, clk_divider);
691 if (err < 0)
692 return err;
693
694 card_clock /= 1000000;
695 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
696
697 clk = card_clock;
698 if (!initial_mode && double_clk)
699 clk = card_clock * 2;
700 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
701 clk, pcr->cur_clock);
702
703 if (clk == pcr->cur_clock)
704 return 0;
705
706 if (pcr->ops->conv_clk_and_div_n)
4d616831 707 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
c0e5f4e7 708 else
4d616831 709 n = clk - 4;
c0e5f4e7
RF		 710 if ((clk <= 4) || (n > 396))
711 return -EINVAL;
712
4d616831 713 mcu_cnt = 125/clk + 3;
c0e5f4e7
RF		 714 if (mcu_cnt > 15)
715 mcu_cnt = 15;
716
717 div = CLK_DIV_1;
718 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
719 if (pcr->ops->conv_clk_and_div_n) {
720 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
721 DIV_N_TO_CLK) * 2;
4d616831 722 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
c0e5f4e7
RF		 723 CLK_TO_DIV_N);
724 } else {
725 n = (n + 4) * 2 - 4;
726 }
727 div++;
728 }
729
5eefe22d 730 n = (n / 2) - 1;
c0e5f4e7
RF		 731 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
732
733 ssc_depth = depth[ssc_depth];
734 if (double_clk)
735 ssc_depth = double_ssc_depth(ssc_depth);
736
737 if (ssc_depth) {
738 if (div == CLK_DIV_2) {
739 if (ssc_depth > 1)
740 ssc_depth -= 1;
741 else
742 ssc_depth = RTS5261_SSC_DEPTH_8M;
743 } else if (div == CLK_DIV_4) {
744 if (ssc_depth > 2)
745 ssc_depth -= 2;
746 else
747 ssc_depth = RTS5261_SSC_DEPTH_8M;
748 } else if (div == CLK_DIV_8) {
749 if (ssc_depth > 3)
750 ssc_depth -= 3;
751 else
752 ssc_depth = RTS5261_SSC_DEPTH_8M;
753 }
754 } else {
755 ssc_depth = 0;
756 }
757 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
758
759 rtsx_pci_init_cmd(pcr);
760 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
761 CLK_LOW_FREQ, CLK_LOW_FREQ);
762 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
763 0xFF, (div << 4) | mcu_cnt);
764 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
765 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
766 SSC_DEPTH_MASK, ssc_depth);
767 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
768 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
769 if (vpclk) {
770 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
771 PHASE_NOT_RESET, 0);
772 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
773 PHASE_NOT_RESET, 0);
774 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
775 PHASE_NOT_RESET, PHASE_NOT_RESET);
776 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
777 PHASE_NOT_RESET, PHASE_NOT_RESET);
778 }
779
780 err = rtsx_pci_send_cmd(pcr, 2000);
781 if (err < 0)
782 return err;
783
784 /* Wait SSC clock stable */
785 udelay(SSC_CLOCK_STABLE_WAIT);
786 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
787 if (err < 0)
788 return err;
789
790 pcr->cur_clock = clk;
791 return 0;
792
793}
794
795void rts5261_init_params(struct rtsx_pcr *pcr)
796{
797 struct rtsx_cr_option *option = &pcr->option;
798 struct rtsx_hw_param *hw_param = &pcr->hw_param;
5afe8021 799 u8 val;
c0e5f4e7
RF		 800
801 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
5afe8021
RF		 802 rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val);
803 if (!(val & RTS5261_EXPRESS_LINK_FAIL_MASK))
804 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
c0e5f4e7
RF		 805 pcr->num_slots = 1;
806 pcr->ops = &rts5261_pcr_ops;
807
808 pcr->flags = 0;
809 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
6f61dd28
RF		 810 pcr->sd30_drive_sel_1v8 = 0x00;
811 pcr->sd30_drive_sel_3v3 = 0x00;
c0e5f4e7 812 pcr->aspm_en = ASPM_L1_EN;
3df4fce7 813 pcr->aspm_mode = ASPM_MODE_REG;
4686392c 814 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
c0e5f4e7
RF		 815 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
816
817 pcr->ic_version = rts5261_get_ic_version(pcr);
818 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
819 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
820
821 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
822
823 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
824 | LTR_L1SS_PWR_GATE_EN);
825 option->ltr_en = true;
826
827 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
828 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
829 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
830 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
831 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
832 option->ltr_l1off_sspwrgate = 0x7F;
833 option->ltr_l1off_snooze_sspwrgate = 0x78;
c0e5f4e7
RF		 834
835 option->ocp_en = 1;
836 hw_param->interrupt_en |= SD_OC_INT_EN;
837 hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
838 option->sd_800mA_ocp_thd = RTS5261_LDO1_OCP_THD_1040;
839}
Linux 6.x block layer and io_uring tree(s)