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misc: rtsx: Fix aspm for RTS5261
[linux-block.git] / drivers / misc / cardreader / rts5261.c
CommitLineData
c0e5f4e7
RF		 1// SPDX-License-Identifier: GPL-2.0-or-later
2/* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Rui FENG <rui_feng@realsil.com.cn>
8 * Wei WANG <wei_wang@realsil.com.cn>
9 */
10
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/rtsx_pci.h>
14
15#include "rts5261.h"
16#include "rtsx_pcr.h"
17
18static u8 rts5261_get_ic_version(struct rtsx_pcr *pcr)
19{
20 u8 val;
21
22 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
23 return val & IC_VERSION_MASK;
24}
25
26static void rts5261_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
27{
28 u8 driving_3v3[4][3] = {
29 {0x13, 0x13, 0x13},
30 {0x96, 0x96, 0x96},
31 {0x7F, 0x7F, 0x7F},
32 {0x96, 0x96, 0x96},
33 };
34 u8 driving_1v8[4][3] = {
35 {0x99, 0x99, 0x99},
36 {0x3A, 0x3A, 0x3A},
37 {0xE6, 0xE6, 0xE6},
38 {0xB3, 0xB3, 0xB3},
39 };
40 u8 (*driving)[3], drive_sel;
41
42 if (voltage == OUTPUT_3V3) {
43 driving = driving_3v3;
44 drive_sel = pcr->sd30_drive_sel_3v3;
45 } else {
46 driving = driving_1v8;
47 drive_sel = pcr->sd30_drive_sel_1v8;
48 }
49
50 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
51 0xFF, driving[drive_sel][0]);
52
53 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
54 0xFF, driving[drive_sel][1]);
55
56 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
57 0xFF, driving[drive_sel][2]);
58}
59
60static void rtsx5261_fetch_vendor_settings(struct rtsx_pcr *pcr)
61{
22bf3251 62 struct pci_dev *pdev = pcr->pci;
c0e5f4e7 63 u32 reg;
22bf3251 64
c0e5f4e7 65 /* 0x814~0x817 */
22bf3251 66 pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
c0e5f4e7
RF		 67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
68
69 if (!rts5261_vendor_setting_valid(reg)) {
70 pcr_dbg(pcr, "skip fetch vendor setting\n");
71 return;
72 }
73
74 pcr->card_drive_sel &= 0x3F;
75 pcr->card_drive_sel |= rts5261_reg_to_card_drive_sel(reg);
76
77 if (rts5261_reg_check_reverse_socket(reg))
78 pcr->flags |= PCR_REVERSE_SOCKET;
79
80 /* 0x724~0x727 */
22bf3251 81 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
c0e5f4e7
RF		 82 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
83
84 pcr->aspm_en = rts5261_reg_to_aspm(reg);
85 pcr->sd30_drive_sel_1v8 = rts5261_reg_to_sd30_drive_sel_1v8(reg);
86 pcr->sd30_drive_sel_3v3 = rts5261_reg_to_sd30_drive_sel_3v3(reg);
87}
88
89static void rts5261_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
90{
91 /* Set relink_time to 0 */
92 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
93 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
94 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
95 RELINK_TIME_MASK, 0);
96
97 if (pm_state == HOST_ENTER_S3)
98 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
99 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
100
101 rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
102 SSC_POWER_DOWN, SSC_POWER_DOWN);
103}
104
105static int rts5261_enable_auto_blink(struct rtsx_pcr *pcr)
106{
107 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
108 LED_SHINE_MASK, LED_SHINE_EN);
109}
110
111static int rts5261_disable_auto_blink(struct rtsx_pcr *pcr)
112{
113 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
114 LED_SHINE_MASK, LED_SHINE_DISABLE);
115}
116
117static int rts5261_turn_on_led(struct rtsx_pcr *pcr)
118{
119 return rtsx_pci_write_register(pcr, GPIO_CTL,
120 0x02, 0x02);
121}
122
123static int rts5261_turn_off_led(struct rtsx_pcr *pcr)
124{
125 return rtsx_pci_write_register(pcr, GPIO_CTL,
126 0x02, 0x00);
127}
128
129/* SD Pull Control Enable:
130 * SD_DAT[3:0] ==> pull up
131 * SD_CD ==> pull up
132 * SD_WP ==> pull up
133 * SD_CMD ==> pull up
134 * SD_CLK ==> pull down
135 */
136static const u32 rts5261_sd_pull_ctl_enable_tbl[] = {
137 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
138 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
139 0,
140};
141
142/* SD Pull Control Disable:
143 * SD_DAT[3:0] ==> pull down
144 * SD_CD ==> pull up
145 * SD_WP ==> pull down
146 * SD_CMD ==> pull down
147 * SD_CLK ==> pull down
148 */
149static const u32 rts5261_sd_pull_ctl_disable_tbl[] = {
150 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
151 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
152 0,
153};
154
155static int rts5261_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
156{
157 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
158 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
159 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
160 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
161 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
162 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
163
164 return 0;
165}
166
167static int rts5261_card_power_on(struct rtsx_pcr *pcr, int card)
168{
169 struct rtsx_cr_option *option = &pcr->option;
170
171 if (option->ocp_en)
172 rtsx_pci_enable_ocp(pcr);
173
174
175 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG1,
176 RTS5261_LDO1_TUNE_MASK, RTS5261_LDO1_33);
177 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
178 RTS5261_LDO1_POWERON, RTS5261_LDO1_POWERON);
179
180 rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
181 RTS5261_LDO3318_POWERON, RTS5261_LDO3318_POWERON);
182
183 msleep(20);
184
185 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
186
187 /* Initialize SD_CFG1 register */
188 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
189 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT);
190
191 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
192 0xFF, SD20_RX_POS_EDGE);
193 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
194 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
195 SD_STOP | SD_CLR_ERR);
196
197 /* Reset SD_CFG3 register */
198 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
199 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
200 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 |
201 SD30_CLK_STOP_CFG0, 0);
202
203 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
204 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
205 rts5261_sd_set_sample_push_timing_sd30(pcr);
206
207 return 0;
208}
209
210static int rts5261_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
211{
212 int err;
213 u16 val = 0;
214
215 rtsx_pci_write_register(pcr, RTS5261_CARD_PWR_CTL,
216 RTS5261_PUPDC, RTS5261_PUPDC);
217
218 switch (voltage) {
219 case OUTPUT_3V3:
220 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
221 val |= PHY_TUNE_SDBUS_33;
222 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
223 if (err < 0)
224 return err;
225
226 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
227 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_33);
228 rtsx_pci_write_register(pcr, SD_PAD_CTL,
229 SD_IO_USING_1V8, 0);
230 break;
231 case OUTPUT_1V8:
232 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val);
233 val &= ~PHY_TUNE_SDBUS_33;
234 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val);
235 if (err < 0)
236 return err;
237
238 rtsx_pci_write_register(pcr, RTS5261_DV3318_CFG,
239 RTS5261_DV3318_TUNE_MASK, RTS5261_DV3318_18);
240 rtsx_pci_write_register(pcr, SD_PAD_CTL,
241 SD_IO_USING_1V8, SD_IO_USING_1V8);
242 break;
243 default:
244 return -EINVAL;
245 }
246
247 /* set pad drive */
248 rts5261_fill_driving(pcr, voltage);
249
250 return 0;
251}
252
253static void rts5261_stop_cmd(struct rtsx_pcr *pcr)
254{
255 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
256 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
257 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
258 RTS5260_DMA_RST | RTS5260_ADMA3_RST,
259 RTS5260_DMA_RST | RTS5260_ADMA3_RST);
260 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
261}
262
263static void rts5261_card_before_power_off(struct rtsx_pcr *pcr)
264{
265 rts5261_stop_cmd(pcr);
266 rts5261_switch_output_voltage(pcr, OUTPUT_3V3);
267
268}
269
270static void rts5261_enable_ocp(struct rtsx_pcr *pcr)
271{
272 u8 val = 0;
273
274 val = SD_OCP_INT_EN | SD_DETECT_EN;
c28e3fb2
RF		 275 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
276 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
277 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
c0e5f4e7
RF		 278 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
279
280}
281
282static void rts5261_disable_ocp(struct rtsx_pcr *pcr)
283{
284 u8 mask = 0;
285
286 mask = SD_OCP_INT_EN | SD_DETECT_EN;
287 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
288 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
289 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
290
291}
292
293static int rts5261_card_power_off(struct rtsx_pcr *pcr, int card)
294{
295 int err = 0;
296
297 rts5261_card_before_power_off(pcr);
298 err = rtsx_pci_write_register(pcr, RTS5261_LDO1233318_POW_CTL,
299 RTS5261_LDO_POWERON_MASK, 0);
300
301 if (pcr->option.ocp_en)
302 rtsx_pci_disable_ocp(pcr);
303
304 return err;
305}
306
307static void rts5261_init_ocp(struct rtsx_pcr *pcr)
308{
309 struct rtsx_cr_option *option = &pcr->option;
310
311 if (option->ocp_en) {
312 u8 mask, val;
313
314 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
315 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN,
316 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN);
317
318 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
319 RTS5261_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd);
320
321 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
322 RTS5261_LDO1_OCP_LMT_THD_MASK,
323 RTS5261_LDO1_LMT_THD_2000);
324
325 mask = SD_OCP_GLITCH_MASK;
326 val = pcr->hw_param.ocp_glitch;
327 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
328
329 rts5261_enable_ocp(pcr);
330 } else {
331 rtsx_pci_write_register(pcr, RTS5261_LDO1_CFG0,
332 RTS5261_LDO1_OCP_EN | RTS5261_LDO1_OCP_LMT_EN, 0);
333 }
334}
335
336static void rts5261_clear_ocpstat(struct rtsx_pcr *pcr)
337{
338 u8 mask = 0;
339 u8 val = 0;
340
341 mask = SD_OCP_INT_CLR | SD_OC_CLR;
342 val = SD_OCP_INT_CLR | SD_OC_CLR;
343
344 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
345
c28e3fb2 346 udelay(1000);
c0e5f4e7
RF		 347 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
348
349}
350
351static void rts5261_process_ocp(struct rtsx_pcr *pcr)
352{
353 if (!pcr->option.ocp_en)
354 return;
355
356 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
357
358 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
c28e3fb2 359 rts5261_clear_ocpstat(pcr);
c0e5f4e7
RF		 360 rts5261_card_power_off(pcr, RTSX_SD_CARD);
361 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
c0e5f4e7
RF		 362 pcr->ocp_stat = 0;
363 }
364
365}
366
367static int rts5261_init_from_hw(struct rtsx_pcr *pcr)
368{
22bf3251 369 struct pci_dev *pdev = pcr->pci;
c0e5f4e7
RF		 370 int retval;
371 u32 lval, i;
372 u8 valid, efuse_valid, tmp;
373
374 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
375 REG_EFUSE_POR | REG_EFUSE_POWER_MASK,
376 REG_EFUSE_POR | REG_EFUSE_POWERON);
377 udelay(1);
378 rtsx_pci_write_register(pcr, RTS5261_EFUSE_ADDR,
379 RTS5261_EFUSE_ADDR_MASK, 0x00);
380 rtsx_pci_write_register(pcr, RTS5261_EFUSE_CTL,
381 RTS5261_EFUSE_ENABLE | RTS5261_EFUSE_MODE_MASK,
382 RTS5261_EFUSE_ENABLE);
383
384 /* Wait transfer end */
385 for (i = 0; i < MAX_RW_REG_CNT; i++) {
386 rtsx_pci_read_register(pcr, RTS5261_EFUSE_CTL, &tmp);
387 if ((tmp & 0x80) == 0)
388 break;
389 }
390 rtsx_pci_read_register(pcr, RTS5261_EFUSE_READ_DATA, &tmp);
391 efuse_valid = ((tmp & 0x0C) >> 2);
392 pcr_dbg(pcr, "Load efuse valid: 0x%x\n", efuse_valid);
393
394 if (efuse_valid == 0) {
22bf3251 395 retval = pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
c0e5f4e7
RF		 396 if (retval != 0)
397 pcr_dbg(pcr, "read 0x814 DW fail\n");
398 pcr_dbg(pcr, "DW from 0x814: 0x%x\n", lval);
399 /* 0x816 */
400 valid = (u8)((lval >> 16) & 0x03);
401 pcr_dbg(pcr, "0x816: %d\n", valid);
402 }
403 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
404 REG_EFUSE_POR, 0);
405 pcr_dbg(pcr, "Disable efuse por!\n");
406
22bf3251 407 pci_read_config_dword(pdev, PCR_SETTING_REG2, &lval);
c0e5f4e7 408 lval = lval & 0x00FFFFFF;
22bf3251 409 retval = pci_write_config_dword(pdev, PCR_SETTING_REG2, lval);
c0e5f4e7
RF		 410 if (retval != 0)
411 pcr_dbg(pcr, "write config fail\n");
412
413 return retval;
414}
415
416static void rts5261_init_from_cfg(struct rtsx_pcr *pcr)
417{
22bf3251 418 struct pci_dev *pdev = pcr->pci;
ed86a987 419 int l1ss;
c0e5f4e7
RF		 420 u32 lval;
421 struct rtsx_cr_option *option = &pcr->option;
422
ed86a987
BH		 423 l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
424 if (!l1ss)
425 return;
426
427 pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
c0e5f4e7 428
7a4462a9 429 if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
c0e5f4e7
RF		 430 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
431 else
432 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
433
7a4462a9 434 if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
c0e5f4e7
RF		 435 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
436 else
437 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
438
7a4462a9 439 if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
c0e5f4e7
RF		 440 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
441 else
442 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
443
7a4462a9 444 if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
c0e5f4e7
RF		 445 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
446 else
447 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
448
449 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
450 if (option->ltr_en) {
451 u16 val;
452
22bf3251 453 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val);
c0e5f4e7
RF		 454 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
455 option->ltr_enabled = true;
456 option->ltr_active = true;
457 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
458 } else {
459 option->ltr_enabled = false;
460 }
461 }
462
463 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
464 | PM_L1_1_EN | PM_L1_2_EN))
465 option->force_clkreq_0 = false;
466 else
467 option->force_clkreq_0 = true;
468}
469
470static int rts5261_extra_init_hw(struct rtsx_pcr *pcr)
471{
472 struct rtsx_cr_option *option = &pcr->option;
473
474 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG1,
475 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
476
477 rts5261_init_from_cfg(pcr);
478 rts5261_init_from_hw(pcr);
479
480 /* power off efuse */
481 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
482 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF);
483 rtsx_pci_write_register(pcr, L1SUB_CONFIG1,
484 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE);
485 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0);
486
487 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
488 RTS5261_AUX_CLK_16M_EN, 0);
489
490 /* Release PRSNT# */
491 rtsx_pci_write_register(pcr, RTS5261_AUTOLOAD_CFG4,
492 RTS5261_FORCE_PRSNT_LOW, 0);
493 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL,
494 FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG);
495
496 rtsx_pci_write_register(pcr, PCLK_CTL,
497 PCLK_MODE_SEL, PCLK_MODE_SEL);
498
499 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
500 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN);
501
502 /* LED shine disabled, set initial shine cycle period */
503 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02);
504
505 /* Configure driving */
506 rts5261_fill_driving(pcr, OUTPUT_3V3);
507
508 /*
509 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
510 * to drive low, and we forcibly request clock.
511 */
512 if (option->force_clkreq_0)
513 rtsx_pci_write_register(pcr, PETXCFG,
514 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
515 else
516 rtsx_pci_write_register(pcr, PETXCFG,
517 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
518
c28e3fb2 519 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB);
c0e5f4e7
RF		 520 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
521 rtsx_pci_write_register(pcr, RTS5261_REG_PME_FORCE_CTL,
522 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL);
523
524 /* Clear Enter RTD3_cold Information*/
525 rtsx_pci_write_register(pcr, RTS5261_FW_CTL,
526 RTS5261_INFORM_RTD3_COLD, 0);
527
528 return 0;
529}
530
531static void rts5261_enable_aspm(struct rtsx_pcr *pcr, bool enable)
532{
0a3bbf92
RF		 533 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
534 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
535
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RF		 536 if (pcr->aspm_enabled == enable)
537 return;
538
0a3bbf92
RF		 539 val |= (pcr->aspm_en & 0x02);
540 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
3d1e7aa8
BH		 541 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
542 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en);
c0e5f4e7 543 pcr->aspm_enabled = enable;
c0e5f4e7
RF		 544}
545
546static void rts5261_disable_aspm(struct rtsx_pcr *pcr, bool enable)
547{
0a3bbf92
RF		 548 u8 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
549 u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1;
550
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RF		 551 if (pcr->aspm_enabled == enable)
552 return;
553
3d1e7aa8
BH		 554 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
555 PCI_EXP_LNKCTL_ASPMC, 0);
0a3bbf92 556 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val);
c0e5f4e7
RF		 557 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
558 udelay(10);
559 pcr->aspm_enabled = enable;
560}
561
562static void rts5261_set_aspm(struct rtsx_pcr *pcr, bool enable)
563{
564 if (enable)
565 rts5261_enable_aspm(pcr, true);
566 else
567 rts5261_disable_aspm(pcr, false);
568}
569
570static void rts5261_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
571{
572 struct rtsx_cr_option *option = &pcr->option;
573 int aspm_L1_1, aspm_L1_2;
574 u8 val = 0;
575
576 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
577 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
578
579 if (active) {
580 /* run, latency: 60us */
581 if (aspm_L1_1)
582 val = option->ltr_l1off_snooze_sspwrgate;
583 } else {
584 /* l1off, latency: 300us */
585 if (aspm_L1_2)
586 val = option->ltr_l1off_sspwrgate;
587 }
588
589 rtsx_set_l1off_sub(pcr, val);
590}
591
592static const struct pcr_ops rts5261_pcr_ops = {
593 .fetch_vendor_settings = rtsx5261_fetch_vendor_settings,
594 .turn_on_led = rts5261_turn_on_led,
595 .turn_off_led = rts5261_turn_off_led,
596 .extra_init_hw = rts5261_extra_init_hw,
597 .enable_auto_blink = rts5261_enable_auto_blink,
598 .disable_auto_blink = rts5261_disable_auto_blink,
599 .card_power_on = rts5261_card_power_on,
600 .card_power_off = rts5261_card_power_off,
601 .switch_output_voltage = rts5261_switch_output_voltage,
602 .force_power_down = rts5261_force_power_down,
603 .stop_cmd = rts5261_stop_cmd,
604 .set_aspm = rts5261_set_aspm,
605 .set_l1off_cfg_sub_d0 = rts5261_set_l1off_cfg_sub_d0,
606 .enable_ocp = rts5261_enable_ocp,
607 .disable_ocp = rts5261_disable_ocp,
608 .init_ocp = rts5261_init_ocp,
609 .process_ocp = rts5261_process_ocp,
610 .clear_ocpstat = rts5261_clear_ocpstat,
611};
612
613static inline u8 double_ssc_depth(u8 depth)
614{
615 return ((depth > 1) ? (depth - 1) : depth);
616}
617
618int rts5261_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
619 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
620{
621 int err, clk;
4d616831
RF		 622 u16 n;
623 u8 clk_divider, mcu_cnt, div;
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RF		 624 static const u8 depth[] = {
625 [RTSX_SSC_DEPTH_4M] = RTS5261_SSC_DEPTH_4M,
626 [RTSX_SSC_DEPTH_2M] = RTS5261_SSC_DEPTH_2M,
627 [RTSX_SSC_DEPTH_1M] = RTS5261_SSC_DEPTH_1M,
628 [RTSX_SSC_DEPTH_500K] = RTS5261_SSC_DEPTH_512K,
629 };
630
631 if (initial_mode) {
632 /* We use 250k(around) here, in initial stage */
c18c1f10
RF		 633 if (is_version(pcr, PID_5261, IC_VER_D)) {
634 clk_divider = SD_CLK_DIVIDE_256;
635 card_clock = 60000000;
636 } else {
637 clk_divider = SD_CLK_DIVIDE_128;
638 card_clock = 30000000;
639 }
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RF		 640 } else {
641 clk_divider = SD_CLK_DIVIDE_0;
642 }
643 err = rtsx_pci_write_register(pcr, SD_CFG1,
644 SD_CLK_DIVIDE_MASK, clk_divider);
645 if (err < 0)
646 return err;
647
648 card_clock /= 1000000;
649 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
650
651 clk = card_clock;
652 if (!initial_mode && double_clk)
653 clk = card_clock * 2;
654 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
655 clk, pcr->cur_clock);
656
657 if (clk == pcr->cur_clock)
658 return 0;
659
660 if (pcr->ops->conv_clk_and_div_n)
4d616831 661 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
c0e5f4e7 662 else
4d616831 663 n = clk - 4;
c0e5f4e7
RF		 664 if ((clk <= 4) || (n > 396))
665 return -EINVAL;
666
4d616831 667 mcu_cnt = 125/clk + 3;
c0e5f4e7
RF		 668 if (mcu_cnt > 15)
669 mcu_cnt = 15;
670
671 div = CLK_DIV_1;
672 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) {
673 if (pcr->ops->conv_clk_and_div_n) {
674 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
675 DIV_N_TO_CLK) * 2;
4d616831 676 n = pcr->ops->conv_clk_and_div_n(dbl_clk,
c0e5f4e7
RF		 677 CLK_TO_DIV_N);
678 } else {
679 n = (n + 4) * 2 - 4;
680 }
681 div++;
682 }
683
684 n = (n / 2);
685 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
686
687 ssc_depth = depth[ssc_depth];
688 if (double_clk)
689 ssc_depth = double_ssc_depth(ssc_depth);
690
691 if (ssc_depth) {
692 if (div == CLK_DIV_2) {
693 if (ssc_depth > 1)
694 ssc_depth -= 1;
695 else
696 ssc_depth = RTS5261_SSC_DEPTH_8M;
697 } else if (div == CLK_DIV_4) {
698 if (ssc_depth > 2)
699 ssc_depth -= 2;
700 else
701 ssc_depth = RTS5261_SSC_DEPTH_8M;
702 } else if (div == CLK_DIV_8) {
703 if (ssc_depth > 3)
704 ssc_depth -= 3;
705 else
706 ssc_depth = RTS5261_SSC_DEPTH_8M;
707 }
708 } else {
709 ssc_depth = 0;
710 }
711 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
712
713 rtsx_pci_init_cmd(pcr);
714 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
715 CLK_LOW_FREQ, CLK_LOW_FREQ);
716 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
717 0xFF, (div << 4) | mcu_cnt);
718 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
719 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
720 SSC_DEPTH_MASK, ssc_depth);
721 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
722 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
723 if (vpclk) {
724 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
725 PHASE_NOT_RESET, 0);
726 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
727 PHASE_NOT_RESET, 0);
728 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
729 PHASE_NOT_RESET, PHASE_NOT_RESET);
730 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL,
731 PHASE_NOT_RESET, PHASE_NOT_RESET);
732 }
733
734 err = rtsx_pci_send_cmd(pcr, 2000);
735 if (err < 0)
736 return err;
737
738 /* Wait SSC clock stable */
739 udelay(SSC_CLOCK_STABLE_WAIT);
740 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
741 if (err < 0)
742 return err;
743
744 pcr->cur_clock = clk;
745 return 0;
746
747}
748
749void rts5261_init_params(struct rtsx_pcr *pcr)
750{
751 struct rtsx_cr_option *option = &pcr->option;
752 struct rtsx_hw_param *hw_param = &pcr->hw_param;
5afe8021 753 u8 val;
c0e5f4e7
RF		 754
755 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
5afe8021
RF		 756 rtsx_pci_read_register(pcr, RTS5261_FW_STATUS, &val);
757 if (!(val & RTS5261_EXPRESS_LINK_FAIL_MASK))
758 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
c0e5f4e7
RF		 759 pcr->num_slots = 1;
760 pcr->ops = &rts5261_pcr_ops;
761
762 pcr->flags = 0;
763 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
764 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
765 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
766 pcr->aspm_en = ASPM_L1_EN;
4686392c 767 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 11);
c0e5f4e7
RF		 768 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
769
770 pcr->ic_version = rts5261_get_ic_version(pcr);
771 pcr->sd_pull_ctl_enable_tbl = rts5261_sd_pull_ctl_enable_tbl;
772 pcr->sd_pull_ctl_disable_tbl = rts5261_sd_pull_ctl_disable_tbl;
773
774 pcr->reg_pm_ctrl3 = RTS5261_AUTOLOAD_CFG3;
775
776 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN
777 | LTR_L1SS_PWR_GATE_EN);
778 option->ltr_en = true;
779
780 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
781 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
782 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
783 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
784 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
785 option->ltr_l1off_sspwrgate = 0x7F;
786 option->ltr_l1off_snooze_sspwrgate = 0x78;
c0e5f4e7
RF		 787
788 option->ocp_en = 1;
789 hw_param->interrupt_en |= SD_OC_INT_EN;
790 hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
791 option->sd_800mA_ocp_thd = RTS5261_LDO1_OCP_THD_1040;
792}
Linux 6.x block layer and io_uring tree(s)