Commit | Line | Data |
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80503b23 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
4eb174be | 2 | /* |
6c536e4c MH |
3 | * ad525x_dpot: Driver for the Analog Devices digital potentiometers |
4 | * Copyright (c) 2009-2010 Analog Devices, Inc. | |
dbd71398 | 5 | * Author: Michael Hennerich <michael.hennerich@analog.com> |
4eb174be | 6 | * |
dcaf7689 | 7 | * DEVID #Wipers #Positions Resistor Options (kOhm) |
4eb174be MH |
8 | * AD5258 1 64 1, 10, 50, 100 |
9 | * AD5259 1 256 5, 10, 50, 100 | |
10 | * AD5251 2 64 1, 10, 50, 100 | |
11 | * AD5252 2 256 1, 10, 50, 100 | |
12 | * AD5255 3 512 25, 250 | |
13 | * AD5253 4 64 1, 10, 50, 100 | |
14 | * AD5254 4 256 1, 10, 50, 100 | |
6c536e4c MH |
15 | * AD5160 1 256 5, 10, 50, 100 |
16 | * AD5161 1 256 5, 10, 50, 100 | |
17 | * AD5162 2 256 2.5, 10, 50, 100 | |
18 | * AD5165 1 256 100 | |
19 | * AD5200 1 256 10, 50 | |
20 | * AD5201 1 33 10, 50 | |
21 | * AD5203 4 64 10, 100 | |
22 | * AD5204 4 256 10, 50, 100 | |
23 | * AD5206 6 256 10, 50, 100 | |
24 | * AD5207 2 256 10, 50, 100 | |
25 | * AD5231 1 1024 10, 50, 100 | |
26 | * AD5232 2 256 10, 50, 100 | |
27 | * AD5233 4 64 10, 50, 100 | |
28 | * AD5235 2 1024 25, 250 | |
29 | * AD5260 1 256 20, 50, 200 | |
30 | * AD5262 2 256 20, 50, 200 | |
31 | * AD5263 4 256 20, 50, 200 | |
32 | * AD5290 1 256 10, 50, 100 | |
a4bd3949 MH |
33 | * AD5291 1 256 20, 50, 100 (20-TP) |
34 | * AD5292 1 1024 20, 50, 100 (20-TP) | |
35 | * AD5293 1 1024 20, 50, 100 | |
6c536e4c MH |
36 | * AD7376 1 128 10, 50, 100, 1M |
37 | * AD8400 1 256 1, 10, 50, 100 | |
38 | * AD8402 2 256 1, 10, 50, 100 | |
39 | * AD8403 4 256 1, 10, 50, 100 | |
40 | * ADN2850 3 512 25, 250 | |
e3ae6847 MH |
41 | * AD5241 1 256 10, 100, 1M |
42 | * AD5246 1 128 5, 10, 50, 100 | |
43 | * AD5247 1 128 5, 10, 50, 100 | |
44 | * AD5245 1 256 5, 10, 50, 100 | |
45 | * AD5243 2 256 2.5, 10, 50, 100 | |
46 | * AD5248 2 256 2.5, 10, 50, 100 | |
47 | * AD5242 2 256 20, 50, 200 | |
c74cba61 MH |
48 | * AD5280 1 256 20, 50, 200 |
49 | * AD5282 2 256 20, 50, 200 | |
50 | * ADN2860 3 512 25, 250 | |
59592d0c MH |
51 | * AD5273 1 64 1, 10, 50, 100 (OTP) |
52 | * AD5171 1 64 5, 10, 50, 100 (OTP) | |
53 | * AD5170 1 256 2.5, 10, 50, 100 (OTP) | |
54 | * AD5172 2 256 2.5, 10, 50, 100 (OTP) | |
55 | * AD5173 2 256 2.5, 10, 50, 100 (OTP) | |
a4bd3949 MH |
56 | * AD5270 1 1024 20, 50, 100 (50-TP) |
57 | * AD5271 1 256 20, 50, 100 (50-TP) | |
58 | * AD5272 1 1024 20, 50, 100 (50-TP) | |
59 | * AD5274 1 256 20, 50, 100 (50-TP) | |
4eb174be | 60 | * |
8a05eb89 | 61 | * See Documentation/misc-devices/ad525x_dpot.rst for more info. |
4eb174be MH |
62 | * |
63 | * derived from ad5258.c | |
64 | * Copyright (c) 2009 Cyber Switching, Inc. | |
65 | * Author: Chris Verges <chrisv@cyberswitching.com> | |
66 | * | |
67 | * derived from ad5252.c | |
dbd71398 | 68 | * Copyright (c) 2006-2011 Michael Hennerich <michael.hennerich@analog.com> |
4eb174be MH |
69 | */ |
70 | ||
71 | #include <linux/module.h> | |
72 | #include <linux/device.h> | |
73 | #include <linux/kernel.h> | |
4eb174be | 74 | #include <linux/delay.h> |
6c536e4c | 75 | #include <linux/slab.h> |
4eb174be | 76 | |
6c536e4c | 77 | #include "ad525x_dpot.h" |
4eb174be MH |
78 | |
79 | /* | |
80 | * Client data (each client gets its own) | |
81 | */ | |
82 | ||
83 | struct dpot_data { | |
6c536e4c | 84 | struct ad_dpot_bus_data bdata; |
4eb174be | 85 | struct mutex update_lock; |
d06d101b DS |
86 | unsigned int rdac_mask; |
87 | unsigned int max_pos; | |
6c536e4c | 88 | unsigned long devid; |
d06d101b DS |
89 | unsigned int uid; |
90 | unsigned int feat; | |
91 | unsigned int wipers; | |
59592d0c MH |
92 | u16 rdac_cache[MAX_RDACS]; |
93 | DECLARE_BITMAP(otp_en_mask, MAX_RDACS); | |
4eb174be MH |
94 | }; |
95 | ||
6c536e4c MH |
96 | static inline int dpot_read_d8(struct dpot_data *dpot) |
97 | { | |
98 | return dpot->bdata.bops->read_d8(dpot->bdata.client); | |
99 | } | |
100 | ||
101 | static inline int dpot_read_r8d8(struct dpot_data *dpot, u8 reg) | |
102 | { | |
103 | return dpot->bdata.bops->read_r8d8(dpot->bdata.client, reg); | |
104 | } | |
105 | ||
106 | static inline int dpot_read_r8d16(struct dpot_data *dpot, u8 reg) | |
107 | { | |
108 | return dpot->bdata.bops->read_r8d16(dpot->bdata.client, reg); | |
109 | } | |
110 | ||
111 | static inline int dpot_write_d8(struct dpot_data *dpot, u8 val) | |
112 | { | |
113 | return dpot->bdata.bops->write_d8(dpot->bdata.client, val); | |
114 | } | |
115 | ||
116 | static inline int dpot_write_r8d8(struct dpot_data *dpot, u8 reg, u16 val) | |
117 | { | |
118 | return dpot->bdata.bops->write_r8d8(dpot->bdata.client, reg, val); | |
119 | } | |
120 | ||
121 | static inline int dpot_write_r8d16(struct dpot_data *dpot, u8 reg, u16 val) | |
122 | { | |
123 | return dpot->bdata.bops->write_r8d16(dpot->bdata.client, reg, val); | |
124 | } | |
125 | ||
e3ae6847 | 126 | static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg) |
6c536e4c | 127 | { |
d06d101b | 128 | unsigned int ctrl = 0; |
a4bd3949 | 129 | int value; |
6c536e4c | 130 | |
e3ae6847 | 131 | if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD))) { |
6c536e4c | 132 | |
e3ae6847 MH |
133 | if (dpot->feat & F_RDACS_WONLY) |
134 | return dpot->rdac_cache[reg & DPOT_RDAC_MASK]; | |
e3ae6847 MH |
135 | if (dpot->uid == DPOT_UID(AD5291_ID) || |
136 | dpot->uid == DPOT_UID(AD5292_ID) || | |
a4bd3949 MH |
137 | dpot->uid == DPOT_UID(AD5293_ID)) { |
138 | ||
139 | value = dpot_read_r8d8(dpot, | |
e3ae6847 | 140 | DPOT_AD5291_READ_RDAC << 2); |
6c536e4c | 141 | |
f8096ff3 DL |
142 | if (value < 0) |
143 | return value; | |
144 | ||
a4bd3949 MH |
145 | if (dpot->uid == DPOT_UID(AD5291_ID)) |
146 | value = value >> 2; | |
147 | ||
148 | return value; | |
149 | } else if (dpot->uid == DPOT_UID(AD5270_ID) || | |
150 | dpot->uid == DPOT_UID(AD5271_ID)) { | |
151 | ||
152 | value = dpot_read_r8d8(dpot, | |
153 | DPOT_AD5270_1_2_4_READ_RDAC << 2); | |
154 | ||
155 | if (value < 0) | |
156 | return value; | |
157 | ||
158 | if (dpot->uid == DPOT_UID(AD5271_ID)) | |
159 | value = value >> 2; | |
160 | ||
161 | return value; | |
162 | } | |
163 | ||
e3ae6847 MH |
164 | ctrl = DPOT_SPI_READ_RDAC; |
165 | } else if (reg & DPOT_ADDR_EEPROM) { | |
166 | ctrl = DPOT_SPI_READ_EEPROM; | |
167 | } | |
6c536e4c | 168 | |
e3ae6847 MH |
169 | if (dpot->feat & F_SPI_16BIT) |
170 | return dpot_read_r8d8(dpot, ctrl); | |
171 | else if (dpot->feat & F_SPI_24BIT) | |
172 | return dpot_read_r8d16(dpot, ctrl); | |
6c536e4c | 173 | |
e3ae6847 MH |
174 | return -EFAULT; |
175 | } | |
6c536e4c | 176 | |
e3ae6847 MH |
177 | static s32 dpot_read_i2c(struct dpot_data *dpot, u8 reg) |
178 | { | |
a4bd3949 | 179 | int value; |
d06d101b | 180 | unsigned int ctrl = 0; |
15584555 | 181 | |
e3ae6847 MH |
182 | switch (dpot->uid) { |
183 | case DPOT_UID(AD5246_ID): | |
184 | case DPOT_UID(AD5247_ID): | |
185 | return dpot_read_d8(dpot); | |
186 | case DPOT_UID(AD5245_ID): | |
187 | case DPOT_UID(AD5241_ID): | |
188 | case DPOT_UID(AD5242_ID): | |
189 | case DPOT_UID(AD5243_ID): | |
190 | case DPOT_UID(AD5248_ID): | |
c74cba61 MH |
191 | case DPOT_UID(AD5280_ID): |
192 | case DPOT_UID(AD5282_ID): | |
e3ae6847 | 193 | ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? |
5f400cf4 | 194 | 0 : DPOT_AD5282_RDAC_AB; |
e3ae6847 | 195 | return dpot_read_r8d8(dpot, ctrl); |
59592d0c MH |
196 | case DPOT_UID(AD5170_ID): |
197 | case DPOT_UID(AD5171_ID): | |
198 | case DPOT_UID(AD5273_ID): | |
199 | return dpot_read_d8(dpot); | |
200 | case DPOT_UID(AD5172_ID): | |
201 | case DPOT_UID(AD5173_ID): | |
202 | ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? | |
5f400cf4 | 203 | 0 : DPOT_AD5172_3_A0; |
59592d0c | 204 | return dpot_read_r8d8(dpot, ctrl); |
a4bd3949 MH |
205 | case DPOT_UID(AD5272_ID): |
206 | case DPOT_UID(AD5274_ID): | |
068ad41e | 207 | dpot_write_r8d8(dpot, |
a4bd3949 MH |
208 | (DPOT_AD5270_1_2_4_READ_RDAC << 2), 0); |
209 | ||
068ad41e CIK |
210 | value = dpot_read_r8d16(dpot, DPOT_AD5270_1_2_4_RDAC << 2); |
211 | if (value < 0) | |
212 | return value; | |
213 | /* | |
214 | * AD5272/AD5274 returns high byte first, however | |
215 | * underling smbus expects low byte first. | |
216 | */ | |
217 | value = swab16(value); | |
218 | ||
219 | if (dpot->uid == DPOT_UID(AD5274_ID)) | |
220 | value = value >> 2; | |
a4bd3949 | 221 | return value; |
e3ae6847 | 222 | default: |
6c536e4c MH |
223 | if ((reg & DPOT_REG_TOL) || (dpot->max_pos > 256)) |
224 | return dpot_read_r8d16(dpot, (reg & 0xF8) | | |
225 | ((reg & 0x7) << 1)); | |
226 | else | |
227 | return dpot_read_r8d8(dpot, reg); | |
6c536e4c | 228 | } |
6c536e4c MH |
229 | } |
230 | ||
e3ae6847 MH |
231 | static s32 dpot_read(struct dpot_data *dpot, u8 reg) |
232 | { | |
233 | if (dpot->feat & F_SPI) | |
234 | return dpot_read_spi(dpot, reg); | |
235 | else | |
236 | return dpot_read_i2c(dpot, reg); | |
237 | } | |
238 | ||
239 | static s32 dpot_write_spi(struct dpot_data *dpot, u8 reg, u16 value) | |
6c536e4c | 240 | { |
d06d101b | 241 | unsigned int val = 0; |
6c536e4c | 242 | |
a4bd3949 | 243 | if (!(reg & (DPOT_ADDR_EEPROM | DPOT_ADDR_CMD | DPOT_ADDR_OTP))) { |
e3ae6847 MH |
244 | if (dpot->feat & F_RDACS_WONLY) |
245 | dpot->rdac_cache[reg & DPOT_RDAC_MASK] = value; | |
246 | ||
247 | if (dpot->feat & F_AD_APPDATA) { | |
248 | if (dpot->feat & F_SPI_8BIT) { | |
249 | val = ((reg & DPOT_RDAC_MASK) << | |
250 | DPOT_MAX_POS(dpot->devid)) | | |
251 | value; | |
252 | return dpot_write_d8(dpot, val); | |
253 | } else if (dpot->feat & F_SPI_16BIT) { | |
254 | val = ((reg & DPOT_RDAC_MASK) << | |
255 | DPOT_MAX_POS(dpot->devid)) | | |
256 | value; | |
257 | return dpot_write_r8d8(dpot, val >> 8, | |
258 | val & 0xFF); | |
259 | } else | |
260 | BUG(); | |
261 | } else { | |
262 | if (dpot->uid == DPOT_UID(AD5291_ID) || | |
263 | dpot->uid == DPOT_UID(AD5292_ID) || | |
a4bd3949 MH |
264 | dpot->uid == DPOT_UID(AD5293_ID)) { |
265 | ||
266 | dpot_write_r8d8(dpot, DPOT_AD5291_CTRLREG << 2, | |
267 | DPOT_AD5291_UNLOCK_CMD); | |
268 | ||
269 | if (dpot->uid == DPOT_UID(AD5291_ID)) | |
270 | value = value << 2; | |
271 | ||
e3ae6847 MH |
272 | return dpot_write_r8d8(dpot, |
273 | (DPOT_AD5291_RDAC << 2) | | |
274 | (value >> 8), value & 0xFF); | |
a4bd3949 MH |
275 | } else if (dpot->uid == DPOT_UID(AD5270_ID) || |
276 | dpot->uid == DPOT_UID(AD5271_ID)) { | |
277 | dpot_write_r8d8(dpot, | |
278 | DPOT_AD5270_1_2_4_CTRLREG << 2, | |
279 | DPOT_AD5270_1_2_4_UNLOCK_CMD); | |
280 | ||
281 | if (dpot->uid == DPOT_UID(AD5271_ID)) | |
282 | value = value << 2; | |
6c536e4c | 283 | |
a4bd3949 MH |
284 | return dpot_write_r8d8(dpot, |
285 | (DPOT_AD5270_1_2_4_RDAC << 2) | | |
286 | (value >> 8), value & 0xFF); | |
287 | } | |
e3ae6847 MH |
288 | val = DPOT_SPI_RDAC | (reg & DPOT_RDAC_MASK); |
289 | } | |
290 | } else if (reg & DPOT_ADDR_EEPROM) { | |
291 | val = DPOT_SPI_EEPROM | (reg & DPOT_RDAC_MASK); | |
292 | } else if (reg & DPOT_ADDR_CMD) { | |
293 | switch (reg) { | |
294 | case DPOT_DEC_ALL_6DB: | |
295 | val = DPOT_SPI_DEC_ALL_6DB; | |
296 | break; | |
297 | case DPOT_INC_ALL_6DB: | |
298 | val = DPOT_SPI_INC_ALL_6DB; | |
299 | break; | |
300 | case DPOT_DEC_ALL: | |
301 | val = DPOT_SPI_DEC_ALL; | |
302 | break; | |
303 | case DPOT_INC_ALL: | |
304 | val = DPOT_SPI_INC_ALL; | |
305 | break; | |
306 | } | |
a4bd3949 MH |
307 | } else if (reg & DPOT_ADDR_OTP) { |
308 | if (dpot->uid == DPOT_UID(AD5291_ID) || | |
309 | dpot->uid == DPOT_UID(AD5292_ID)) { | |
310 | return dpot_write_r8d8(dpot, | |
311 | DPOT_AD5291_STORE_XTPM << 2, 0); | |
312 | } else if (dpot->uid == DPOT_UID(AD5270_ID) || | |
313 | dpot->uid == DPOT_UID(AD5271_ID)) { | |
314 | return dpot_write_r8d8(dpot, | |
315 | DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0); | |
316 | } | |
e3ae6847 MH |
317 | } else |
318 | BUG(); | |
319 | ||
320 | if (dpot->feat & F_SPI_16BIT) | |
321 | return dpot_write_r8d8(dpot, val, value); | |
322 | else if (dpot->feat & F_SPI_24BIT) | |
323 | return dpot_write_r8d16(dpot, val, value); | |
6c536e4c MH |
324 | |
325 | return -EFAULT; | |
326 | } | |
327 | ||
e3ae6847 MH |
328 | static s32 dpot_write_i2c(struct dpot_data *dpot, u8 reg, u16 value) |
329 | { | |
330 | /* Only write the instruction byte for certain commands */ | |
d06d101b | 331 | unsigned int tmp = 0, ctrl = 0; |
e3ae6847 MH |
332 | |
333 | switch (dpot->uid) { | |
334 | case DPOT_UID(AD5246_ID): | |
335 | case DPOT_UID(AD5247_ID): | |
336 | return dpot_write_d8(dpot, value); | |
e3ae6847 MH |
337 | |
338 | case DPOT_UID(AD5245_ID): | |
339 | case DPOT_UID(AD5241_ID): | |
340 | case DPOT_UID(AD5242_ID): | |
341 | case DPOT_UID(AD5243_ID): | |
342 | case DPOT_UID(AD5248_ID): | |
c74cba61 MH |
343 | case DPOT_UID(AD5280_ID): |
344 | case DPOT_UID(AD5282_ID): | |
345 | ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? | |
5f400cf4 | 346 | 0 : DPOT_AD5282_RDAC_AB; |
e3ae6847 | 347 | return dpot_write_r8d8(dpot, ctrl, value); |
59592d0c MH |
348 | case DPOT_UID(AD5171_ID): |
349 | case DPOT_UID(AD5273_ID): | |
350 | if (reg & DPOT_ADDR_OTP) { | |
351 | tmp = dpot_read_d8(dpot); | |
352 | if (tmp >> 6) /* Ready to Program? */ | |
353 | return -EFAULT; | |
354 | ctrl = DPOT_AD5273_FUSE; | |
355 | } | |
356 | return dpot_write_r8d8(dpot, ctrl, value); | |
59592d0c MH |
357 | case DPOT_UID(AD5172_ID): |
358 | case DPOT_UID(AD5173_ID): | |
359 | ctrl = ((reg & DPOT_RDAC_MASK) == DPOT_RDAC0) ? | |
5f400cf4 | 360 | 0 : DPOT_AD5172_3_A0; |
59592d0c MH |
361 | if (reg & DPOT_ADDR_OTP) { |
362 | tmp = dpot_read_r8d16(dpot, ctrl); | |
363 | if (tmp >> 14) /* Ready to Program? */ | |
364 | return -EFAULT; | |
5f400cf4 | 365 | ctrl |= DPOT_AD5170_2_3_FUSE; |
59592d0c MH |
366 | } |
367 | return dpot_write_r8d8(dpot, ctrl, value); | |
59592d0c MH |
368 | case DPOT_UID(AD5170_ID): |
369 | if (reg & DPOT_ADDR_OTP) { | |
370 | tmp = dpot_read_r8d16(dpot, tmp); | |
371 | if (tmp >> 14) /* Ready to Program? */ | |
372 | return -EFAULT; | |
a4bd3949 | 373 | ctrl = DPOT_AD5170_2_3_FUSE; |
59592d0c MH |
374 | } |
375 | return dpot_write_r8d8(dpot, ctrl, value); | |
a4bd3949 MH |
376 | case DPOT_UID(AD5272_ID): |
377 | case DPOT_UID(AD5274_ID): | |
378 | dpot_write_r8d8(dpot, DPOT_AD5270_1_2_4_CTRLREG << 2, | |
379 | DPOT_AD5270_1_2_4_UNLOCK_CMD); | |
380 | ||
381 | if (reg & DPOT_ADDR_OTP) | |
382 | return dpot_write_r8d8(dpot, | |
383 | DPOT_AD5270_1_2_4_STORE_XTPM << 2, 0); | |
384 | ||
385 | if (dpot->uid == DPOT_UID(AD5274_ID)) | |
386 | value = value << 2; | |
387 | ||
388 | return dpot_write_r8d8(dpot, (DPOT_AD5270_1_2_4_RDAC << 2) | | |
389 | (value >> 8), value & 0xFF); | |
e3ae6847 | 390 | default: |
c74cba61 MH |
391 | if (reg & DPOT_ADDR_CMD) |
392 | return dpot_write_d8(dpot, reg); | |
e3ae6847 | 393 | |
c74cba61 MH |
394 | if (dpot->max_pos > 256) |
395 | return dpot_write_r8d16(dpot, (reg & 0xF8) | | |
396 | ((reg & 0x7) << 1), value); | |
397 | else | |
398 | /* All other registers require instruction + data bytes */ | |
399 | return dpot_write_r8d8(dpot, reg, value); | |
e3ae6847 MH |
400 | } |
401 | } | |
402 | ||
e3ae6847 MH |
403 | static s32 dpot_write(struct dpot_data *dpot, u8 reg, u16 value) |
404 | { | |
405 | if (dpot->feat & F_SPI) | |
406 | return dpot_write_spi(dpot, reg, value); | |
407 | else | |
408 | return dpot_write_i2c(dpot, reg, value); | |
409 | } | |
410 | ||
4eb174be MH |
411 | /* sysfs functions */ |
412 | ||
413 | static ssize_t sysfs_show_reg(struct device *dev, | |
6c536e4c MH |
414 | struct device_attribute *attr, |
415 | char *buf, u32 reg) | |
4eb174be | 416 | { |
6c536e4c | 417 | struct dpot_data *data = dev_get_drvdata(dev); |
4eb174be MH |
418 | s32 value; |
419 | ||
59592d0c MH |
420 | if (reg & DPOT_ADDR_OTP_EN) |
421 | return sprintf(buf, "%s\n", | |
422 | test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask) ? | |
423 | "enabled" : "disabled"); | |
424 | ||
425 | ||
4eb174be | 426 | mutex_lock(&data->update_lock); |
6c536e4c | 427 | value = dpot_read(data, reg); |
4eb174be MH |
428 | mutex_unlock(&data->update_lock); |
429 | ||
430 | if (value < 0) | |
431 | return -EINVAL; | |
432 | /* | |
433 | * Let someone else deal with converting this ... | |
434 | * the tolerance is a two-byte value where the MSB | |
435 | * is a sign + integer value, and the LSB is a | |
436 | * decimal value. See page 18 of the AD5258 | |
437 | * datasheet (Rev. A) for more details. | |
438 | */ | |
439 | ||
6c536e4c | 440 | if (reg & DPOT_REG_TOL) |
4eb174be MH |
441 | return sprintf(buf, "0x%04x\n", value & 0xFFFF); |
442 | else | |
443 | return sprintf(buf, "%u\n", value & data->rdac_mask); | |
444 | } | |
445 | ||
446 | static ssize_t sysfs_set_reg(struct device *dev, | |
447 | struct device_attribute *attr, | |
448 | const char *buf, size_t count, u32 reg) | |
449 | { | |
6c536e4c | 450 | struct dpot_data *data = dev_get_drvdata(dev); |
4eb174be MH |
451 | unsigned long value; |
452 | int err; | |
453 | ||
59592d0c | 454 | if (reg & DPOT_ADDR_OTP_EN) { |
1bb850a1 | 455 | if (sysfs_streq(buf, "enabled")) |
59592d0c MH |
456 | set_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask); |
457 | else | |
458 | clear_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask); | |
459 | ||
460 | return count; | |
461 | } | |
462 | ||
463 | if ((reg & DPOT_ADDR_OTP) && | |
464 | !test_bit(DPOT_RDAC_MASK & reg, data->otp_en_mask)) | |
465 | return -EPERM; | |
466 | ||
f7b41276 | 467 | err = kstrtoul(buf, 10, &value); |
4eb174be MH |
468 | if (err) |
469 | return err; | |
470 | ||
471 | if (value > data->rdac_mask) | |
472 | value = data->rdac_mask; | |
473 | ||
474 | mutex_lock(&data->update_lock); | |
6c536e4c MH |
475 | dpot_write(data, reg, value); |
476 | if (reg & DPOT_ADDR_EEPROM) | |
4eb174be | 477 | msleep(26); /* Sleep while the EEPROM updates */ |
59592d0c MH |
478 | else if (reg & DPOT_ADDR_OTP) |
479 | msleep(400); /* Sleep while the OTP updates */ | |
4eb174be MH |
480 | mutex_unlock(&data->update_lock); |
481 | ||
482 | return count; | |
483 | } | |
484 | ||
485 | static ssize_t sysfs_do_cmd(struct device *dev, | |
486 | struct device_attribute *attr, | |
487 | const char *buf, size_t count, u32 reg) | |
488 | { | |
6c536e4c | 489 | struct dpot_data *data = dev_get_drvdata(dev); |
4eb174be MH |
490 | |
491 | mutex_lock(&data->update_lock); | |
6c536e4c | 492 | dpot_write(data, reg, 0); |
4eb174be MH |
493 | mutex_unlock(&data->update_lock); |
494 | ||
495 | return count; | |
496 | } | |
497 | ||
498 | /* ------------------------------------------------------------------------- */ | |
499 | ||
0993dbed MH |
500 | #define DPOT_DEVICE_SHOW(_name, _reg) static ssize_t \ |
501 | show_##_name(struct device *dev, \ | |
502 | struct device_attribute *attr, char *buf) \ | |
503 | { \ | |
504 | return sysfs_show_reg(dev, attr, buf, _reg); \ | |
4eb174be MH |
505 | } |
506 | ||
0993dbed MH |
507 | #define DPOT_DEVICE_SET(_name, _reg) static ssize_t \ |
508 | set_##_name(struct device *dev, \ | |
509 | struct device_attribute *attr, \ | |
510 | const char *buf, size_t count) \ | |
511 | { \ | |
512 | return sysfs_set_reg(dev, attr, buf, count, _reg); \ | |
4eb174be MH |
513 | } |
514 | ||
0993dbed MH |
515 | #define DPOT_DEVICE_SHOW_SET(name, reg) \ |
516 | DPOT_DEVICE_SHOW(name, reg) \ | |
517 | DPOT_DEVICE_SET(name, reg) \ | |
12eaa7a1 | 518 | static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, set_##name) |
4eb174be | 519 | |
0993dbed MH |
520 | #define DPOT_DEVICE_SHOW_ONLY(name, reg) \ |
521 | DPOT_DEVICE_SHOW(name, reg) \ | |
12eaa7a1 | 522 | static DEVICE_ATTR(name, S_IWUSR | S_IRUGO, show_##name, NULL) |
4eb174be | 523 | |
6c536e4c MH |
524 | DPOT_DEVICE_SHOW_SET(rdac0, DPOT_ADDR_RDAC | DPOT_RDAC0); |
525 | DPOT_DEVICE_SHOW_SET(eeprom0, DPOT_ADDR_EEPROM | DPOT_RDAC0); | |
526 | DPOT_DEVICE_SHOW_ONLY(tolerance0, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC0); | |
59592d0c MH |
527 | DPOT_DEVICE_SHOW_SET(otp0, DPOT_ADDR_OTP | DPOT_RDAC0); |
528 | DPOT_DEVICE_SHOW_SET(otp0en, DPOT_ADDR_OTP_EN | DPOT_RDAC0); | |
6c536e4c MH |
529 | |
530 | DPOT_DEVICE_SHOW_SET(rdac1, DPOT_ADDR_RDAC | DPOT_RDAC1); | |
531 | DPOT_DEVICE_SHOW_SET(eeprom1, DPOT_ADDR_EEPROM | DPOT_RDAC1); | |
532 | DPOT_DEVICE_SHOW_ONLY(tolerance1, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC1); | |
59592d0c MH |
533 | DPOT_DEVICE_SHOW_SET(otp1, DPOT_ADDR_OTP | DPOT_RDAC1); |
534 | DPOT_DEVICE_SHOW_SET(otp1en, DPOT_ADDR_OTP_EN | DPOT_RDAC1); | |
6c536e4c MH |
535 | |
536 | DPOT_DEVICE_SHOW_SET(rdac2, DPOT_ADDR_RDAC | DPOT_RDAC2); | |
537 | DPOT_DEVICE_SHOW_SET(eeprom2, DPOT_ADDR_EEPROM | DPOT_RDAC2); | |
538 | DPOT_DEVICE_SHOW_ONLY(tolerance2, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC2); | |
59592d0c MH |
539 | DPOT_DEVICE_SHOW_SET(otp2, DPOT_ADDR_OTP | DPOT_RDAC2); |
540 | DPOT_DEVICE_SHOW_SET(otp2en, DPOT_ADDR_OTP_EN | DPOT_RDAC2); | |
6c536e4c MH |
541 | |
542 | DPOT_DEVICE_SHOW_SET(rdac3, DPOT_ADDR_RDAC | DPOT_RDAC3); | |
543 | DPOT_DEVICE_SHOW_SET(eeprom3, DPOT_ADDR_EEPROM | DPOT_RDAC3); | |
544 | DPOT_DEVICE_SHOW_ONLY(tolerance3, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC3); | |
59592d0c MH |
545 | DPOT_DEVICE_SHOW_SET(otp3, DPOT_ADDR_OTP | DPOT_RDAC3); |
546 | DPOT_DEVICE_SHOW_SET(otp3en, DPOT_ADDR_OTP_EN | DPOT_RDAC3); | |
6c536e4c MH |
547 | |
548 | DPOT_DEVICE_SHOW_SET(rdac4, DPOT_ADDR_RDAC | DPOT_RDAC4); | |
549 | DPOT_DEVICE_SHOW_SET(eeprom4, DPOT_ADDR_EEPROM | DPOT_RDAC4); | |
550 | DPOT_DEVICE_SHOW_ONLY(tolerance4, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC4); | |
59592d0c MH |
551 | DPOT_DEVICE_SHOW_SET(otp4, DPOT_ADDR_OTP | DPOT_RDAC4); |
552 | DPOT_DEVICE_SHOW_SET(otp4en, DPOT_ADDR_OTP_EN | DPOT_RDAC4); | |
6c536e4c MH |
553 | |
554 | DPOT_DEVICE_SHOW_SET(rdac5, DPOT_ADDR_RDAC | DPOT_RDAC5); | |
555 | DPOT_DEVICE_SHOW_SET(eeprom5, DPOT_ADDR_EEPROM | DPOT_RDAC5); | |
556 | DPOT_DEVICE_SHOW_ONLY(tolerance5, DPOT_ADDR_EEPROM | DPOT_TOL_RDAC5); | |
59592d0c MH |
557 | DPOT_DEVICE_SHOW_SET(otp5, DPOT_ADDR_OTP | DPOT_RDAC5); |
558 | DPOT_DEVICE_SHOW_SET(otp5en, DPOT_ADDR_OTP_EN | DPOT_RDAC5); | |
6c536e4c MH |
559 | |
560 | static const struct attribute *dpot_attrib_wipers[] = { | |
561 | &dev_attr_rdac0.attr, | |
562 | &dev_attr_rdac1.attr, | |
563 | &dev_attr_rdac2.attr, | |
564 | &dev_attr_rdac3.attr, | |
565 | &dev_attr_rdac4.attr, | |
566 | &dev_attr_rdac5.attr, | |
567 | NULL | |
568 | }; | |
569 | ||
570 | static const struct attribute *dpot_attrib_eeprom[] = { | |
571 | &dev_attr_eeprom0.attr, | |
572 | &dev_attr_eeprom1.attr, | |
573 | &dev_attr_eeprom2.attr, | |
574 | &dev_attr_eeprom3.attr, | |
575 | &dev_attr_eeprom4.attr, | |
576 | &dev_attr_eeprom5.attr, | |
577 | NULL | |
4eb174be MH |
578 | }; |
579 | ||
59592d0c MH |
580 | static const struct attribute *dpot_attrib_otp[] = { |
581 | &dev_attr_otp0.attr, | |
582 | &dev_attr_otp1.attr, | |
583 | &dev_attr_otp2.attr, | |
584 | &dev_attr_otp3.attr, | |
585 | &dev_attr_otp4.attr, | |
586 | &dev_attr_otp5.attr, | |
587 | NULL | |
588 | }; | |
589 | ||
590 | static const struct attribute *dpot_attrib_otp_en[] = { | |
591 | &dev_attr_otp0en.attr, | |
592 | &dev_attr_otp1en.attr, | |
593 | &dev_attr_otp2en.attr, | |
594 | &dev_attr_otp3en.attr, | |
595 | &dev_attr_otp4en.attr, | |
596 | &dev_attr_otp5en.attr, | |
597 | NULL | |
598 | }; | |
599 | ||
6c536e4c MH |
600 | static const struct attribute *dpot_attrib_tolerance[] = { |
601 | &dev_attr_tolerance0.attr, | |
602 | &dev_attr_tolerance1.attr, | |
603 | &dev_attr_tolerance2.attr, | |
604 | &dev_attr_tolerance3.attr, | |
605 | &dev_attr_tolerance4.attr, | |
606 | &dev_attr_tolerance5.attr, | |
607 | NULL | |
4eb174be MH |
608 | }; |
609 | ||
610 | /* ------------------------------------------------------------------------- */ | |
611 | ||
0993dbed MH |
612 | #define DPOT_DEVICE_DO_CMD(_name, _cmd) static ssize_t \ |
613 | set_##_name(struct device *dev, \ | |
614 | struct device_attribute *attr, \ | |
615 | const char *buf, size_t count) \ | |
616 | { \ | |
617 | return sysfs_do_cmd(dev, attr, buf, count, _cmd); \ | |
618 | } \ | |
12eaa7a1 | 619 | static DEVICE_ATTR(_name, S_IWUSR | S_IRUGO, NULL, set_##_name) |
0993dbed | 620 | |
6c536e4c MH |
621 | DPOT_DEVICE_DO_CMD(inc_all, DPOT_INC_ALL); |
622 | DPOT_DEVICE_DO_CMD(dec_all, DPOT_DEC_ALL); | |
623 | DPOT_DEVICE_DO_CMD(inc_all_6db, DPOT_INC_ALL_6DB); | |
624 | DPOT_DEVICE_DO_CMD(dec_all_6db, DPOT_DEC_ALL_6DB); | |
4eb174be MH |
625 | |
626 | static struct attribute *ad525x_attributes_commands[] = { | |
627 | &dev_attr_inc_all.attr, | |
628 | &dev_attr_dec_all.attr, | |
629 | &dev_attr_inc_all_6db.attr, | |
630 | &dev_attr_dec_all_6db.attr, | |
631 | NULL | |
632 | }; | |
633 | ||
634 | static const struct attribute_group ad525x_group_commands = { | |
635 | .attrs = ad525x_attributes_commands, | |
636 | }; | |
637 | ||
1bdd2c45 | 638 | static int ad_dpot_add_files(struct device *dev, |
d06d101b | 639 | unsigned int features, unsigned int rdac) |
4eb174be | 640 | { |
6c536e4c MH |
641 | int err = sysfs_create_file(&dev->kobj, |
642 | dpot_attrib_wipers[rdac]); | |
643 | if (features & F_CMD_EEP) | |
644 | err |= sysfs_create_file(&dev->kobj, | |
645 | dpot_attrib_eeprom[rdac]); | |
646 | if (features & F_CMD_TOL) | |
647 | err |= sysfs_create_file(&dev->kobj, | |
648 | dpot_attrib_tolerance[rdac]); | |
59592d0c MH |
649 | if (features & F_CMD_OTP) { |
650 | err |= sysfs_create_file(&dev->kobj, | |
651 | dpot_attrib_otp_en[rdac]); | |
652 | err |= sysfs_create_file(&dev->kobj, | |
653 | dpot_attrib_otp[rdac]); | |
654 | } | |
4eb174be | 655 | |
6c536e4c MH |
656 | if (err) |
657 | dev_err(dev, "failed to register sysfs hooks for RDAC%d\n", | |
658 | rdac); | |
659 | ||
660 | return err; | |
4eb174be MH |
661 | } |
662 | ||
1bdd2c45 | 663 | static inline void ad_dpot_remove_files(struct device *dev, |
d06d101b | 664 | unsigned int features, unsigned int rdac) |
4eb174be | 665 | { |
6c536e4c MH |
666 | sysfs_remove_file(&dev->kobj, |
667 | dpot_attrib_wipers[rdac]); | |
668 | if (features & F_CMD_EEP) | |
669 | sysfs_remove_file(&dev->kobj, | |
670 | dpot_attrib_eeprom[rdac]); | |
671 | if (features & F_CMD_TOL) | |
672 | sysfs_remove_file(&dev->kobj, | |
673 | dpot_attrib_tolerance[rdac]); | |
59592d0c MH |
674 | if (features & F_CMD_OTP) { |
675 | sysfs_remove_file(&dev->kobj, | |
676 | dpot_attrib_otp_en[rdac]); | |
677 | sysfs_remove_file(&dev->kobj, | |
678 | dpot_attrib_otp[rdac]); | |
679 | } | |
4eb174be MH |
680 | } |
681 | ||
80c8ae28 | 682 | int ad_dpot_probe(struct device *dev, |
7f3379de MH |
683 | struct ad_dpot_bus_data *bdata, unsigned long devid, |
684 | const char *name) | |
4eb174be | 685 | { |
4eb174be | 686 | |
6c536e4c MH |
687 | struct dpot_data *data; |
688 | int i, err = 0; | |
4eb174be MH |
689 | |
690 | data = kzalloc(sizeof(struct dpot_data), GFP_KERNEL); | |
691 | if (!data) { | |
692 | err = -ENOMEM; | |
693 | goto exit; | |
694 | } | |
695 | ||
6c536e4c | 696 | dev_set_drvdata(dev, data); |
4eb174be MH |
697 | mutex_init(&data->update_lock); |
698 | ||
6c536e4c | 699 | data->bdata = *bdata; |
7f3379de | 700 | data->devid = devid; |
6c536e4c | 701 | |
7f3379de | 702 | data->max_pos = 1 << DPOT_MAX_POS(devid); |
6c536e4c | 703 | data->rdac_mask = data->max_pos - 1; |
7f3379de MH |
704 | data->feat = DPOT_FEAT(devid); |
705 | data->uid = DPOT_UID(devid); | |
706 | data->wipers = DPOT_WIPERS(devid); | |
6c536e4c | 707 | |
59592d0c | 708 | for (i = DPOT_RDAC0; i < MAX_RDACS; i++) |
6c536e4c MH |
709 | if (data->wipers & (1 << i)) { |
710 | err = ad_dpot_add_files(dev, data->feat, i); | |
711 | if (err) | |
712 | goto exit_remove_files; | |
713 | /* power-up midscale */ | |
714 | if (data->feat & F_RDACS_WONLY) | |
715 | data->rdac_cache[i] = data->max_pos / 2; | |
716 | } | |
717 | ||
718 | if (data->feat & F_CMD_INC) | |
719 | err = sysfs_create_group(&dev->kobj, &ad525x_group_commands); | |
4eb174be MH |
720 | |
721 | if (err) { | |
722 | dev_err(dev, "failed to register sysfs hooks\n"); | |
723 | goto exit_free; | |
724 | } | |
725 | ||
4eb174be | 726 | dev_info(dev, "%s %d-Position Digital Potentiometer registered\n", |
7f3379de | 727 | name, data->max_pos); |
4eb174be MH |
728 | |
729 | return 0; | |
730 | ||
6c536e4c | 731 | exit_remove_files: |
59592d0c | 732 | for (i = DPOT_RDAC0; i < MAX_RDACS; i++) |
6c536e4c MH |
733 | if (data->wipers & (1 << i)) |
734 | ad_dpot_remove_files(dev, data->feat, i); | |
735 | ||
4eb174be MH |
736 | exit_free: |
737 | kfree(data); | |
6c536e4c | 738 | dev_set_drvdata(dev, NULL); |
4eb174be | 739 | exit: |
6c536e4c | 740 | dev_err(dev, "failed to create client for %s ID 0x%lX\n", |
7f3379de | 741 | name, devid); |
4eb174be MH |
742 | return err; |
743 | } | |
6c536e4c | 744 | EXPORT_SYMBOL(ad_dpot_probe); |
4eb174be | 745 | |
85385a51 | 746 | void ad_dpot_remove(struct device *dev) |
4eb174be | 747 | { |
6c536e4c MH |
748 | struct dpot_data *data = dev_get_drvdata(dev); |
749 | int i; | |
750 | ||
59592d0c | 751 | for (i = DPOT_RDAC0; i < MAX_RDACS; i++) |
6c536e4c MH |
752 | if (data->wipers & (1 << i)) |
753 | ad_dpot_remove_files(dev, data->feat, i); | |
4eb174be | 754 | |
4eb174be | 755 | kfree(data); |
4eb174be | 756 | } |
6c536e4c | 757 | EXPORT_SYMBOL(ad_dpot_remove); |
4eb174be | 758 | |
4eb174be MH |
759 | |
760 | MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>, " | |
dbd71398 | 761 | "Michael Hennerich <michael.hennerich@analog.com>"); |
6c536e4c | 762 | MODULE_DESCRIPTION("Digital potentiometer driver"); |
4eb174be | 763 | MODULE_LICENSE("GPL"); |