[linux-block.git] / drivers / mfd / wm831x-irq.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm831x-irq.c  --  Interrupt controller support for Wolfson WM831x PMICs
 *
 * Copyright 2009 Wolfson Microelectronics PLC.
 *
 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>

#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm831x/irq.h>

#include <linux/delay.h>

struct wm831x_irq_data {
	int primary;
	int reg;
	int mask;
};

static struct wm831x_irq_data wm831x_irqs[] = {
	[WM831X_IRQ_TEMP_THW] = {
		.primary = WM831X_TEMP_INT,
		.reg = 1,
		.mask = WM831X_TEMP_THW_EINT,
	},
	[WM831X_IRQ_GPIO_1] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP1_EINT,
	},
	[WM831X_IRQ_GPIO_2] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP2_EINT,
	},
	[WM831X_IRQ_GPIO_3] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP3_EINT,
	},
	[WM831X_IRQ_GPIO_4] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP4_EINT,
	},
	[WM831X_IRQ_GPIO_5] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP5_EINT,
	},
	[WM831X_IRQ_GPIO_6] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP6_EINT,
	},
	[WM831X_IRQ_GPIO_7] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP7_EINT,
	},
	[WM831X_IRQ_GPIO_8] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP8_EINT,
	},
	[WM831X_IRQ_GPIO_9] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP9_EINT,
	},
	[WM831X_IRQ_GPIO_10] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP10_EINT,
	},
	[WM831X_IRQ_GPIO_11] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP11_EINT,
	},
	[WM831X_IRQ_GPIO_12] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP12_EINT,
	},
	[WM831X_IRQ_GPIO_13] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP13_EINT,
	},
	[WM831X_IRQ_GPIO_14] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP14_EINT,
	},
	[WM831X_IRQ_GPIO_15] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP15_EINT,
	},
	[WM831X_IRQ_GPIO_16] = {
		.primary = WM831X_GP_INT,
		.reg = 5,
		.mask = WM831X_GP16_EINT,
	},
	[WM831X_IRQ_ON] = {
		.primary = WM831X_ON_PIN_INT,
		.reg = 1,
		.mask = WM831X_ON_PIN_EINT,
	},
	[WM831X_IRQ_PPM_SYSLO] = {
		.primary = WM831X_PPM_INT,
		.reg = 1,
		.mask = WM831X_PPM_SYSLO_EINT,
	},
	[WM831X_IRQ_PPM_PWR_SRC] = {
		.primary = WM831X_PPM_INT,
		.reg = 1,
		.mask = WM831X_PPM_PWR_SRC_EINT,
	},
	[WM831X_IRQ_PPM_USB_CURR] = {
		.primary = WM831X_PPM_INT,
		.reg = 1,
		.mask = WM831X_PPM_USB_CURR_EINT,
	},
	[WM831X_IRQ_WDOG_TO] = {
		.primary = WM831X_WDOG_INT,
		.reg = 1,
		.mask = WM831X_WDOG_TO_EINT,
	},
	[WM831X_IRQ_RTC_PER] = {
		.primary = WM831X_RTC_INT,
		.reg = 1,
		.mask = WM831X_RTC_PER_EINT,
	},
	[WM831X_IRQ_RTC_ALM] = {
		.primary = WM831X_RTC_INT,
		.reg = 1,
		.mask = WM831X_RTC_ALM_EINT,
	},
	[WM831X_IRQ_CHG_BATT_HOT] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_BATT_HOT_EINT,
	},
	[WM831X_IRQ_CHG_BATT_COLD] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_BATT_COLD_EINT,
	},
	[WM831X_IRQ_CHG_BATT_FAIL] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_BATT_FAIL_EINT,
	},
	[WM831X_IRQ_CHG_OV] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_OV_EINT,
	},
	[WM831X_IRQ_CHG_END] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_END_EINT,
	},
	[WM831X_IRQ_CHG_TO] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_TO_EINT,
	},
	[WM831X_IRQ_CHG_MODE] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_MODE_EINT,
	},
	[WM831X_IRQ_CHG_START] = {
		.primary = WM831X_CHG_INT,
		.reg = 2,
		.mask = WM831X_CHG_START_EINT,
	},
	[WM831X_IRQ_TCHDATA] = {
		.primary = WM831X_TCHDATA_INT,
		.reg = 1,
		.mask = WM831X_TCHDATA_EINT,
	},
	[WM831X_IRQ_TCHPD] = {
		.primary = WM831X_TCHPD_INT,
		.reg = 1,
		.mask = WM831X_TCHPD_EINT,
	},
	[WM831X_IRQ_AUXADC_DATA] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DATA_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP1] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP1_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP2] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP2_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP3] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP3_EINT,
	},
	[WM831X_IRQ_AUXADC_DCOMP4] = {
		.primary = WM831X_AUXADC_INT,
		.reg = 1,
		.mask = WM831X_AUXADC_DCOMP4_EINT,
	},
	[WM831X_IRQ_CS1] = {
		.primary = WM831X_CS_INT,
		.reg = 2,
		.mask = WM831X_CS1_EINT,
	},
	[WM831X_IRQ_CS2] = {
		.primary = WM831X_CS_INT,
		.reg = 2,
		.mask = WM831X_CS2_EINT,
	},
	[WM831X_IRQ_HC_DC1] = {
		.primary = WM831X_HC_INT,
		.reg = 4,
		.mask = WM831X_HC_DC1_EINT,
	},
	[WM831X_IRQ_HC_DC2] = {
		.primary = WM831X_HC_INT,
		.reg = 4,
		.mask = WM831X_HC_DC2_EINT,
	},
	[WM831X_IRQ_UV_LDO1] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO1_EINT,
	},
	[WM831X_IRQ_UV_LDO2] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO2_EINT,
	},
	[WM831X_IRQ_UV_LDO3] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO3_EINT,
	},
	[WM831X_IRQ_UV_LDO4] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO4_EINT,
	},
	[WM831X_IRQ_UV_LDO5] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO5_EINT,
	},
	[WM831X_IRQ_UV_LDO6] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO6_EINT,
	},
	[WM831X_IRQ_UV_LDO7] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO7_EINT,
	},
	[WM831X_IRQ_UV_LDO8] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO8_EINT,
	},
	[WM831X_IRQ_UV_LDO9] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO9_EINT,
	},
	[WM831X_IRQ_UV_LDO10] = {
		.primary = WM831X_UV_INT,
		.reg = 3,
		.mask = WM831X_UV_LDO10_EINT,
	},
	[WM831X_IRQ_UV_DC1] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC1_EINT,
	},
	[WM831X_IRQ_UV_DC2] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC2_EINT,
	},
	[WM831X_IRQ_UV_DC3] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC3_EINT,
	},
	[WM831X_IRQ_UV_DC4] = {
		.primary = WM831X_UV_INT,
		.reg = 4,
		.mask = WM831X_UV_DC4_EINT,
	},
};

static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
{
	return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
}

static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
							int irq)
{
	return &wm831x_irqs[irq];
}

static void wm831x_irq_lock(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);

	mutex_lock(&wm831x->irq_lock);
}

static void wm831x_irq_sync_unlock(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	int i;

	for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
		if (wm831x->gpio_update[i]) {
			wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
					WM831X_GPN_INT_MODE | WM831X_GPN_POL,
					wm831x->gpio_update[i]);
			wm831x->gpio_update[i] = 0;
		}
	}

	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
		/* If there's been a change in the mask write it back
		 * to the hardware. */
		if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
			dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
				WM831X_INTERRUPT_STATUS_1_MASK + i,
				wm831x->irq_masks_cur[i]);

			wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
			wm831x_reg_write(wm831x,
					 WM831X_INTERRUPT_STATUS_1_MASK + i,
					 wm831x->irq_masks_cur[i]);
		}
	}

	mutex_unlock(&wm831x->irq_lock);
}

static void wm831x_irq_enable(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
							     data->hwirq);

	wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
}

static void wm831x_irq_disable(struct irq_data *data)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
							     data->hwirq);

	wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
}

static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
{
	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
	int irq;

	irq = data->hwirq;

	if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
		/* Ignore internal-only IRQs */
		if (irq >= 0 && irq < WM831X_NUM_IRQS)
			return 0;
		else
			return -EINVAL;
	}

	/* Rebase the IRQ into the GPIO range so we've got a sensible array
	 * index.
	 */
	irq -= WM831X_IRQ_GPIO_1;

	/* We set the high bit to flag that we need an update; don't
	 * do the update here as we can be called with the bus lock
	 * held.
	 */
	wm831x->gpio_level_low[irq] = false;
	wm831x->gpio_level_high[irq] = false;
	switch (type) {
	case IRQ_TYPE_EDGE_BOTH:
		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_INT_MODE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		wm831x->gpio_update[irq] = 0x10000;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		wm831x->gpio_update[irq] = 0x10000 | WM831X_GPN_POL;
		wm831x->gpio_level_high[irq] = true;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		wm831x->gpio_update[irq] = 0x10000;
		wm831x->gpio_level_low[irq] = true;
		break;
	default:
		return -EINVAL;
	}

	return 0;
}

static struct irq_chip wm831x_irq_chip = {
	.name			= "wm831x",
	.irq_bus_lock		= wm831x_irq_lock,
	.irq_bus_sync_unlock	= wm831x_irq_sync_unlock,
	.irq_disable		= wm831x_irq_disable,
	.irq_enable		= wm831x_irq_enable,
	.irq_set_type		= wm831x_irq_set_type,
};

/* The processing of the primary interrupt occurs in a thread so that
 * we can interact with the device over I2C or SPI. */
static irqreturn_t wm831x_irq_thread(int irq, void *data)
{
	struct wm831x *wm831x = data;
	unsigned int i;
	int primary, status_addr, ret;
	int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
	int read[WM831X_NUM_IRQ_REGS] = { 0 };
	int *status;

	primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
	if (primary < 0) {
		dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
			primary);
		goto out;
	}

	/* The touch interrupts are visible in the primary register as
	 * an optimisation; open code this to avoid complicating the
	 * main handling loop and so we can also skip iterating the
	 * descriptors.
	 */
	if (primary & WM831X_TCHPD_INT)
		handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
						   WM831X_IRQ_TCHPD));
	if (primary & WM831X_TCHDATA_INT)
		handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
						   WM831X_IRQ_TCHDATA));
	primary &= ~(WM831X_TCHDATA_EINT | WM831X_TCHPD_EINT);

	for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
		int offset = wm831x_irqs[i].reg - 1;

		if (!(primary & wm831x_irqs[i].primary))
			continue;

		status = &status_regs[offset];

		/* Hopefully there should only be one register to read
		 * each time otherwise we ought to do a block read. */
		if (!read[offset]) {
			status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);

			*status = wm831x_reg_read(wm831x, status_addr);
			if (*status < 0) {
				dev_err(wm831x->dev,
					"Failed to read IRQ status: %d\n",
					*status);
				goto out;
			}

			read[offset] = 1;

			/* Ignore any bits that we don't think are masked */
			*status &= ~wm831x->irq_masks_cur[offset];

			/* Acknowledge now so we don't miss
			 * notifications while we handle.
			 */
			wm831x_reg_write(wm831x, status_addr, *status);
		}

		if (*status & wm831x_irqs[i].mask)
			handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
							   i));

		/* Simulate an edge triggered IRQ by polling the input
		 * status.  This is sucky but improves interoperability.
		 */
		if (primary == WM831X_GP_INT &&
		    wm831x->gpio_level_high[i - WM831X_IRQ_GPIO_1]) {
			ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
			while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
				handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
								   i));
				ret = wm831x_reg_read(wm831x,
						      WM831X_GPIO_LEVEL);
			}
		}

		if (primary == WM831X_GP_INT &&
		    wm831x->gpio_level_low[i - WM831X_IRQ_GPIO_1]) {
			ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
			while (!(ret & 1 << (i - WM831X_IRQ_GPIO_1))) {
				handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
								   i));
				ret = wm831x_reg_read(wm831x,
						      WM831X_GPIO_LEVEL);
			}
		}
	}

out:
	return IRQ_HANDLED;
}

static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hw)
{
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
	irq_set_nested_thread(virq, 1);
	irq_set_noprobe(virq);

	return 0;
}

static const struct irq_domain_ops wm831x_irq_domain_ops = {
	.map	= wm831x_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

int wm831x_irq_init(struct wm831x *wm831x, int irq)
{
	struct wm831x_pdata *pdata = &wm831x->pdata;
	struct irq_domain *domain;
	int i, ret, irq_base;

	mutex_init(&wm831x->irq_lock);

	/* Mask the individual interrupt sources */
	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
		wm831x->irq_masks_cur[i] = 0xffff;
		wm831x->irq_masks_cache[i] = 0xffff;
		wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
				 0xffff);
	}

	/* Try to dynamically allocate IRQs if no base is specified */
	if (pdata->irq_base) {
		irq_base = irq_alloc_descs(pdata->irq_base, 0,
					   WM831X_NUM_IRQS, 0);
		if (irq_base < 0) {
			dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
				 irq_base);
			irq_base = 0;
		}
	} else {
		irq_base = 0;
	}

	if (irq_base)
		domain = irq_domain_add_legacy(wm831x->dev->of_node,
					       ARRAY_SIZE(wm831x_irqs),
					       irq_base, 0,
					       &wm831x_irq_domain_ops,
					       wm831x);
	else
		domain = irq_domain_add_linear(wm831x->dev->of_node,
					       ARRAY_SIZE(wm831x_irqs),
					       &wm831x_irq_domain_ops,
					       wm831x);

	if (!domain) {
		dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
		return -EINVAL;
	}

	if (pdata->irq_cmos)
		i = 0;
	else
		i = WM831X_IRQ_OD;

	wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
			WM831X_IRQ_OD, i);

	wm831x->irq = irq;
	wm831x->irq_domain = domain;

	if (irq) {
		/* Try to flag /IRQ as a wake source; there are a number of
		 * unconditional wake sources in the PMIC so this isn't
		 * conditional but we don't actually care *too* much if it
		 * fails.
		 */
		ret = enable_irq_wake(irq);
		if (ret != 0) {
			dev_warn(wm831x->dev,
				 "Can't enable IRQ as wake source: %d\n",
				 ret);
		}

		ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
					   IRQF_TRIGGER_LOW | IRQF_ONESHOT,
					   "wm831x", wm831x);
		if (ret != 0) {
			dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
				irq, ret);
			return ret;
		}
	} else {
		dev_warn(wm831x->dev,
			 "No interrupt specified - functionality limited\n");
	}

	/* Enable top level interrupts, we mask at secondary level */
	wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);

	return 0;
}

void wm831x_irq_exit(struct wm831x *wm831x)
{
	if (wm831x->irq)
		free_irq(wm831x->irq, wm831x);
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
7d4d0a3e MB	2	/*
	3	* wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
	4	*
	5	* Copyright 2009 Wolfson Microelectronics PLC.
	6	*
	7	* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7d4d0a3e MB	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/i2c.h>
5fb4d38b	13	#include <linux/irq.h>
7d4d0a3e MB	14	#include <linux/mfd/core.h>
7d4d0a3e MB	15	#include <linux/interrupt.h>
cd99758b	16	#include <linux/irqdomain.h>
7d4d0a3e MB	17
	18	#include <linux/mfd/wm831x/core.h>
	19	#include <linux/mfd/wm831x/pdata.h>
896060c7	20	#include <linux/mfd/wm831x/gpio.h>
7d4d0a3e MB	21	#include <linux/mfd/wm831x/irq.h>
	22
	23	#include <linux/delay.h>
	24
7d4d0a3e MB	25	struct wm831x_irq_data {
	26	int primary;
	27	int reg;
	28	int mask;
7d4d0a3e MB	29	};
	30
	31	static struct wm831x_irq_data wm831x_irqs[] = {
	32	[WM831X_IRQ_TEMP_THW] = {
	33	.primary = WM831X_TEMP_INT,
	34	.reg = 1,
	35	.mask = WM831X_TEMP_THW_EINT,
	36	},
	37	[WM831X_IRQ_GPIO_1] = {
	38	.primary = WM831X_GP_INT,
	39	.reg = 5,
	40	.mask = WM831X_GP1_EINT,
	41	},
	42	[WM831X_IRQ_GPIO_2] = {
	43	.primary = WM831X_GP_INT,
	44	.reg = 5,
	45	.mask = WM831X_GP2_EINT,
	46	},
	47	[WM831X_IRQ_GPIO_3] = {
	48	.primary = WM831X_GP_INT,
	49	.reg = 5,
	50	.mask = WM831X_GP3_EINT,
	51	},
	52	[WM831X_IRQ_GPIO_4] = {
	53	.primary = WM831X_GP_INT,
	54	.reg = 5,
	55	.mask = WM831X_GP4_EINT,
	56	},
	57	[WM831X_IRQ_GPIO_5] = {
	58	.primary = WM831X_GP_INT,
	59	.reg = 5,
	60	.mask = WM831X_GP5_EINT,
	61	},
	62	[WM831X_IRQ_GPIO_6] = {
	63	.primary = WM831X_GP_INT,
	64	.reg = 5,
	65	.mask = WM831X_GP6_EINT,
	66	},
	67	[WM831X_IRQ_GPIO_7] = {
	68	.primary = WM831X_GP_INT,
	69	.reg = 5,
	70	.mask = WM831X_GP7_EINT,
	71	},
	72	[WM831X_IRQ_GPIO_8] = {
	73	.primary = WM831X_GP_INT,
	74	.reg = 5,
	75	.mask = WM831X_GP8_EINT,
	76	},
	77	[WM831X_IRQ_GPIO_9] = {
	78	.primary = WM831X_GP_INT,
	79	.reg = 5,
	80	.mask = WM831X_GP9_EINT,
	81	},
	82	[WM831X_IRQ_GPIO_10] = {
	83	.primary = WM831X_GP_INT,
	84	.reg = 5,
	85	.mask = WM831X_GP10_EINT,
	86	},
	87	[WM831X_IRQ_GPIO_11] = {
	88	.primary = WM831X_GP_INT,
	89	.reg = 5,
	90	.mask = WM831X_GP11_EINT,
	91	},
	92	[WM831X_IRQ_GPIO_12] = {
93	.primary = WM831X_GP_INT,
94	.reg = 5,
95	.mask = WM831X_GP12_EINT,
96	},
97	[WM831X_IRQ_GPIO_13] = {
98	.primary = WM831X_GP_INT,
99	.reg = 5,
100	.mask = WM831X_GP13_EINT,
101	},
102	[WM831X_IRQ_GPIO_14] = {
103	.primary = WM831X_GP_INT,
104	.reg = 5,
105	.mask = WM831X_GP14_EINT,
106	},
107	[WM831X_IRQ_GPIO_15] = {
108	.primary = WM831X_GP_INT,
109	.reg = 5,
110	.mask = WM831X_GP15_EINT,
111	},
112	[WM831X_IRQ_GPIO_16] = {
113	.primary = WM831X_GP_INT,
114	.reg = 5,
115	.mask = WM831X_GP16_EINT,
116	},
117	[WM831X_IRQ_ON] = {
118	.primary = WM831X_ON_PIN_INT,
119	.reg = 1,
120	.mask = WM831X_ON_PIN_EINT,
121	},
122	[WM831X_IRQ_PPM_SYSLO] = {
123	.primary = WM831X_PPM_INT,
124	.reg = 1,
125	.mask = WM831X_PPM_SYSLO_EINT,
126	},
127	[WM831X_IRQ_PPM_PWR_SRC] = {
128	.primary = WM831X_PPM_INT,
129	.reg = 1,
130	.mask = WM831X_PPM_PWR_SRC_EINT,
131	},
132	[WM831X_IRQ_PPM_USB_CURR] = {
133	.primary = WM831X_PPM_INT,
134	.reg = 1,
135	.mask = WM831X_PPM_USB_CURR_EINT,
136	},
137	[WM831X_IRQ_WDOG_TO] = {
138	.primary = WM831X_WDOG_INT,
139	.reg = 1,
140	.mask = WM831X_WDOG_TO_EINT,
141	},
142	[WM831X_IRQ_RTC_PER] = {
143	.primary = WM831X_RTC_INT,
144	.reg = 1,
145	.mask = WM831X_RTC_PER_EINT,
146	},
147	[WM831X_IRQ_RTC_ALM] = {
148	.primary = WM831X_RTC_INT,
149	.reg = 1,
150	.mask = WM831X_RTC_ALM_EINT,
151	},
152	[WM831X_IRQ_CHG_BATT_HOT] = {
153	.primary = WM831X_CHG_INT,
154	.reg = 2,
155	.mask = WM831X_CHG_BATT_HOT_EINT,
156	},
157	[WM831X_IRQ_CHG_BATT_COLD] = {
158	.primary = WM831X_CHG_INT,
159	.reg = 2,
160	.mask = WM831X_CHG_BATT_COLD_EINT,
161	},
162	[WM831X_IRQ_CHG_BATT_FAIL] = {
163	.primary = WM831X_CHG_INT,
164	.reg = 2,
165	.mask = WM831X_CHG_BATT_FAIL_EINT,
166	},
167	[WM831X_IRQ_CHG_OV] = {
168	.primary = WM831X_CHG_INT,
169	.reg = 2,
170	.mask = WM831X_CHG_OV_EINT,
171	},
172	[WM831X_IRQ_CHG_END] = {
173	.primary = WM831X_CHG_INT,
174	.reg = 2,
175	.mask = WM831X_CHG_END_EINT,
176	},
177	[WM831X_IRQ_CHG_TO] = {
178	.primary = WM831X_CHG_INT,
179	.reg = 2,
180	.mask = WM831X_CHG_TO_EINT,
181	},
182	[WM831X_IRQ_CHG_MODE] = {
183	.primary = WM831X_CHG_INT,
184	.reg = 2,
185	.mask = WM831X_CHG_MODE_EINT,
186	},
187	[WM831X_IRQ_CHG_START] = {
188	.primary = WM831X_CHG_INT,
189	.reg = 2,
190	.mask = WM831X_CHG_START_EINT,
191	},
192	[WM831X_IRQ_TCHDATA] = {
193	.primary = WM831X_TCHDATA_INT,
194	.reg = 1,
195	.mask = WM831X_TCHDATA_EINT,
196	},
197	[WM831X_IRQ_TCHPD] = {
198	.primary = WM831X_TCHPD_INT,
199	.reg = 1,
200	.mask = WM831X_TCHPD_EINT,
201	},
202	[WM831X_IRQ_AUXADC_DATA] = {
203	.primary = WM831X_AUXADC_INT,
204	.reg = 1,
205	.mask = WM831X_AUXADC_DATA_EINT,
206	},
207	[WM831X_IRQ_AUXADC_DCOMP1] = {
208	.primary = WM831X_AUXADC_INT,
209	.reg = 1,
210	.mask = WM831X_AUXADC_DCOMP1_EINT,
211	},
212	[WM831X_IRQ_AUXADC_DCOMP2] = {
213	.primary = WM831X_AUXADC_INT,
214	.reg = 1,
215	.mask = WM831X_AUXADC_DCOMP2_EINT,
216	},
217	[WM831X_IRQ_AUXADC_DCOMP3] = {
218	.primary = WM831X_AUXADC_INT,
219	.reg = 1,
220	.mask = WM831X_AUXADC_DCOMP3_EINT,
221	},
222	[WM831X_IRQ_AUXADC_DCOMP4] = {
223	.primary = WM831X_AUXADC_INT,
224	.reg = 1,
225	.mask = WM831X_AUXADC_DCOMP4_EINT,
226	},
227	[WM831X_IRQ_CS1] = {
228	.primary = WM831X_CS_INT,
229	.reg = 2,
230	.mask = WM831X_CS1_EINT,
231	},
232	[WM831X_IRQ_CS2] = {
233	.primary = WM831X_CS_INT,
234	.reg = 2,
235	.mask = WM831X_CS2_EINT,
236	},
237	[WM831X_IRQ_HC_DC1] = {
238	.primary = WM831X_HC_INT,
239	.reg = 4,
240	.mask = WM831X_HC_DC1_EINT,
241	},
242	[WM831X_IRQ_HC_DC2] = {
243	.primary = WM831X_HC_INT,
244	.reg = 4,
245	.mask = WM831X_HC_DC2_EINT,
246	},
247	[WM831X_IRQ_UV_LDO1] = {
248	.primary = WM831X_UV_INT,
249	.reg = 3,
250	.mask = WM831X_UV_LDO1_EINT,
251	},
252	[WM831X_IRQ_UV_LDO2] = {
253	.primary = WM831X_UV_INT,
254	.reg = 3,
255	.mask = WM831X_UV_LDO2_EINT,
256	},
257	[WM831X_IRQ_UV_LDO3] = {
258	.primary = WM831X_UV_INT,
259	.reg = 3,
260	.mask = WM831X_UV_LDO3_EINT,
261	},
262	[WM831X_IRQ_UV_LDO4] = {
263	.primary = WM831X_UV_INT,
264	.reg = 3,
265	.mask = WM831X_UV_LDO4_EINT,
266	},
267	[WM831X_IRQ_UV_LDO5] = {
268	.primary = WM831X_UV_INT,
269	.reg = 3,
270	.mask = WM831X_UV_LDO5_EINT,
271	},
272	[WM831X_IRQ_UV_LDO6] = {
273	.primary = WM831X_UV_INT,
274	.reg = 3,
275	.mask = WM831X_UV_LDO6_EINT,
276	},
277	[WM831X_IRQ_UV_LDO7] = {
278	.primary = WM831X_UV_INT,
279	.reg = 3,
280	.mask = WM831X_UV_LDO7_EINT,
281	},
282	[WM831X_IRQ_UV_LDO8] = {
283	.primary = WM831X_UV_INT,
284	.reg = 3,
285	.mask = WM831X_UV_LDO8_EINT,
286	},
287	[WM831X_IRQ_UV_LDO9] = {
288	.primary = WM831X_UV_INT,
289	.reg = 3,
290	.mask = WM831X_UV_LDO9_EINT,
291	},
292	[WM831X_IRQ_UV_LDO10] = {
293	.primary = WM831X_UV_INT,
294	.reg = 3,
295	.mask = WM831X_UV_LDO10_EINT,
296	},
297	[WM831X_IRQ_UV_DC1] = {
298	.primary = WM831X_UV_INT,
299	.reg = 4,
300	.mask = WM831X_UV_DC1_EINT,
301	},
302	[WM831X_IRQ_UV_DC2] = {
303	.primary = WM831X_UV_INT,
304	.reg = 4,
305	.mask = WM831X_UV_DC2_EINT,
306	},
307	[WM831X_IRQ_UV_DC3] = {
308	.primary = WM831X_UV_INT,
309	.reg = 4,
310	.mask = WM831X_UV_DC3_EINT,
311	},
312	[WM831X_IRQ_UV_DC4] = {
313	.primary = WM831X_UV_INT,
314	.reg = 4,
315	.mask = WM831X_UV_DC4_EINT,
316	},
317	};
318
319	static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
320	{
321	return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
322	}
323
5fb4d38b MB	324	static inline struct wm831x_irq_data irq_to_wm831x_irq(struct wm831x wm831x,
5fb4d38b MB	325	int irq)
7d4d0a3e	326	{
cd99758b	327	return &wm831x_irqs[irq];
7d4d0a3e MB	328	}
7d4d0a3e MB	329
ba81cd39	330	static void wm831x_irq_lock(struct irq_data *data)
7d4d0a3e	331	{
25a947f8	332	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
7d4d0a3e	333
7d4d0a3e	334	mutex_lock(&wm831x->irq_lock);
7d4d0a3e	335	}
7d4d0a3e	336
ba81cd39	337	static void wm831x_irq_sync_unlock(struct irq_data *data)
7d4d0a3e	338	{
25a947f8	339	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
5fb4d38b MB	340	int i;
5fb4d38b MB	341
ca7a7182 MB	342	for (i = 0; i < ARRAY_SIZE(wm831x->gpio_update); i++) {
	343	if (wm831x->gpio_update[i]) {
	344	wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + i,
	345	WM831X_GPN_INT_MODE \| WM831X_GPN_POL,
	346	wm831x->gpio_update[i]);
	347	wm831x->gpio_update[i] = 0;
	348	}
	349	}
	350
5fb4d38b MB	351	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
	352	/* If there's been a change in the mask write it back
	353	* to the hardware. */
	354	if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
f624effb MB	355	dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n",
	356	WM831X_INTERRUPT_STATUS_1_MASK + i,
	357	wm831x->irq_masks_cur[i]);
	358
5fb4d38b MB	359	wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
	360	wm831x_reg_write(wm831x,
	361	WM831X_INTERRUPT_STATUS_1_MASK + i,
	362	wm831x->irq_masks_cur[i]);
	363	}
7d4d0a3e MB	364	}
7d4d0a3e MB	365
7d4d0a3e	366	mutex_unlock(&wm831x->irq_lock);
7d4d0a3e	367	}
7d4d0a3e	368
f624effb	369	static void wm831x_irq_enable(struct irq_data *data)
7d4d0a3e	370	{
25a947f8	371	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
ba81cd39	372	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
cd99758b	373	data->hwirq);
7d4d0a3e	374
5fb4d38b	375	wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
7d4d0a3e	376	}
7d4d0a3e	377
f624effb	378	static void wm831x_irq_disable(struct irq_data *data)
7d4d0a3e	379	{
25a947f8	380	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
ba81cd39	381	struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x,
cd99758b	382	data->hwirq);
5fb4d38b MB	383
5fb4d38b MB	384	wm831x->irq_masks_cur[irq_data->reg - 1] \|= irq_data->mask;
7d4d0a3e MB	385	}
7d4d0a3e MB	386
ba81cd39	387	static int wm831x_irq_set_type(struct irq_data *data, unsigned int type)
896060c7	388	{
25a947f8	389	struct wm831x *wm831x = irq_data_get_irq_chip_data(data);
ca7a7182	390	int irq;
896060c7	391
cd99758b	392	irq = data->hwirq;
896060c7	393
c9d66d35 MB	394	if (irq < WM831X_IRQ_GPIO_1 \|\| irq > WM831X_IRQ_GPIO_11) {
	395	/* Ignore internal-only IRQs */
	396	if (irq >= 0 && irq < WM831X_NUM_IRQS)
	397	return 0;
	398	else
	399	return -EINVAL;
	400	}
896060c7	401
08256712 DP	402	/* Rebase the IRQ into the GPIO range so we've got a sensible array
	403	* index.
	404	*/
	405	irq -= WM831X_IRQ_GPIO_1;
	406
ca7a7182 MB	407	/* We set the high bit to flag that we need an update; don't
	408	* do the update here as we can be called with the bus lock
	409	* held.
	410	*/
1fe17a24 MB	411	wm831x->gpio_level_low[irq] = false;
1fe17a24 MB	412	wm831x->gpio_level_high[irq] = false;
896060c7 MB	413	switch (type) {
896060c7 MB	414	case IRQ_TYPE_EDGE_BOTH:
ca7a7182	415	wm831x->gpio_update[irq] = 0x10000 \| WM831X_GPN_INT_MODE;
896060c7 MB	416	break;
896060c7 MB	417	case IRQ_TYPE_EDGE_RISING:
ca7a7182	418	wm831x->gpio_update[irq] = 0x10000 \| WM831X_GPN_POL;
896060c7 MB	419	break;
896060c7 MB	420	case IRQ_TYPE_EDGE_FALLING:
ca7a7182	421	wm831x->gpio_update[irq] = 0x10000;
7583a213 MB	422	break;
	423	case IRQ_TYPE_LEVEL_HIGH:
	424	wm831x->gpio_update[irq] = 0x10000 \| WM831X_GPN_POL;
1fe17a24 MB	425	wm831x->gpio_level_high[irq] = true;
	426	break;
	427	case IRQ_TYPE_LEVEL_LOW:
	428	wm831x->gpio_update[irq] = 0x10000;
	429	wm831x->gpio_level_low[irq] = true;
896060c7 MB	430	break;
	431	default:
	432	return -EINVAL;
	433	}
	434
ca7a7182	435	return 0;
896060c7 MB	436	}
896060c7 MB	437
5fb4d38b	438	static struct irq_chip wm831x_irq_chip = {
ba81cd39 MB	439	.name = "wm831x",
	440	.irq_bus_lock = wm831x_irq_lock,
	441	.irq_bus_sync_unlock = wm831x_irq_sync_unlock,
f624effb MB	442	.irq_disable = wm831x_irq_disable,
f624effb MB	443	.irq_enable = wm831x_irq_enable,
ba81cd39	444	.irq_set_type = wm831x_irq_set_type,
5fb4d38b MB	445	};
	446
	447	/* The processing of the primary interrupt occurs in a thread so that
	448	* we can interact with the device over I2C or SPI. */
	449	static irqreturn_t wm831x_irq_thread(int irq, void *data)
7d4d0a3e	450	{
5fb4d38b	451	struct wm831x *wm831x = data;
7d4d0a3e	452	unsigned int i;
7583a213	453	int primary, status_addr, ret;
5fb4d38b MB	454	int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
5fb4d38b MB	455	int read[WM831X_NUM_IRQ_REGS] = { 0 };
7d4d0a3e MB	456	int *status;
	457
	458	primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
	459	if (primary < 0) {
	460	dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
	461	primary);
	462	goto out;
	463	}
	464
8546bd4a MB	465	/* The touch interrupts are visible in the primary register as
	466	* an optimisation; open code this to avoid complicating the
	467	* main handling loop and so we can also skip iterating the
	468	* descriptors.
	469	*/
	470	if (primary & WM831X_TCHPD_INT)
cd99758b MB	471	handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
cd99758b MB	472	WM831X_IRQ_TCHPD));
8546bd4a	473	if (primary & WM831X_TCHDATA_INT)
cd99758b MB	474	handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
cd99758b MB	475	WM831X_IRQ_TCHDATA));
953c7d02	476	primary &= ~(WM831X_TCHDATA_EINT \| WM831X_TCHPD_EINT);
8546bd4a	477
7d4d0a3e MB	478	for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
	479	int offset = wm831x_irqs[i].reg - 1;
	480
	481	if (!(primary & wm831x_irqs[i].primary))
	482	continue;
	483
	484	status = &status_regs[offset];
	485
	486	/* Hopefully there should only be one register to read
	487	* each time otherwise we ought to do a block read. */
	488	if (!read[offset]) {
88c93977 MB	489	status_addr = irq_data_to_status_reg(&wm831x_irqs[i]);
	490
	491	*status = wm831x_reg_read(wm831x, status_addr);
7d4d0a3e MB	492	if (*status < 0) {
	493	dev_err(wm831x->dev,
	494	"Failed to read IRQ status: %d\n",
	495	*status);
5fb4d38b	496	goto out;
7d4d0a3e MB	497	}
7d4d0a3e MB	498
7d4d0a3e	499	read[offset] = 1;
88c93977 MB	500
	501	/* Ignore any bits that we don't think are masked */
	502	*status &= ~wm831x->irq_masks_cur[offset];
	503
	504	/* Acknowledge now so we don't miss
	505	* notifications while we handle.
	506	*/
	507	wm831x_reg_write(wm831x, status_addr, *status);
7d4d0a3e MB	508	}
7d4d0a3e MB	509
88c93977	510	if (*status & wm831x_irqs[i].mask)
cd99758b MB	511	handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
cd99758b MB	512	i));
7583a213 MB	513
	514	/* Simulate an edge triggered IRQ by polling the input
	515	* status. This is sucky but improves interoperability.
	516	*/
	517	if (primary == WM831X_GP_INT &&
1fe17a24	518	wm831x->gpio_level_high[i - WM831X_IRQ_GPIO_1]) {
7583a213 MB	519	ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
7583a213 MB	520	while (ret & 1 << (i - WM831X_IRQ_GPIO_1)) {
1fe17a24 MB	521	handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
	522	i));
	523	ret = wm831x_reg_read(wm831x,
	524	WM831X_GPIO_LEVEL);
	525	}
	526	}
	527
	528	if (primary == WM831X_GP_INT &&
	529	wm831x->gpio_level_low[i - WM831X_IRQ_GPIO_1]) {
	530	ret = wm831x_reg_read(wm831x, WM831X_GPIO_LEVEL);
	531	while (!(ret & 1 << (i - WM831X_IRQ_GPIO_1))) {
cd99758b MB	532	handle_nested_irq(irq_find_mapping(wm831x->irq_domain,
cd99758b MB	533	i));
7583a213 MB	534	ret = wm831x_reg_read(wm831x,
	535	WM831X_GPIO_LEVEL);
	536	}
	537	}
7d4d0a3e MB	538	}
7d4d0a3e MB	539
7d4d0a3e	540	out:
7d4d0a3e MB	541	return IRQ_HANDLED;
	542	}
	543
cd99758b MB	544	static int wm831x_irq_map(struct irq_domain *h, unsigned int virq,
	545	irq_hw_number_t hw)
	546	{
	547	irq_set_chip_data(virq, h->host_data);
	548	irq_set_chip_and_handler(virq, &wm831x_irq_chip, handle_edge_irq);
	549	irq_set_nested_thread(virq, 1);
cd99758b	550	irq_set_noprobe(virq);
cd99758b MB	551
	552	return 0;
	553	}
	554
7ce7b26f	555	static const struct irq_domain_ops wm831x_irq_domain_ops = {
cd99758b MB	556	.map = wm831x_irq_map,
	557	.xlate = irq_domain_xlate_twocell,
	558	};
	559
7d4d0a3e MB	560	int wm831x_irq_init(struct wm831x *wm831x, int irq)
7d4d0a3e MB	561	{
f6dd8449	562	struct wm831x_pdata *pdata = &wm831x->pdata;
cd99758b MB	563	struct irq_domain *domain;
cd99758b MB	564	int i, ret, irq_base;
7d4d0a3e	565
14f572fa MB	566	mutex_init(&wm831x->irq_lock);
14f572fa MB	567
0d7e0e39 MB	568	/* Mask the individual interrupt sources */
	569	for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
	570	wm831x->irq_masks_cur[i] = 0xffff;
	571	wm831x->irq_masks_cache[i] = 0xffff;
	572	wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
	573	0xffff);
	574	}
	575
5c05a8d1	576	/* Try to dynamically allocate IRQs if no base is specified */
f6dd8449	577	if (pdata->irq_base) {
cd99758b MB	578	irq_base = irq_alloc_descs(pdata->irq_base, 0,
	579	WM831X_NUM_IRQS, 0);
	580	if (irq_base < 0) {
	581	dev_warn(wm831x->dev, "Failed to allocate IRQs: %d\n",
	582	irq_base);
	583	irq_base = 0;
	584	}
	585	} else {
	586	irq_base = 0;
	587	}
	588
	589	if (irq_base)
	590	domain = irq_domain_add_legacy(wm831x->dev->of_node,
	591	ARRAY_SIZE(wm831x_irqs),
	592	irq_base, 0,
	593	&wm831x_irq_domain_ops,
	594	wm831x);
5c05a8d1	595	else
cd99758b MB	596	domain = irq_domain_add_linear(wm831x->dev->of_node,
	597	ARRAY_SIZE(wm831x_irqs),
	598	&wm831x_irq_domain_ops,
	599	wm831x);
5c05a8d1	600
cd99758b MB	601	if (!domain) {
	602	dev_warn(wm831x->dev, "Failed to allocate IRQ domain\n");
	603	return -EINVAL;
7d4d0a3e MB	604	}
7d4d0a3e MB	605
f6dd8449	606	if (pdata->irq_cmos)
b103e0b3 MB	607	i = 0;
	608	else
	609	i = WM831X_IRQ_OD;
	610
	611	wm831x_set_bits(wm831x, WM831X_IRQ_CONFIG,
	612	WM831X_IRQ_OD, i);
	613
7d4d0a3e	614	wm831x->irq = irq;
cd99758b	615	wm831x->irq_domain = domain;
7d4d0a3e	616
bc86fcee	617	if (irq) {
4492c4c3 MB	618	/* Try to flag /IRQ as a wake source; there are a number of
	619	* unconditional wake sources in the PMIC so this isn't
	620	* conditional but we don't actually care too much if it
	621	* fails.
	622	*/
	623	ret = enable_irq_wake(irq);
	624	if (ret != 0) {
	625	dev_warn(wm831x->dev,
	626	"Can't enable IRQ as wake source: %d\n",
	627	ret);
	628	}
	629
bc86fcee MB	630	ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
	631	IRQF_TRIGGER_LOW \| IRQF_ONESHOT,
	632	"wm831x", wm831x);
	633	if (ret != 0) {
	634	dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
	635	irq, ret);
	636	return ret;
	637	}
	638	} else {
	639	dev_warn(wm831x->dev,
	640	"No interrupt specified - functionality limited\n");
7d4d0a3e MB	641	}
7d4d0a3e MB	642
5fb4d38b MB	643	/* Enable top level interrupts, we mask at secondary level */
	644	wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
	645
7d4d0a3e MB	646	return 0;
	647	}
	648
	649	void wm831x_irq_exit(struct wm831x *wm831x)
	650	{
	651	if (wm831x->irq)
	652	free_irq(wm831x->irq, wm831x);
	653	}