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05c45ca9 RK |
1 | /* |
2 | * linux/drivers/mfd/ucb1x00-core.c | |
3 | * | |
4 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License. | |
9 | * | |
10 | * The UCB1x00 core driver provides basic services for handling IO, | |
11 | * the ADC, interrupts, and accessing registers. It is designed | |
12 | * such that everything goes through this layer, thereby providing | |
13 | * a consistent locking methodology, as well as allowing the drivers | |
14 | * to be used on other non-MCP-enabled hardware platforms. | |
15 | * | |
16 | * Note that all locks are private to this file. Nothing else may | |
17 | * touch them. | |
18 | */ | |
05c45ca9 RK |
19 | #include <linux/module.h> |
20 | #include <linux/kernel.h> | |
d43c36dc | 21 | #include <linux/sched.h> |
05c45ca9 RK |
22 | #include <linux/slab.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/device.h> | |
a621aaed | 27 | #include <linux/mutex.h> |
c8602edf | 28 | #include <linux/mfd/ucb1x00.h> |
5a09b712 | 29 | #include <linux/pm.h> |
9ca3dc80 | 30 | #include <linux/gpio.h> |
05c45ca9 | 31 | |
a621aaed | 32 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
33 | static LIST_HEAD(ucb1x00_drivers); |
34 | static LIST_HEAD(ucb1x00_devices); | |
35 | ||
36 | /** | |
37 | * ucb1x00_io_set_dir - set IO direction | |
38 | * @ucb: UCB1x00 structure describing chip | |
39 | * @in: bitfield of IO pins to be set as inputs | |
40 | * @out: bitfield of IO pins to be set as outputs | |
41 | * | |
42 | * Set the IO direction of the ten general purpose IO pins on | |
43 | * the UCB1x00 chip. The @in bitfield has priority over the | |
44 | * @out bitfield, in that if you specify a pin as both input | |
45 | * and output, it will end up as an input. | |
46 | * | |
47 | * ucb1x00_enable must have been called to enable the comms | |
48 | * before using this function. | |
49 | * | |
50 | * This function takes a spinlock, disabling interrupts. | |
51 | */ | |
52 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
53 | { | |
54 | unsigned long flags; | |
55 | ||
56 | spin_lock_irqsave(&ucb->io_lock, flags); | |
57 | ucb->io_dir |= out; | |
58 | ucb->io_dir &= ~in; | |
59 | ||
60 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
61 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
62 | } | |
63 | ||
64 | /** | |
65 | * ucb1x00_io_write - set or clear IO outputs | |
66 | * @ucb: UCB1x00 structure describing chip | |
67 | * @set: bitfield of IO pins to set to logic '1' | |
68 | * @clear: bitfield of IO pins to set to logic '0' | |
69 | * | |
70 | * Set the IO output state of the specified IO pins. The value | |
71 | * is retained if the pins are subsequently configured as inputs. | |
72 | * The @clear bitfield has priority over the @set bitfield - | |
73 | * outputs will be cleared. | |
74 | * | |
75 | * ucb1x00_enable must have been called to enable the comms | |
76 | * before using this function. | |
77 | * | |
78 | * This function takes a spinlock, disabling interrupts. | |
79 | */ | |
80 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
81 | { | |
82 | unsigned long flags; | |
83 | ||
84 | spin_lock_irqsave(&ucb->io_lock, flags); | |
85 | ucb->io_out |= set; | |
86 | ucb->io_out &= ~clear; | |
87 | ||
88 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
89 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
90 | } | |
91 | ||
92 | /** | |
93 | * ucb1x00_io_read - read the current state of the IO pins | |
94 | * @ucb: UCB1x00 structure describing chip | |
95 | * | |
96 | * Return a bitfield describing the logic state of the ten | |
97 | * general purpose IO pins. | |
98 | * | |
99 | * ucb1x00_enable must have been called to enable the comms | |
100 | * before using this function. | |
101 | * | |
cae15476 | 102 | * This function does not take any mutexes or spinlocks. |
05c45ca9 RK |
103 | */ |
104 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
105 | { | |
106 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
107 | } | |
108 | ||
9ca3dc80 TK |
109 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
110 | { | |
111 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
112 | unsigned long flags; | |
113 | ||
114 | spin_lock_irqsave(&ucb->io_lock, flags); | |
115 | if (value) | |
116 | ucb->io_out |= 1 << offset; | |
117 | else | |
118 | ucb->io_out &= ~(1 << offset); | |
119 | ||
ed442b67 | 120 | ucb1x00_enable(ucb); |
9ca3dc80 | 121 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
ed442b67 | 122 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
123 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
124 | } | |
125 | ||
126 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
127 | { | |
128 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
ed442b67 RK |
129 | unsigned val; |
130 | ||
131 | ucb1x00_enable(ucb); | |
132 | val = ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
133 | ucb1x00_disable(ucb); | |
134 | ||
135 | return val & (1 << offset); | |
9ca3dc80 TK |
136 | } |
137 | ||
138 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
139 | { | |
140 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
141 | unsigned long flags; | |
142 | ||
143 | spin_lock_irqsave(&ucb->io_lock, flags); | |
144 | ucb->io_dir &= ~(1 << offset); | |
ed442b67 | 145 | ucb1x00_enable(ucb); |
9ca3dc80 | 146 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 147 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
148 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
154 | , int value) | |
155 | { | |
156 | struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio); | |
157 | unsigned long flags; | |
c23bb602 | 158 | unsigned old, mask = 1 << offset; |
9ca3dc80 TK |
159 | |
160 | spin_lock_irqsave(&ucb->io_lock, flags); | |
c23bb602 | 161 | old = ucb->io_out; |
9ca3dc80 | 162 | if (value) |
c23bb602 | 163 | ucb->io_out |= mask; |
9ca3dc80 | 164 | else |
c23bb602 RK |
165 | ucb->io_out &= ~mask; |
166 | ||
ed442b67 | 167 | ucb1x00_enable(ucb); |
c23bb602 RK |
168 | if (old != ucb->io_out) |
169 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
170 | ||
171 | if (!(ucb->io_dir & mask)) { | |
172 | ucb->io_dir |= mask; | |
173 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
174 | } | |
ed442b67 | 175 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
176 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
177 | ||
178 | return 0; | |
179 | } | |
180 | ||
05c45ca9 RK |
181 | /* |
182 | * UCB1300 data sheet says we must: | |
183 | * 1. enable ADC => 5us (including reference startup time) | |
184 | * 2. select input => 51*tsibclk => 4.3us | |
185 | * 3. start conversion => 102*tsibclk => 8.5us | |
186 | * (tsibclk = 1/11981000) | |
187 | * Period between SIB 128-bit frames = 10.7us | |
188 | */ | |
189 | ||
190 | /** | |
191 | * ucb1x00_adc_enable - enable the ADC converter | |
192 | * @ucb: UCB1x00 structure describing chip | |
193 | * | |
194 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
195 | * Any code wishing to use the ADC converter must call this | |
196 | * function prior to using it. | |
197 | * | |
cae15476 | 198 | * This function takes the ADC mutex to prevent two or more |
05c45ca9 RK |
199 | * concurrent uses, and therefore may sleep. As a result, it |
200 | * can only be called from process context, not interrupt | |
201 | * context. | |
202 | * | |
203 | * You should release the ADC as soon as possible using | |
204 | * ucb1x00_adc_disable. | |
205 | */ | |
206 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
207 | { | |
cae15476 | 208 | mutex_lock(&ucb->adc_mutex); |
05c45ca9 RK |
209 | |
210 | ucb->adc_cr |= UCB_ADC_ENA; | |
211 | ||
212 | ucb1x00_enable(ucb); | |
213 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
214 | } | |
215 | ||
216 | /** | |
217 | * ucb1x00_adc_read - read the specified ADC channel | |
218 | * @ucb: UCB1x00 structure describing chip | |
219 | * @adc_channel: ADC channel mask | |
220 | * @sync: wait for syncronisation pulse. | |
221 | * | |
222 | * Start an ADC conversion and wait for the result. Note that | |
223 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
224 | * until the trigger is asserted and the conversion is finished. | |
225 | * | |
226 | * This function currently spins waiting for the conversion to | |
227 | * complete (2 frames max without sync). | |
228 | * | |
229 | * If called for a synchronised ADC conversion, it may sleep | |
cae15476 | 230 | * with the ADC mutex held. |
05c45ca9 RK |
231 | */ |
232 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
233 | { | |
234 | unsigned int val; | |
235 | ||
236 | if (sync) | |
237 | adc_channel |= UCB_ADC_SYNC_ENA; | |
238 | ||
239 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
240 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
241 | ||
242 | for (;;) { | |
243 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
244 | if (val & UCB_ADC_DAT_VAL) | |
245 | break; | |
246 | /* yield to other processes */ | |
247 | set_current_state(TASK_INTERRUPTIBLE); | |
248 | schedule_timeout(1); | |
249 | } | |
250 | ||
251 | return UCB_ADC_DAT(val); | |
252 | } | |
253 | ||
254 | /** | |
255 | * ucb1x00_adc_disable - disable the ADC converter | |
256 | * @ucb: UCB1x00 structure describing chip | |
257 | * | |
cae15476 | 258 | * Disable the ADC converter and release the ADC mutex. |
05c45ca9 RK |
259 | */ |
260 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
261 | { | |
262 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
263 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
264 | ucb1x00_disable(ucb); | |
265 | ||
cae15476 | 266 | mutex_unlock(&ucb->adc_mutex); |
05c45ca9 RK |
267 | } |
268 | ||
269 | /* | |
270 | * UCB1x00 Interrupt handling. | |
271 | * | |
272 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
273 | * Since we need to read an internal register, we must re-enable | |
274 | * SIBCLK to talk to the chip. We leave the clock running until | |
275 | * we have finished processing all interrupts from the chip. | |
276 | */ | |
7d12e780 | 277 | static irqreturn_t ucb1x00_irq(int irqnr, void *devid) |
05c45ca9 RK |
278 | { |
279 | struct ucb1x00 *ucb = devid; | |
280 | struct ucb1x00_irq *irq; | |
281 | unsigned int isr, i; | |
282 | ||
283 | ucb1x00_enable(ucb); | |
284 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
285 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
286 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
287 | ||
288 | for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++) | |
289 | if (isr & 1 && irq->fn) | |
290 | irq->fn(i, irq->devid); | |
291 | ucb1x00_disable(ucb); | |
292 | ||
293 | return IRQ_HANDLED; | |
294 | } | |
295 | ||
296 | /** | |
297 | * ucb1x00_hook_irq - hook a UCB1x00 interrupt | |
298 | * @ucb: UCB1x00 structure describing chip | |
299 | * @idx: interrupt index | |
300 | * @fn: function to call when interrupt is triggered | |
301 | * @devid: device id to pass to interrupt handler | |
302 | * | |
303 | * Hook the specified interrupt. You can only register one handler | |
304 | * for each interrupt source. The interrupt source is not enabled | |
305 | * by this function; use ucb1x00_enable_irq instead. | |
306 | * | |
307 | * Interrupt handlers will be called with other interrupts enabled. | |
308 | * | |
309 | * Returns zero on success, or one of the following errors: | |
310 | * -EINVAL if the interrupt index is invalid | |
311 | * -EBUSY if the interrupt has already been hooked | |
312 | */ | |
313 | int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid) | |
314 | { | |
315 | struct ucb1x00_irq *irq; | |
316 | int ret = -EINVAL; | |
317 | ||
318 | if (idx < 16) { | |
319 | irq = ucb->irq_handler + idx; | |
320 | ret = -EBUSY; | |
321 | ||
322 | spin_lock_irq(&ucb->lock); | |
323 | if (irq->fn == NULL) { | |
324 | irq->devid = devid; | |
325 | irq->fn = fn; | |
326 | ret = 0; | |
327 | } | |
328 | spin_unlock_irq(&ucb->lock); | |
329 | } | |
330 | return ret; | |
331 | } | |
332 | ||
333 | /** | |
334 | * ucb1x00_enable_irq - enable an UCB1x00 interrupt source | |
335 | * @ucb: UCB1x00 structure describing chip | |
336 | * @idx: interrupt index | |
337 | * @edges: interrupt edges to enable | |
338 | * | |
339 | * Enable the specified interrupt to trigger on %UCB_RISING, | |
340 | * %UCB_FALLING or both edges. The interrupt should have been | |
341 | * hooked by ucb1x00_hook_irq. | |
342 | */ | |
343 | void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
344 | { | |
345 | unsigned long flags; | |
346 | ||
347 | if (idx < 16) { | |
348 | spin_lock_irqsave(&ucb->lock, flags); | |
349 | ||
350 | ucb1x00_enable(ucb); | |
351 | if (edges & UCB_RISING) { | |
352 | ucb->irq_ris_enbl |= 1 << idx; | |
353 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
354 | } | |
355 | if (edges & UCB_FALLING) { | |
356 | ucb->irq_fal_enbl |= 1 << idx; | |
357 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
358 | } | |
359 | ucb1x00_disable(ucb); | |
360 | spin_unlock_irqrestore(&ucb->lock, flags); | |
361 | } | |
362 | } | |
363 | ||
364 | /** | |
365 | * ucb1x00_disable_irq - disable an UCB1x00 interrupt source | |
366 | * @ucb: UCB1x00 structure describing chip | |
367 | * @edges: interrupt edges to disable | |
368 | * | |
369 | * Disable the specified interrupt triggering on the specified | |
370 | * (%UCB_RISING, %UCB_FALLING or both) edges. | |
371 | */ | |
372 | void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges) | |
373 | { | |
374 | unsigned long flags; | |
375 | ||
376 | if (idx < 16) { | |
377 | spin_lock_irqsave(&ucb->lock, flags); | |
378 | ||
379 | ucb1x00_enable(ucb); | |
380 | if (edges & UCB_RISING) { | |
381 | ucb->irq_ris_enbl &= ~(1 << idx); | |
382 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
383 | } | |
384 | if (edges & UCB_FALLING) { | |
385 | ucb->irq_fal_enbl &= ~(1 << idx); | |
386 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
387 | } | |
388 | ucb1x00_disable(ucb); | |
389 | spin_unlock_irqrestore(&ucb->lock, flags); | |
390 | } | |
391 | } | |
392 | ||
393 | /** | |
394 | * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt | |
395 | * @ucb: UCB1x00 structure describing chip | |
396 | * @idx: interrupt index | |
397 | * @devid: device id. | |
398 | * | |
399 | * Disable the interrupt source and remove the handler. devid must | |
400 | * match the devid passed when hooking the interrupt. | |
401 | * | |
402 | * Returns zero on success, or one of the following errors: | |
403 | * -EINVAL if the interrupt index is invalid | |
404 | * -ENOENT if devid does not match | |
405 | */ | |
406 | int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid) | |
407 | { | |
408 | struct ucb1x00_irq *irq; | |
409 | int ret; | |
410 | ||
411 | if (idx >= 16) | |
412 | goto bad; | |
413 | ||
414 | irq = ucb->irq_handler + idx; | |
415 | ret = -ENOENT; | |
416 | ||
417 | spin_lock_irq(&ucb->lock); | |
418 | if (irq->devid == devid) { | |
419 | ucb->irq_ris_enbl &= ~(1 << idx); | |
420 | ucb->irq_fal_enbl &= ~(1 << idx); | |
421 | ||
422 | ucb1x00_enable(ucb); | |
423 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl); | |
424 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl); | |
425 | ucb1x00_disable(ucb); | |
426 | ||
427 | irq->fn = NULL; | |
428 | irq->devid = NULL; | |
429 | ret = 0; | |
430 | } | |
431 | spin_unlock_irq(&ucb->lock); | |
432 | return ret; | |
433 | ||
434 | bad: | |
435 | printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx); | |
436 | return -EINVAL; | |
437 | } | |
438 | ||
439 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) | |
440 | { | |
441 | struct ucb1x00_dev *dev; | |
442 | int ret = -ENOMEM; | |
443 | ||
444 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
445 | if (dev) { | |
446 | dev->ucb = ucb; | |
447 | dev->drv = drv; | |
448 | ||
449 | ret = drv->add(dev); | |
450 | ||
451 | if (ret == 0) { | |
65b539bb RK |
452 | list_add_tail(&dev->dev_node, &ucb->devs); |
453 | list_add_tail(&dev->drv_node, &drv->devs); | |
05c45ca9 RK |
454 | } else { |
455 | kfree(dev); | |
456 | } | |
457 | } | |
458 | return ret; | |
459 | } | |
460 | ||
461 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
462 | { | |
463 | dev->drv->remove(dev); | |
464 | list_del(&dev->dev_node); | |
465 | list_del(&dev->drv_node); | |
466 | kfree(dev); | |
467 | } | |
468 | ||
469 | /* | |
470 | * Try to probe our interrupt, rather than relying on lots of | |
471 | * hard-coded machine dependencies. For reference, the expected | |
472 | * IRQ mappings are: | |
473 | * | |
474 | * Machine Default IRQ | |
475 | * adsbitsy IRQ_GPCIN4 | |
476 | * cerf IRQ_GPIO_UCB1200_IRQ | |
477 | * flexanet IRQ_GPIO_GUI | |
478 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
479 | * graphicsclient ADS_EXT_IRQ(8) | |
480 | * graphicsmaster ADS_EXT_IRQ(8) | |
481 | * lart LART_IRQ_UCB1200 | |
482 | * omnimeter IRQ_GPIO23 | |
483 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
484 | * simpad IRQ_GPIO_UCB1300_IRQ | |
485 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
486 | * yopy IRQ_GPIO_UCB1200_IRQ | |
487 | */ | |
488 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
489 | { | |
490 | unsigned long mask; | |
491 | ||
492 | mask = probe_irq_on(); | |
cfc73656 IM |
493 | if (!mask) { |
494 | probe_irq_off(mask); | |
05c45ca9 | 495 | return NO_IRQ; |
cfc73656 | 496 | } |
05c45ca9 RK |
497 | |
498 | /* | |
499 | * Enable the ADC interrupt. | |
500 | */ | |
501 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
502 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
503 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
504 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
505 | ||
506 | /* | |
507 | * Cause an ADC interrupt. | |
508 | */ | |
509 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
510 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
511 | ||
512 | /* | |
513 | * Wait for the conversion to complete. | |
514 | */ | |
515 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
516 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
517 | ||
518 | /* | |
519 | * Disable and clear interrupt. | |
520 | */ | |
521 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
522 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
523 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
524 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
525 | ||
526 | /* | |
527 | * Read triggered interrupt. | |
528 | */ | |
529 | return probe_irq_off(mask); | |
530 | } | |
531 | ||
0c55445f | 532 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
533 | { |
534 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
535 | kfree(ucb); | |
536 | } | |
537 | ||
538 | static struct class ucb1x00_class = { | |
539 | .name = "ucb1x00", | |
0c55445f | 540 | .dev_release = ucb1x00_release, |
585f5457 NP |
541 | }; |
542 | ||
05c45ca9 RK |
543 | static int ucb1x00_probe(struct mcp *mcp) |
544 | { | |
2f7510c6 | 545 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 | 546 | struct ucb1x00_driver *drv; |
2f7510c6 | 547 | struct ucb1x00 *ucb; |
05c45ca9 RK |
548 | unsigned int id; |
549 | int ret = -ENODEV; | |
9ca3dc80 | 550 | int temp; |
05c45ca9 | 551 | |
2f7510c6 RK |
552 | /* Tell the platform to deassert the UCB1x00 reset */ |
553 | if (pdata && pdata->reset) | |
554 | pdata->reset(UCB_RST_PROBE); | |
555 | ||
05c45ca9 RK |
556 | mcp_enable(mcp); |
557 | id = mcp_reg_read(mcp, UCB_ID); | |
2b4d9d2b | 558 | mcp_disable(mcp); |
05c45ca9 | 559 | |
65f2e753 RK |
560 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
561 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
2b4d9d2b | 562 | goto out; |
05c45ca9 RK |
563 | } |
564 | ||
dd00cc48 | 565 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
566 | ret = -ENOMEM; |
567 | if (!ucb) | |
2b4d9d2b | 568 | goto out; |
05c45ca9 | 569 | |
f5ae587f | 570 | device_initialize(&ucb->dev); |
0c55445f TJ |
571 | ucb->dev.class = &ucb1x00_class; |
572 | ucb->dev.parent = &mcp->attached_device; | |
65f2e753 | 573 | dev_set_name(&ucb->dev, "ucb1x00"); |
05c45ca9 RK |
574 | |
575 | spin_lock_init(&ucb->lock); | |
576 | spin_lock_init(&ucb->io_lock); | |
cae15476 | 577 | mutex_init(&ucb->adc_mutex); |
05c45ca9 | 578 | |
65f2e753 | 579 | ucb->id = id; |
05c45ca9 | 580 | ucb->mcp = mcp; |
f5ae587f RK |
581 | |
582 | ret = device_add(&ucb->dev); | |
583 | if (ret) | |
584 | goto err_dev_add; | |
585 | ||
2b4d9d2b | 586 | ucb1x00_enable(ucb); |
05c45ca9 | 587 | ucb->irq = ucb1x00_detect_irq(ucb); |
2b4d9d2b | 588 | ucb1x00_disable(ucb); |
05c45ca9 | 589 | if (ucb->irq == NO_IRQ) { |
f5ae587f | 590 | dev_err(&ucb->dev, "IRQ probe failed\n"); |
05c45ca9 | 591 | ret = -ENODEV; |
f5ae587f | 592 | goto err_no_irq; |
05c45ca9 RK |
593 | } |
594 | ||
9ca3dc80 | 595 | ucb->gpio.base = -1; |
abe06082 | 596 | if (pdata && pdata->gpio_base) { |
9ca3dc80 | 597 | ucb->gpio.label = dev_name(&ucb->dev); |
7655b2ac RK |
598 | ucb->gpio.dev = &ucb->dev; |
599 | ucb->gpio.owner = THIS_MODULE; | |
abe06082 | 600 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
601 | ucb->gpio.ngpio = 10; |
602 | ucb->gpio.set = ucb1x00_gpio_set; | |
603 | ucb->gpio.get = ucb1x00_gpio_get; | |
604 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
605 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
606 | ret = gpiochip_add(&ucb->gpio); | |
607 | if (ret) | |
f5ae587f | 608 | goto err_gpio_add; |
9ca3dc80 TK |
609 | } else |
610 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
611 | ||
dace1453 | 612 | ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING, |
65f2e753 | 613 | "UCB1x00", ucb); |
05c45ca9 | 614 | if (ret) { |
f5ae587f | 615 | dev_err(&ucb->dev, "ucb1x00: unable to grab irq%d: %d\n", |
65f2e753 | 616 | ucb->irq, ret); |
f5ae587f | 617 | goto err_irq; |
05c45ca9 RK |
618 | } |
619 | ||
05c45ca9 RK |
620 | mcp_set_drvdata(mcp, ucb); |
621 | ||
05c45ca9 | 622 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 623 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 624 | list_add_tail(&ucb->node, &ucb1x00_devices); |
05c45ca9 RK |
625 | list_for_each_entry(drv, &ucb1x00_drivers, node) { |
626 | ucb1x00_add_dev(ucb, drv); | |
627 | } | |
a621aaed | 628 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 629 | |
2f7510c6 | 630 | return ret; |
05c45ca9 RK |
631 | |
632 | err_irq: | |
9ca3dc80 TK |
633 | if (ucb->gpio.base != -1) |
634 | temp = gpiochip_remove(&ucb->gpio); | |
f5ae587f RK |
635 | err_gpio_add: |
636 | err_no_irq: | |
637 | device_del(&ucb->dev); | |
638 | err_dev_add: | |
639 | put_device(&ucb->dev); | |
05c45ca9 | 640 | out: |
2f7510c6 RK |
641 | if (pdata && pdata->reset) |
642 | pdata->reset(UCB_RST_PROBE_FAIL); | |
05c45ca9 RK |
643 | return ret; |
644 | } | |
645 | ||
646 | static void ucb1x00_remove(struct mcp *mcp) | |
647 | { | |
2f7510c6 | 648 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 RK |
649 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); |
650 | struct list_head *l, *n; | |
9ca3dc80 | 651 | int ret; |
05c45ca9 | 652 | |
a621aaed | 653 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
654 | list_del(&ucb->node); |
655 | list_for_each_safe(l, n, &ucb->devs) { | |
656 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
657 | ucb1x00_remove_dev(dev); | |
658 | } | |
a621aaed | 659 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 660 | |
9ca3dc80 TK |
661 | if (ucb->gpio.base != -1) { |
662 | ret = gpiochip_remove(&ucb->gpio); | |
663 | if (ret) | |
664 | dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret); | |
665 | } | |
666 | ||
05c45ca9 | 667 | free_irq(ucb->irq, ucb); |
0c55445f | 668 | device_unregister(&ucb->dev); |
2f7510c6 RK |
669 | |
670 | if (pdata && pdata->reset) | |
671 | pdata->reset(UCB_RST_REMOVE); | |
05c45ca9 RK |
672 | } |
673 | ||
05c45ca9 RK |
674 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
675 | { | |
676 | struct ucb1x00 *ucb; | |
677 | ||
678 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 679 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 680 | list_add_tail(&drv->node, &ucb1x00_drivers); |
05c45ca9 RK |
681 | list_for_each_entry(ucb, &ucb1x00_devices, node) { |
682 | ucb1x00_add_dev(ucb, drv); | |
683 | } | |
a621aaed | 684 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
685 | return 0; |
686 | } | |
687 | ||
688 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
689 | { | |
690 | struct list_head *n, *l; | |
691 | ||
a621aaed | 692 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
693 | list_del(&drv->node); |
694 | list_for_each_safe(l, n, &drv->devs) { | |
695 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
696 | ucb1x00_remove_dev(dev); | |
697 | } | |
a621aaed | 698 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
699 | } |
700 | ||
5a09b712 | 701 | static int ucb1x00_suspend(struct device *dev) |
05c45ca9 | 702 | { |
5a09b712 RK |
703 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
704 | struct ucb1x00_dev *udev; | |
05c45ca9 | 705 | |
a621aaed | 706 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
707 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
708 | if (udev->drv->suspend) | |
709 | udev->drv->suspend(udev); | |
05c45ca9 | 710 | } |
a621aaed | 711 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
712 | return 0; |
713 | } | |
714 | ||
5a09b712 | 715 | static int ucb1x00_resume(struct device *dev) |
05c45ca9 | 716 | { |
5a09b712 RK |
717 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
718 | struct ucb1x00_dev *udev; | |
05c45ca9 | 719 | |
ed442b67 | 720 | ucb1x00_enable(ucb); |
2e95e51e | 721 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
9ca3dc80 | 722 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 723 | ucb1x00_disable(ucb); |
a621aaed | 724 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
725 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
726 | if (udev->drv->resume) | |
727 | udev->drv->resume(udev); | |
05c45ca9 | 728 | } |
a621aaed | 729 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
730 | return 0; |
731 | } | |
732 | ||
5a09b712 RK |
733 | static const struct dev_pm_ops ucb1x00_pm_ops = { |
734 | SET_SYSTEM_SLEEP_PM_OPS(ucb1x00_suspend, ucb1x00_resume) | |
735 | }; | |
736 | ||
05c45ca9 RK |
737 | static struct mcp_driver ucb1x00_driver = { |
738 | .drv = { | |
739 | .name = "ucb1x00", | |
ddb1e04a | 740 | .owner = THIS_MODULE, |
5a09b712 | 741 | .pm = &ucb1x00_pm_ops, |
05c45ca9 RK |
742 | }, |
743 | .probe = ucb1x00_probe, | |
744 | .remove = ucb1x00_remove, | |
05c45ca9 RK |
745 | }; |
746 | ||
747 | static int __init ucb1x00_init(void) | |
748 | { | |
749 | int ret = class_register(&ucb1x00_class); | |
750 | if (ret == 0) { | |
751 | ret = mcp_driver_register(&ucb1x00_driver); | |
752 | if (ret) | |
753 | class_unregister(&ucb1x00_class); | |
754 | } | |
755 | return ret; | |
756 | } | |
757 | ||
758 | static void __exit ucb1x00_exit(void) | |
759 | { | |
760 | mcp_driver_unregister(&ucb1x00_driver); | |
761 | class_unregister(&ucb1x00_class); | |
762 | } | |
763 | ||
764 | module_init(ucb1x00_init); | |
765 | module_exit(ucb1x00_exit); | |
766 | ||
05c45ca9 RK |
767 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
768 | EXPORT_SYMBOL(ucb1x00_io_write); | |
769 | EXPORT_SYMBOL(ucb1x00_io_read); | |
770 | ||
771 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
772 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
773 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
774 | ||
775 | EXPORT_SYMBOL(ucb1x00_hook_irq); | |
776 | EXPORT_SYMBOL(ucb1x00_free_irq); | |
777 | EXPORT_SYMBOL(ucb1x00_enable_irq); | |
778 | EXPORT_SYMBOL(ucb1x00_disable_irq); | |
779 | ||
780 | EXPORT_SYMBOL(ucb1x00_register_driver); | |
781 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
782 | ||
ddb1e04a | 783 | MODULE_ALIAS("mcp:ucb1x00"); |
05c45ca9 RK |
784 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
785 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
786 | MODULE_LICENSE("GPL"); |