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84a14ae8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
05c45ca9 RK |
2 | /* |
3 | * linux/drivers/mfd/ucb1x00-core.c | |
4 | * | |
5 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
6 | * | |
05c45ca9 RK |
7 | * The UCB1x00 core driver provides basic services for handling IO, |
8 | * the ADC, interrupts, and accessing registers. It is designed | |
9 | * such that everything goes through this layer, thereby providing | |
10 | * a consistent locking methodology, as well as allowing the drivers | |
11 | * to be used on other non-MCP-enabled hardware platforms. | |
12 | * | |
13 | * Note that all locks are private to this file. Nothing else may | |
14 | * touch them. | |
15 | */ | |
05c45ca9 RK |
16 | #include <linux/module.h> |
17 | #include <linux/kernel.h> | |
d43c36dc | 18 | #include <linux/sched.h> |
05c45ca9 RK |
19 | #include <linux/slab.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/interrupt.h> | |
a3364409 | 23 | #include <linux/irq.h> |
05c45ca9 | 24 | #include <linux/device.h> |
a621aaed | 25 | #include <linux/mutex.h> |
c8602edf | 26 | #include <linux/mfd/ucb1x00.h> |
5a09b712 | 27 | #include <linux/pm.h> |
7d94352e | 28 | #include <linux/gpio/driver.h> |
05c45ca9 | 29 | |
a621aaed | 30 | static DEFINE_MUTEX(ucb1x00_mutex); |
05c45ca9 RK |
31 | static LIST_HEAD(ucb1x00_drivers); |
32 | static LIST_HEAD(ucb1x00_devices); | |
33 | ||
34 | /** | |
35 | * ucb1x00_io_set_dir - set IO direction | |
36 | * @ucb: UCB1x00 structure describing chip | |
37 | * @in: bitfield of IO pins to be set as inputs | |
38 | * @out: bitfield of IO pins to be set as outputs | |
39 | * | |
40 | * Set the IO direction of the ten general purpose IO pins on | |
41 | * the UCB1x00 chip. The @in bitfield has priority over the | |
42 | * @out bitfield, in that if you specify a pin as both input | |
43 | * and output, it will end up as an input. | |
44 | * | |
45 | * ucb1x00_enable must have been called to enable the comms | |
46 | * before using this function. | |
47 | * | |
48 | * This function takes a spinlock, disabling interrupts. | |
49 | */ | |
50 | void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) | |
51 | { | |
52 | unsigned long flags; | |
53 | ||
54 | spin_lock_irqsave(&ucb->io_lock, flags); | |
55 | ucb->io_dir |= out; | |
56 | ucb->io_dir &= ~in; | |
57 | ||
58 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
59 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
60 | } | |
61 | ||
62 | /** | |
63 | * ucb1x00_io_write - set or clear IO outputs | |
64 | * @ucb: UCB1x00 structure describing chip | |
65 | * @set: bitfield of IO pins to set to logic '1' | |
66 | * @clear: bitfield of IO pins to set to logic '0' | |
67 | * | |
68 | * Set the IO output state of the specified IO pins. The value | |
69 | * is retained if the pins are subsequently configured as inputs. | |
70 | * The @clear bitfield has priority over the @set bitfield - | |
71 | * outputs will be cleared. | |
72 | * | |
73 | * ucb1x00_enable must have been called to enable the comms | |
74 | * before using this function. | |
75 | * | |
76 | * This function takes a spinlock, disabling interrupts. | |
77 | */ | |
78 | void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) | |
79 | { | |
80 | unsigned long flags; | |
81 | ||
82 | spin_lock_irqsave(&ucb->io_lock, flags); | |
83 | ucb->io_out |= set; | |
84 | ucb->io_out &= ~clear; | |
85 | ||
86 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
87 | spin_unlock_irqrestore(&ucb->io_lock, flags); | |
88 | } | |
89 | ||
90 | /** | |
91 | * ucb1x00_io_read - read the current state of the IO pins | |
92 | * @ucb: UCB1x00 structure describing chip | |
93 | * | |
94 | * Return a bitfield describing the logic state of the ten | |
95 | * general purpose IO pins. | |
96 | * | |
97 | * ucb1x00_enable must have been called to enable the comms | |
98 | * before using this function. | |
99 | * | |
cae15476 | 100 | * This function does not take any mutexes or spinlocks. |
05c45ca9 RK |
101 | */ |
102 | unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) | |
103 | { | |
104 | return ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
105 | } | |
106 | ||
9ca3dc80 TK |
107 | static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
108 | { | |
7d94352e | 109 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
9ca3dc80 TK |
110 | unsigned long flags; |
111 | ||
112 | spin_lock_irqsave(&ucb->io_lock, flags); | |
113 | if (value) | |
114 | ucb->io_out |= 1 << offset; | |
115 | else | |
116 | ucb->io_out &= ~(1 << offset); | |
117 | ||
ed442b67 | 118 | ucb1x00_enable(ucb); |
9ca3dc80 | 119 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
ed442b67 | 120 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
121 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
122 | } | |
123 | ||
124 | static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) | |
125 | { | |
7d94352e | 126 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
ed442b67 RK |
127 | unsigned val; |
128 | ||
129 | ucb1x00_enable(ucb); | |
130 | val = ucb1x00_reg_read(ucb, UCB_IO_DATA); | |
131 | ucb1x00_disable(ucb); | |
132 | ||
0c7f3f92 | 133 | return !!(val & (1 << offset)); |
9ca3dc80 TK |
134 | } |
135 | ||
136 | static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
137 | { | |
7d94352e | 138 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
9ca3dc80 TK |
139 | unsigned long flags; |
140 | ||
141 | spin_lock_irqsave(&ucb->io_lock, flags); | |
142 | ucb->io_dir &= ~(1 << offset); | |
ed442b67 | 143 | ucb1x00_enable(ucb); |
9ca3dc80 | 144 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
ed442b67 | 145 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
146 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset | |
152 | , int value) | |
153 | { | |
7d94352e | 154 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
9ca3dc80 | 155 | unsigned long flags; |
c23bb602 | 156 | unsigned old, mask = 1 << offset; |
9ca3dc80 TK |
157 | |
158 | spin_lock_irqsave(&ucb->io_lock, flags); | |
c23bb602 | 159 | old = ucb->io_out; |
9ca3dc80 | 160 | if (value) |
c23bb602 | 161 | ucb->io_out |= mask; |
9ca3dc80 | 162 | else |
c23bb602 RK |
163 | ucb->io_out &= ~mask; |
164 | ||
ed442b67 | 165 | ucb1x00_enable(ucb); |
c23bb602 RK |
166 | if (old != ucb->io_out) |
167 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); | |
168 | ||
169 | if (!(ucb->io_dir & mask)) { | |
170 | ucb->io_dir |= mask; | |
171 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); | |
172 | } | |
ed442b67 | 173 | ucb1x00_disable(ucb); |
9ca3dc80 TK |
174 | spin_unlock_irqrestore(&ucb->io_lock, flags); |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
a3364409 RK |
179 | static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset) |
180 | { | |
7d94352e | 181 | struct ucb1x00 *ucb = gpiochip_get_data(chip); |
a3364409 RK |
182 | |
183 | return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO; | |
184 | } | |
185 | ||
05c45ca9 RK |
186 | /* |
187 | * UCB1300 data sheet says we must: | |
188 | * 1. enable ADC => 5us (including reference startup time) | |
189 | * 2. select input => 51*tsibclk => 4.3us | |
190 | * 3. start conversion => 102*tsibclk => 8.5us | |
191 | * (tsibclk = 1/11981000) | |
192 | * Period between SIB 128-bit frames = 10.7us | |
193 | */ | |
194 | ||
195 | /** | |
196 | * ucb1x00_adc_enable - enable the ADC converter | |
197 | * @ucb: UCB1x00 structure describing chip | |
198 | * | |
199 | * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. | |
200 | * Any code wishing to use the ADC converter must call this | |
201 | * function prior to using it. | |
202 | * | |
cae15476 | 203 | * This function takes the ADC mutex to prevent two or more |
05c45ca9 RK |
204 | * concurrent uses, and therefore may sleep. As a result, it |
205 | * can only be called from process context, not interrupt | |
206 | * context. | |
207 | * | |
208 | * You should release the ADC as soon as possible using | |
209 | * ucb1x00_adc_disable. | |
210 | */ | |
211 | void ucb1x00_adc_enable(struct ucb1x00 *ucb) | |
212 | { | |
cae15476 | 213 | mutex_lock(&ucb->adc_mutex); |
05c45ca9 RK |
214 | |
215 | ucb->adc_cr |= UCB_ADC_ENA; | |
216 | ||
217 | ucb1x00_enable(ucb); | |
218 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
219 | } | |
220 | ||
221 | /** | |
222 | * ucb1x00_adc_read - read the specified ADC channel | |
223 | * @ucb: UCB1x00 structure describing chip | |
224 | * @adc_channel: ADC channel mask | |
225 | * @sync: wait for syncronisation pulse. | |
226 | * | |
227 | * Start an ADC conversion and wait for the result. Note that | |
228 | * synchronised ADC conversions (via the ADCSYNC pin) must wait | |
229 | * until the trigger is asserted and the conversion is finished. | |
230 | * | |
231 | * This function currently spins waiting for the conversion to | |
232 | * complete (2 frames max without sync). | |
233 | * | |
234 | * If called for a synchronised ADC conversion, it may sleep | |
cae15476 | 235 | * with the ADC mutex held. |
05c45ca9 RK |
236 | */ |
237 | unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) | |
238 | { | |
239 | unsigned int val; | |
240 | ||
241 | if (sync) | |
242 | adc_channel |= UCB_ADC_SYNC_ENA; | |
243 | ||
244 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); | |
245 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); | |
246 | ||
247 | for (;;) { | |
248 | val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); | |
249 | if (val & UCB_ADC_DAT_VAL) | |
250 | break; | |
251 | /* yield to other processes */ | |
252 | set_current_state(TASK_INTERRUPTIBLE); | |
253 | schedule_timeout(1); | |
254 | } | |
255 | ||
256 | return UCB_ADC_DAT(val); | |
257 | } | |
258 | ||
259 | /** | |
260 | * ucb1x00_adc_disable - disable the ADC converter | |
261 | * @ucb: UCB1x00 structure describing chip | |
262 | * | |
cae15476 | 263 | * Disable the ADC converter and release the ADC mutex. |
05c45ca9 RK |
264 | */ |
265 | void ucb1x00_adc_disable(struct ucb1x00 *ucb) | |
266 | { | |
267 | ucb->adc_cr &= ~UCB_ADC_ENA; | |
268 | ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); | |
269 | ucb1x00_disable(ucb); | |
270 | ||
cae15476 | 271 | mutex_unlock(&ucb->adc_mutex); |
05c45ca9 RK |
272 | } |
273 | ||
274 | /* | |
275 | * UCB1x00 Interrupt handling. | |
276 | * | |
277 | * The UCB1x00 can generate interrupts when the SIBCLK is stopped. | |
278 | * Since we need to read an internal register, we must re-enable | |
279 | * SIBCLK to talk to the chip. We leave the clock running until | |
280 | * we have finished processing all interrupts from the chip. | |
281 | */ | |
bd0b9ac4 | 282 | static void ucb1x00_irq(struct irq_desc *desc) |
05c45ca9 | 283 | { |
a3364409 | 284 | struct ucb1x00 *ucb = irq_desc_get_handler_data(desc); |
05c45ca9 RK |
285 | unsigned int isr, i; |
286 | ||
287 | ucb1x00_enable(ucb); | |
288 | isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); | |
289 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); | |
290 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
291 | ||
0d674d93 | 292 | for (i = 0; i < 16 && isr; i++, isr >>= 1) |
a3364409 RK |
293 | if (isr & 1) |
294 | generic_handle_irq(ucb->irq_base + i); | |
05c45ca9 | 295 | ucb1x00_disable(ucb); |
05c45ca9 RK |
296 | } |
297 | ||
a3364409 | 298 | static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask) |
05c45ca9 | 299 | { |
a3364409 RK |
300 | ucb1x00_enable(ucb); |
301 | if (ucb->irq_ris_enbl & mask) | |
302 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
303 | ucb->irq_mask); | |
304 | if (ucb->irq_fal_enbl & mask) | |
305 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
306 | ucb->irq_mask); | |
307 | ucb1x00_disable(ucb); | |
05c45ca9 RK |
308 | } |
309 | ||
a3364409 | 310 | static void ucb1x00_irq_noop(struct irq_data *data) |
05c45ca9 | 311 | { |
05c45ca9 RK |
312 | } |
313 | ||
a3364409 | 314 | static void ucb1x00_irq_mask(struct irq_data *data) |
05c45ca9 | 315 | { |
a3364409 RK |
316 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
317 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 318 | |
a3364409 RK |
319 | raw_spin_lock(&ucb->irq_lock); |
320 | ucb->irq_mask &= ~mask; | |
321 | ucb1x00_irq_update(ucb, mask); | |
322 | raw_spin_unlock(&ucb->irq_lock); | |
05c45ca9 RK |
323 | } |
324 | ||
a3364409 | 325 | static void ucb1x00_irq_unmask(struct irq_data *data) |
05c45ca9 | 326 | { |
a3364409 RK |
327 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); |
328 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 329 | |
a3364409 RK |
330 | raw_spin_lock(&ucb->irq_lock); |
331 | ucb->irq_mask |= mask; | |
332 | ucb1x00_irq_update(ucb, mask); | |
333 | raw_spin_unlock(&ucb->irq_lock); | |
334 | } | |
05c45ca9 | 335 | |
a3364409 RK |
336 | static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type) |
337 | { | |
338 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); | |
339 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
05c45ca9 | 340 | |
a3364409 RK |
341 | raw_spin_lock(&ucb->irq_lock); |
342 | if (type & IRQ_TYPE_EDGE_RISING) | |
343 | ucb->irq_ris_enbl |= mask; | |
344 | else | |
345 | ucb->irq_ris_enbl &= ~mask; | |
05c45ca9 | 346 | |
a3364409 RK |
347 | if (type & IRQ_TYPE_EDGE_FALLING) |
348 | ucb->irq_fal_enbl |= mask; | |
349 | else | |
350 | ucb->irq_fal_enbl &= ~mask; | |
351 | if (ucb->irq_mask & mask) { | |
352 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
353 | ucb->irq_mask); | |
354 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
355 | ucb->irq_mask); | |
05c45ca9 | 356 | } |
a3364409 | 357 | raw_spin_unlock(&ucb->irq_lock); |
05c45ca9 | 358 | |
a3364409 | 359 | return 0; |
05c45ca9 RK |
360 | } |
361 | ||
33237616 RK |
362 | static int ucb1x00_irq_set_wake(struct irq_data *data, unsigned int on) |
363 | { | |
364 | struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); | |
365 | struct ucb1x00_plat_data *pdata = ucb->mcp->attached_device.platform_data; | |
366 | unsigned mask = 1 << (data->irq - ucb->irq_base); | |
367 | ||
368 | if (!pdata || !pdata->can_wakeup) | |
369 | return -EINVAL; | |
370 | ||
371 | raw_spin_lock(&ucb->irq_lock); | |
372 | if (on) | |
373 | ucb->irq_wake |= mask; | |
374 | else | |
375 | ucb->irq_wake &= ~mask; | |
376 | raw_spin_unlock(&ucb->irq_lock); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
a3364409 RK |
381 | static struct irq_chip ucb1x00_irqchip = { |
382 | .name = "ucb1x00", | |
383 | .irq_ack = ucb1x00_irq_noop, | |
384 | .irq_mask = ucb1x00_irq_mask, | |
385 | .irq_unmask = ucb1x00_irq_unmask, | |
386 | .irq_set_type = ucb1x00_irq_set_type, | |
33237616 | 387 | .irq_set_wake = ucb1x00_irq_set_wake, |
a3364409 RK |
388 | }; |
389 | ||
05c45ca9 RK |
390 | static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) |
391 | { | |
392 | struct ucb1x00_dev *dev; | |
02a0bf6e | 393 | int ret; |
05c45ca9 RK |
394 | |
395 | dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL); | |
02a0bf6e LJ |
396 | if (!dev) |
397 | return -ENOMEM; | |
398 | ||
399 | dev->ucb = ucb; | |
400 | dev->drv = drv; | |
401 | ||
402 | ret = drv->add(dev); | |
403 | if (ret) { | |
404 | kfree(dev); | |
405 | return ret; | |
05c45ca9 | 406 | } |
02a0bf6e LJ |
407 | |
408 | list_add_tail(&dev->dev_node, &ucb->devs); | |
409 | list_add_tail(&dev->drv_node, &drv->devs); | |
410 | ||
05c45ca9 RK |
411 | return ret; |
412 | } | |
413 | ||
414 | static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) | |
415 | { | |
416 | dev->drv->remove(dev); | |
417 | list_del(&dev->dev_node); | |
418 | list_del(&dev->drv_node); | |
419 | kfree(dev); | |
420 | } | |
421 | ||
422 | /* | |
423 | * Try to probe our interrupt, rather than relying on lots of | |
424 | * hard-coded machine dependencies. For reference, the expected | |
425 | * IRQ mappings are: | |
426 | * | |
427 | * Machine Default IRQ | |
428 | * adsbitsy IRQ_GPCIN4 | |
429 | * cerf IRQ_GPIO_UCB1200_IRQ | |
430 | * flexanet IRQ_GPIO_GUI | |
431 | * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ | |
432 | * graphicsclient ADS_EXT_IRQ(8) | |
433 | * graphicsmaster ADS_EXT_IRQ(8) | |
434 | * lart LART_IRQ_UCB1200 | |
435 | * omnimeter IRQ_GPIO23 | |
436 | * pfs168 IRQ_GPIO_UCB1300_IRQ | |
437 | * simpad IRQ_GPIO_UCB1300_IRQ | |
438 | * shannon SHANNON_IRQ_GPIO_IRQ_CODEC | |
439 | * yopy IRQ_GPIO_UCB1200_IRQ | |
440 | */ | |
441 | static int ucb1x00_detect_irq(struct ucb1x00 *ucb) | |
442 | { | |
443 | unsigned long mask; | |
444 | ||
445 | mask = probe_irq_on(); | |
05c45ca9 RK |
446 | |
447 | /* | |
448 | * Enable the ADC interrupt. | |
449 | */ | |
450 | ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); | |
451 | ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); | |
452 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
453 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
454 | ||
455 | /* | |
456 | * Cause an ADC interrupt. | |
457 | */ | |
458 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); | |
459 | ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); | |
460 | ||
461 | /* | |
462 | * Wait for the conversion to complete. | |
463 | */ | |
464 | while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); | |
465 | ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); | |
466 | ||
467 | /* | |
468 | * Disable and clear interrupt. | |
469 | */ | |
470 | ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); | |
471 | ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); | |
472 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); | |
473 | ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); | |
474 | ||
475 | /* | |
476 | * Read triggered interrupt. | |
477 | */ | |
478 | return probe_irq_off(mask); | |
479 | } | |
480 | ||
0c55445f | 481 | static void ucb1x00_release(struct device *dev) |
585f5457 NP |
482 | { |
483 | struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); | |
484 | kfree(ucb); | |
485 | } | |
486 | ||
487 | static struct class ucb1x00_class = { | |
488 | .name = "ucb1x00", | |
0c55445f | 489 | .dev_release = ucb1x00_release, |
585f5457 NP |
490 | }; |
491 | ||
05c45ca9 RK |
492 | static int ucb1x00_probe(struct mcp *mcp) |
493 | { | |
2f7510c6 | 494 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 | 495 | struct ucb1x00_driver *drv; |
2f7510c6 | 496 | struct ucb1x00 *ucb; |
a3364409 | 497 | unsigned id, i, irq_base; |
05c45ca9 RK |
498 | int ret = -ENODEV; |
499 | ||
2f7510c6 RK |
500 | /* Tell the platform to deassert the UCB1x00 reset */ |
501 | if (pdata && pdata->reset) | |
502 | pdata->reset(UCB_RST_PROBE); | |
503 | ||
05c45ca9 RK |
504 | mcp_enable(mcp); |
505 | id = mcp_reg_read(mcp, UCB_ID); | |
2b4d9d2b | 506 | mcp_disable(mcp); |
05c45ca9 | 507 | |
65f2e753 RK |
508 | if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { |
509 | printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); | |
2b4d9d2b | 510 | goto out; |
05c45ca9 RK |
511 | } |
512 | ||
dd00cc48 | 513 | ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL); |
05c45ca9 RK |
514 | ret = -ENOMEM; |
515 | if (!ucb) | |
2b4d9d2b | 516 | goto out; |
05c45ca9 | 517 | |
f5ae587f | 518 | device_initialize(&ucb->dev); |
0c55445f TJ |
519 | ucb->dev.class = &ucb1x00_class; |
520 | ucb->dev.parent = &mcp->attached_device; | |
65f2e753 | 521 | dev_set_name(&ucb->dev, "ucb1x00"); |
05c45ca9 | 522 | |
a3364409 | 523 | raw_spin_lock_init(&ucb->irq_lock); |
05c45ca9 | 524 | spin_lock_init(&ucb->io_lock); |
cae15476 | 525 | mutex_init(&ucb->adc_mutex); |
05c45ca9 | 526 | |
65f2e753 | 527 | ucb->id = id; |
05c45ca9 | 528 | ucb->mcp = mcp; |
f5ae587f RK |
529 | |
530 | ret = device_add(&ucb->dev); | |
531 | if (ret) | |
532 | goto err_dev_add; | |
533 | ||
2b4d9d2b | 534 | ucb1x00_enable(ucb); |
05c45ca9 | 535 | ucb->irq = ucb1x00_detect_irq(ucb); |
2b4d9d2b | 536 | ucb1x00_disable(ucb); |
b53046cb | 537 | if (!ucb->irq) { |
f5ae587f | 538 | dev_err(&ucb->dev, "IRQ probe failed\n"); |
05c45ca9 | 539 | ret = -ENODEV; |
f5ae587f | 540 | goto err_no_irq; |
05c45ca9 RK |
541 | } |
542 | ||
9ca3dc80 | 543 | ucb->gpio.base = -1; |
a3364409 RK |
544 | irq_base = pdata ? pdata->irq_base : 0; |
545 | ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1); | |
546 | if (ucb->irq_base < 0) { | |
547 | dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n", | |
548 | ucb->irq_base); | |
18fefda9 | 549 | ret = ucb->irq_base; |
a3364409 RK |
550 | goto err_irq_alloc; |
551 | } | |
552 | ||
553 | for (i = 0; i < 16; i++) { | |
554 | unsigned irq = ucb->irq_base + i; | |
555 | ||
556 | irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq); | |
557 | irq_set_chip_data(irq, ucb); | |
9bd09f34 | 558 | irq_clear_status_flags(irq, IRQ_NOREQUEST); |
a3364409 RK |
559 | } |
560 | ||
561 | irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING); | |
056c0acf | 562 | irq_set_chained_handler_and_data(ucb->irq, ucb1x00_irq, ucb); |
a3364409 | 563 | |
abe06082 | 564 | if (pdata && pdata->gpio_base) { |
9ca3dc80 | 565 | ucb->gpio.label = dev_name(&ucb->dev); |
58383c78 | 566 | ucb->gpio.parent = &ucb->dev; |
7655b2ac | 567 | ucb->gpio.owner = THIS_MODULE; |
abe06082 | 568 | ucb->gpio.base = pdata->gpio_base; |
9ca3dc80 TK |
569 | ucb->gpio.ngpio = 10; |
570 | ucb->gpio.set = ucb1x00_gpio_set; | |
571 | ucb->gpio.get = ucb1x00_gpio_get; | |
572 | ucb->gpio.direction_input = ucb1x00_gpio_direction_input; | |
573 | ucb->gpio.direction_output = ucb1x00_gpio_direction_output; | |
a3364409 | 574 | ucb->gpio.to_irq = ucb1x00_to_irq; |
7d94352e | 575 | ret = gpiochip_add_data(&ucb->gpio, ucb); |
9ca3dc80 | 576 | if (ret) |
f5ae587f | 577 | goto err_gpio_add; |
9ca3dc80 TK |
578 | } else |
579 | dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); | |
580 | ||
05c45ca9 RK |
581 | mcp_set_drvdata(mcp, ucb); |
582 | ||
33237616 RK |
583 | if (pdata) |
584 | device_set_wakeup_capable(&ucb->dev, pdata->can_wakeup); | |
585 | ||
05c45ca9 | 586 | INIT_LIST_HEAD(&ucb->devs); |
a621aaed | 587 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 588 | list_add_tail(&ucb->node, &ucb1x00_devices); |
05c45ca9 RK |
589 | list_for_each_entry(drv, &ucb1x00_drivers, node) { |
590 | ucb1x00_add_dev(ucb, drv); | |
591 | } | |
a621aaed | 592 | mutex_unlock(&ucb1x00_mutex); |
9ca3dc80 | 593 | |
2f7510c6 | 594 | return ret; |
05c45ca9 | 595 | |
f5ae587f | 596 | err_gpio_add: |
a3364409 RK |
597 | irq_set_chained_handler(ucb->irq, NULL); |
598 | err_irq_alloc: | |
599 | if (ucb->irq_base > 0) | |
600 | irq_free_descs(ucb->irq_base, 16); | |
f5ae587f RK |
601 | err_no_irq: |
602 | device_del(&ucb->dev); | |
603 | err_dev_add: | |
604 | put_device(&ucb->dev); | |
05c45ca9 | 605 | out: |
2f7510c6 RK |
606 | if (pdata && pdata->reset) |
607 | pdata->reset(UCB_RST_PROBE_FAIL); | |
05c45ca9 RK |
608 | return ret; |
609 | } | |
610 | ||
611 | static void ucb1x00_remove(struct mcp *mcp) | |
612 | { | |
2f7510c6 | 613 | struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; |
05c45ca9 RK |
614 | struct ucb1x00 *ucb = mcp_get_drvdata(mcp); |
615 | struct list_head *l, *n; | |
616 | ||
a621aaed | 617 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
618 | list_del(&ucb->node); |
619 | list_for_each_safe(l, n, &ucb->devs) { | |
620 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); | |
621 | ucb1x00_remove_dev(dev); | |
622 | } | |
a621aaed | 623 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 | 624 | |
88d5e520 | 625 | if (ucb->gpio.base != -1) |
626 | gpiochip_remove(&ucb->gpio); | |
9ca3dc80 | 627 | |
a3364409 RK |
628 | irq_set_chained_handler(ucb->irq, NULL); |
629 | irq_free_descs(ucb->irq_base, 16); | |
0c55445f | 630 | device_unregister(&ucb->dev); |
2f7510c6 RK |
631 | |
632 | if (pdata && pdata->reset) | |
633 | pdata->reset(UCB_RST_REMOVE); | |
05c45ca9 RK |
634 | } |
635 | ||
05c45ca9 RK |
636 | int ucb1x00_register_driver(struct ucb1x00_driver *drv) |
637 | { | |
638 | struct ucb1x00 *ucb; | |
639 | ||
640 | INIT_LIST_HEAD(&drv->devs); | |
a621aaed | 641 | mutex_lock(&ucb1x00_mutex); |
65b539bb | 642 | list_add_tail(&drv->node, &ucb1x00_drivers); |
05c45ca9 RK |
643 | list_for_each_entry(ucb, &ucb1x00_devices, node) { |
644 | ucb1x00_add_dev(ucb, drv); | |
645 | } | |
a621aaed | 646 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
647 | return 0; |
648 | } | |
649 | ||
650 | void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) | |
651 | { | |
652 | struct list_head *n, *l; | |
653 | ||
a621aaed | 654 | mutex_lock(&ucb1x00_mutex); |
05c45ca9 RK |
655 | list_del(&drv->node); |
656 | list_for_each_safe(l, n, &drv->devs) { | |
657 | struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); | |
658 | ucb1x00_remove_dev(dev); | |
659 | } | |
a621aaed | 660 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
661 | } |
662 | ||
5a09b712 | 663 | static int ucb1x00_suspend(struct device *dev) |
05c45ca9 | 664 | { |
334a41ce | 665 | struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); |
5a09b712 RK |
666 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
667 | struct ucb1x00_dev *udev; | |
05c45ca9 | 668 | |
a621aaed | 669 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
670 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
671 | if (udev->drv->suspend) | |
672 | udev->drv->suspend(udev); | |
05c45ca9 | 673 | } |
a621aaed | 674 | mutex_unlock(&ucb1x00_mutex); |
33237616 RK |
675 | |
676 | if (ucb->irq_wake) { | |
677 | unsigned long flags; | |
678 | ||
679 | raw_spin_lock_irqsave(&ucb->irq_lock, flags); | |
680 | ucb1x00_enable(ucb); | |
681 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
682 | ucb->irq_wake); | |
683 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
684 | ucb->irq_wake); | |
685 | ucb1x00_disable(ucb); | |
686 | raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); | |
687 | ||
688 | enable_irq_wake(ucb->irq); | |
689 | } else if (pdata && pdata->reset) | |
690 | pdata->reset(UCB_RST_SUSPEND); | |
691 | ||
05c45ca9 RK |
692 | return 0; |
693 | } | |
694 | ||
5a09b712 | 695 | static int ucb1x00_resume(struct device *dev) |
05c45ca9 | 696 | { |
334a41ce | 697 | struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); |
5a09b712 RK |
698 | struct ucb1x00 *ucb = dev_get_drvdata(dev); |
699 | struct ucb1x00_dev *udev; | |
05c45ca9 | 700 | |
33237616 RK |
701 | if (!ucb->irq_wake && pdata && pdata->reset) |
702 | pdata->reset(UCB_RST_RESUME); | |
703 | ||
ed442b67 | 704 | ucb1x00_enable(ucb); |
2e95e51e | 705 | ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); |
9ca3dc80 | 706 | ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); |
33237616 RK |
707 | |
708 | if (ucb->irq_wake) { | |
709 | unsigned long flags; | |
710 | ||
711 | raw_spin_lock_irqsave(&ucb->irq_lock, flags); | |
712 | ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & | |
713 | ucb->irq_mask); | |
714 | ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & | |
715 | ucb->irq_mask); | |
716 | raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); | |
717 | ||
718 | disable_irq_wake(ucb->irq); | |
719 | } | |
ed442b67 | 720 | ucb1x00_disable(ucb); |
33237616 | 721 | |
a621aaed | 722 | mutex_lock(&ucb1x00_mutex); |
5a09b712 RK |
723 | list_for_each_entry(udev, &ucb->devs, dev_node) { |
724 | if (udev->drv->resume) | |
725 | udev->drv->resume(udev); | |
05c45ca9 | 726 | } |
a621aaed | 727 | mutex_unlock(&ucb1x00_mutex); |
05c45ca9 RK |
728 | return 0; |
729 | } | |
730 | ||
03bf96cf PC |
731 | static DEFINE_SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops, |
732 | ucb1x00_suspend, ucb1x00_resume); | |
5a09b712 | 733 | |
05c45ca9 RK |
734 | static struct mcp_driver ucb1x00_driver = { |
735 | .drv = { | |
736 | .name = "ucb1x00", | |
ddb1e04a | 737 | .owner = THIS_MODULE, |
03bf96cf | 738 | .pm = pm_sleep_ptr(&ucb1x00_pm_ops), |
05c45ca9 RK |
739 | }, |
740 | .probe = ucb1x00_probe, | |
741 | .remove = ucb1x00_remove, | |
05c45ca9 RK |
742 | }; |
743 | ||
744 | static int __init ucb1x00_init(void) | |
745 | { | |
746 | int ret = class_register(&ucb1x00_class); | |
747 | if (ret == 0) { | |
748 | ret = mcp_driver_register(&ucb1x00_driver); | |
749 | if (ret) | |
750 | class_unregister(&ucb1x00_class); | |
751 | } | |
752 | return ret; | |
753 | } | |
754 | ||
755 | static void __exit ucb1x00_exit(void) | |
756 | { | |
757 | mcp_driver_unregister(&ucb1x00_driver); | |
758 | class_unregister(&ucb1x00_class); | |
759 | } | |
760 | ||
761 | module_init(ucb1x00_init); | |
762 | module_exit(ucb1x00_exit); | |
763 | ||
05c45ca9 RK |
764 | EXPORT_SYMBOL(ucb1x00_io_set_dir); |
765 | EXPORT_SYMBOL(ucb1x00_io_write); | |
766 | EXPORT_SYMBOL(ucb1x00_io_read); | |
767 | ||
768 | EXPORT_SYMBOL(ucb1x00_adc_enable); | |
769 | EXPORT_SYMBOL(ucb1x00_adc_read); | |
770 | EXPORT_SYMBOL(ucb1x00_adc_disable); | |
771 | ||
05c45ca9 RK |
772 | EXPORT_SYMBOL(ucb1x00_register_driver); |
773 | EXPORT_SYMBOL(ucb1x00_unregister_driver); | |
774 | ||
ddb1e04a | 775 | MODULE_ALIAS("mcp:ucb1x00"); |
05c45ca9 RK |
776 | MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); |
777 | MODULE_DESCRIPTION("UCB1x00 core driver"); | |
778 | MODULE_LICENSE("GPL"); |