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Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[linux-2.6-block.git] / drivers / mfd / twl6040.c
CommitLineData
2b27bdcc 1// SPDX-License-Identifier: GPL-2.0-only
f19b2823
MLC		 2/*
3 * MFD driver for TWL6040 audio device
4 *
5 * Authors: Misael Lopez Cruz <misael.lopez@ti.com>
6 * Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 *
9 * Copyright: (C) 2011 Texas Instruments, Inc.
f19b2823
MLC		 10 */
11
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/slab.h>
15#include <linux/kernel.h>
5af7df6b 16#include <linux/err.h>
f19b2823 17#include <linux/platform_device.h>
37e13cec 18#include <linux/of.h>
3c92699a 19#include <linux/gpio/consumer.h>
f19b2823 20#include <linux/delay.h>
8eaeb939
PU		 21#include <linux/i2c.h>
22#include <linux/regmap.h>
f19b2823
MLC		 23#include <linux/mfd/core.h>
24#include <linux/mfd/twl6040.h>
5af7df6b 25#include <linux/regulator/consumer.h>
f19b2823 26
31b402e3 27#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
5af7df6b 28#define TWL6040_NUM_SUPPLIES (2)
31b402e3 29
de1e23f8 30static const struct reg_default twl6040_defaults[] = {
c7f9129d
PU		 31 { 0x01, 0x4B }, /* REG_ASICID (ro) */
32 { 0x02, 0x00 }, /* REG_ASICREV (ro) */
33 { 0x03, 0x00 }, /* REG_INTID */
34 { 0x04, 0x00 }, /* REG_INTMR */
35 { 0x05, 0x00 }, /* REG_NCPCTRL */
36 { 0x06, 0x00 }, /* REG_LDOCTL */
37 { 0x07, 0x60 }, /* REG_HPPLLCTL */
38 { 0x08, 0x00 }, /* REG_LPPLLCTL */
39 { 0x09, 0x4A }, /* REG_LPPLLDIV */
40 { 0x0A, 0x00 }, /* REG_AMICBCTL */
41 { 0x0B, 0x00 }, /* REG_DMICBCTL */
42 { 0x0C, 0x00 }, /* REG_MICLCTL */
43 { 0x0D, 0x00 }, /* REG_MICRCTL */
44 { 0x0E, 0x00 }, /* REG_MICGAIN */
45 { 0x0F, 0x1B }, /* REG_LINEGAIN */
46 { 0x10, 0x00 }, /* REG_HSLCTL */
47 { 0x11, 0x00 }, /* REG_HSRCTL */
48 { 0x12, 0x00 }, /* REG_HSGAIN */
49 { 0x13, 0x00 }, /* REG_EARCTL */
50 { 0x14, 0x00 }, /* REG_HFLCTL */
51 { 0x15, 0x00 }, /* REG_HFLGAIN */
52 { 0x16, 0x00 }, /* REG_HFRCTL */
53 { 0x17, 0x00 }, /* REG_HFRGAIN */
54 { 0x18, 0x00 }, /* REG_VIBCTLL */
55 { 0x19, 0x00 }, /* REG_VIBDATL */
56 { 0x1A, 0x00 }, /* REG_VIBCTLR */
57 { 0x1B, 0x00 }, /* REG_VIBDATR */
58 { 0x1C, 0x00 }, /* REG_HKCTL1 */
59 { 0x1D, 0x00 }, /* REG_HKCTL2 */
60 { 0x1E, 0x00 }, /* REG_GPOCTL */
61 { 0x1F, 0x00 }, /* REG_ALB */
62 { 0x20, 0x00 }, /* REG_DLB */
63 /* 0x28, REG_TRIM1 */
64 /* 0x29, REG_TRIM2 */
65 /* 0x2A, REG_TRIM3 */
66 /* 0x2B, REG_HSOTRIM */
67 /* 0x2C, REG_HFOTRIM */
68 { 0x2D, 0x08 }, /* REG_ACCCTL */
69 { 0x2E, 0x00 }, /* REG_STATUS (ro) */
70};
71
8019ff6c 72static struct reg_sequence twl6040_patch[] = {
11e38e11
PU		 73 /*
74 * Select I2C bus access to dual access registers
75 * Interrupt register is cleared on read
76 * Select fast mode for i2c (400KHz)
77 */
78 { TWL6040_REG_ACCCTL,
79 TWL6040_I2CSEL | TWL6040_INTCLRMODE | TWL6040_I2CMODE(1) },
c7f9129d
PU		 80};
81
82
85e9b13c 83static bool twl6040_has_vibra(struct device_node *parent)
ca2cad6a 84{
85e9b13c
JH		 85 struct device_node *node;
86
87 node = of_get_child_by_name(parent, "vibra");
88 if (node) {
89 of_node_put(node);
ca2cad6a 90 return true;
85e9b13c
JH		 91 }
92
ca2cad6a
SO		 93 return false;
94}
95
f19b2823
MLC		 96int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
97{
98 int ret;
8eaeb939 99 unsigned int val;
f19b2823 100
c6f39257
MB		 101 ret = regmap_read(twl6040->regmap, reg, &val);
102 if (ret < 0)
103 return ret;
f19b2823
MLC		 104
105 return val;
106}
107EXPORT_SYMBOL(twl6040_reg_read);
108
109int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
110{
111 int ret;
112
8eaeb939 113 ret = regmap_write(twl6040->regmap, reg, val);
f19b2823
MLC		 114
115 return ret;
116}
117EXPORT_SYMBOL(twl6040_reg_write);
118
119int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
120{
c600040f 121 return regmap_update_bits(twl6040->regmap, reg, mask, mask);
f19b2823
MLC		 122}
123EXPORT_SYMBOL(twl6040_set_bits);
124
125int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
126{
c600040f 127 return regmap_update_bits(twl6040->regmap, reg, mask, 0);
f19b2823
MLC		 128}
129EXPORT_SYMBOL(twl6040_clear_bits);
130
131/* twl6040 codec manual power-up sequence */
f9be1343 132static int twl6040_power_up_manual(struct twl6040 *twl6040)
f19b2823
MLC		 133{
134 u8 ldoctl, ncpctl, lppllctl;
135 int ret;
136
137 /* enable high-side LDO, reference system and internal oscillator */
138 ldoctl = TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA;
139 ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
140 if (ret)
141 return ret;
142 usleep_range(10000, 10500);
143
144 /* enable negative charge pump */
145 ncpctl = TWL6040_NCPENA;
146 ret = twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
147 if (ret)
148 goto ncp_err;
149 usleep_range(1000, 1500);
150
151 /* enable low-side LDO */
152 ldoctl |= TWL6040_LSLDOENA;
153 ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
154 if (ret)
155 goto lsldo_err;
156 usleep_range(1000, 1500);
157
158 /* enable low-power PLL */
159 lppllctl = TWL6040_LPLLENA;
160 ret = twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
161 if (ret)
162 goto lppll_err;
163 usleep_range(5000, 5500);
164
165 /* disable internal oscillator */
166 ldoctl &= ~TWL6040_OSCENA;
167 ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
168 if (ret)
169 goto osc_err;
170
171 return 0;
172
173osc_err:
174 lppllctl &= ~TWL6040_LPLLENA;
175 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
176lppll_err:
177 ldoctl &= ~TWL6040_LSLDOENA;
178 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
179lsldo_err:
180 ncpctl &= ~TWL6040_NCPENA;
181 twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
182ncp_err:
183 ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
184 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
185
f9be1343 186 dev_err(twl6040->dev, "manual power-up failed\n");
f19b2823
MLC		 187 return ret;
188}
189
190/* twl6040 manual power-down sequence */
f9be1343 191static void twl6040_power_down_manual(struct twl6040 *twl6040)
f19b2823
MLC		 192{
193 u8 ncpctl, ldoctl, lppllctl;
194
195 ncpctl = twl6040_reg_read(twl6040, TWL6040_REG_NCPCTL);
196 ldoctl = twl6040_reg_read(twl6040, TWL6040_REG_LDOCTL);
197 lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
198
199 /* enable internal oscillator */
200 ldoctl |= TWL6040_OSCENA;
201 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
202 usleep_range(1000, 1500);
203
204 /* disable low-power PLL */
205 lppllctl &= ~TWL6040_LPLLENA;
206 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
207
208 /* disable low-side LDO */
209 ldoctl &= ~TWL6040_LSLDOENA;
210 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
211
212 /* disable negative charge pump */
213 ncpctl &= ~TWL6040_NCPENA;
214 twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
215
216 /* disable high-side LDO, reference system and internal oscillator */
217 ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
218 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
219}
220
1ac96265 221static irqreturn_t twl6040_readyint_handler(int irq, void *data)
f19b2823
MLC		 222{
223 struct twl6040 *twl6040 = data;
f19b2823 224
1ac96265 225 complete(&twl6040->ready);
f19b2823 226
1ac96265
PU		 227 return IRQ_HANDLED;
228}
f19b2823 229
1ac96265
PU		 230static irqreturn_t twl6040_thint_handler(int irq, void *data)
231{
232 struct twl6040 *twl6040 = data;
233 u8 status;
234
235 status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
236 if (status & TWL6040_TSHUTDET) {
237 dev_warn(twl6040->dev, "Thermal shutdown, powering-off");
238 twl6040_power(twl6040, 0);
239 } else {
240 dev_warn(twl6040->dev, "Leaving thermal shutdown, powering-on");
241 twl6040_power(twl6040, 1);
f19b2823
MLC		 242 }
243
244 return IRQ_HANDLED;
245}
246
f9be1343 247static int twl6040_power_up_automatic(struct twl6040 *twl6040)
f19b2823
MLC		 248{
249 int time_left;
f9be1343 250
3c92699a 251 gpiod_set_value_cansleep(twl6040->audpwron, 1);
f19b2823
MLC		 252
253 time_left = wait_for_completion_timeout(&twl6040->ready,
254 msecs_to_jiffies(144));
255 if (!time_left) {
f9be1343
PU		 256 u8 intid;
257
258 dev_warn(twl6040->dev, "timeout waiting for READYINT\n");
f19b2823
MLC		 259 intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
260 if (!(intid & TWL6040_READYINT)) {
f9be1343 261 dev_err(twl6040->dev, "automatic power-up failed\n");
3c92699a 262 gpiod_set_value_cansleep(twl6040->audpwron, 0);
f19b2823
MLC		 263 return -ETIMEDOUT;
264 }
265 }
266
267 return 0;
268}
269
270int twl6040_power(struct twl6040 *twl6040, int on)
271{
f19b2823
MLC		 272 int ret = 0;
273
274 mutex_lock(&twl6040->mutex);
275
276 if (on) {
277 /* already powered-up */
278 if (twl6040->power_count++)
279 goto out;
280
32852bca
JMC		 281 ret = clk_prepare_enable(twl6040->clk32k);
282 if (ret) {
283 twl6040->power_count = 0;
284 goto out;
285 }
68bab866 286
c7f9129d
PU		 287 /* Allow writes to the chip */
288 regcache_cache_only(twl6040->regmap, false);
289
3c92699a 290 if (twl6040->audpwron) {
f9be1343
PU		 291 /* use automatic power-up sequence */
292 ret = twl6040_power_up_automatic(twl6040);
f19b2823 293 if (ret) {
d6441dc5 294 clk_disable_unprepare(twl6040->clk32k);
f19b2823
MLC		 295 twl6040->power_count = 0;
296 goto out;
297 }
298 } else {
299 /* use manual power-up sequence */
f9be1343 300 ret = twl6040_power_up_manual(twl6040);
f19b2823 301 if (ret) {
d6441dc5 302 clk_disable_unprepare(twl6040->clk32k);
f19b2823
MLC		 303 twl6040->power_count = 0;
304 goto out;
305 }
306 }
c7f9129d 307
48171d0e
TL		 308 /*
309 * Register access can produce errors after power-up unless we
310 * wait at least 8ms based on measurements on duovero.
311 */
312 usleep_range(10000, 12000);
313
c7f9129d 314 /* Sync with the HW */
48171d0e
TL		 315 ret = regcache_sync(twl6040->regmap);
316 if (ret) {
317 dev_err(twl6040->dev, "Failed to sync with the HW: %i\n",
318 ret);
319 goto out;
320 }
c7f9129d 321
cfb7a33b
PU		 322 /* Default PLL configuration after power up */
323 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
0a58da1e 324 twl6040->sysclk_rate = 19200000;
f19b2823
MLC		 325 } else {
326 /* already powered-down */
327 if (!twl6040->power_count) {
2d7c957e 328 dev_err(twl6040->dev,
f19b2823
MLC		 329 "device is already powered-off\n");
330 ret = -EPERM;
331 goto out;
332 }
333
334 if (--twl6040->power_count)
335 goto out;
336
3c92699a 337 if (twl6040->audpwron) {
f19b2823 338 /* use AUDPWRON line */
3c92699a 339 gpiod_set_value_cansleep(twl6040->audpwron, 0);
f19b2823
MLC		 340
341 /* power-down sequence latency */
342 usleep_range(500, 700);
343 } else {
344 /* use manual power-down sequence */
f9be1343 345 twl6040_power_down_manual(twl6040);
f19b2823 346 }
c7f9129d
PU		 347
348 /* Set regmap to cache only and mark it as dirty */
349 regcache_cache_only(twl6040->regmap, true);
350 regcache_mark_dirty(twl6040->regmap);
351
0a58da1e
PU		 352 twl6040->sysclk_rate = 0;
353
354 if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) {
355 clk_disable_unprepare(twl6040->mclk);
356 twl6040->mclk_rate = 0;
357 }
68bab866
PU		 358
359 clk_disable_unprepare(twl6040->clk32k);
f19b2823
MLC		 360 }
361
362out:
363 mutex_unlock(&twl6040->mutex);
364 return ret;
365}
366EXPORT_SYMBOL(twl6040_power);
367
cfb7a33b 368int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
f19b2823
MLC		 369 unsigned int freq_in, unsigned int freq_out)
370{
371 u8 hppllctl, lppllctl;
372 int ret = 0;
373
374 mutex_lock(&twl6040->mutex);
375
376 hppllctl = twl6040_reg_read(twl6040, TWL6040_REG_HPPLLCTL);
377 lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
378
2bd05db7
PU		 379 /* Force full reconfiguration when switching between PLL */
380 if (pll_id != twl6040->pll) {
0a58da1e
PU		 381 twl6040->sysclk_rate = 0;
382 twl6040->mclk_rate = 0;
2bd05db7
PU		 383 }
384
cfb7a33b
PU		 385 switch (pll_id) {
386 case TWL6040_SYSCLK_SEL_LPPLL:
f19b2823 387 /* low-power PLL divider */
2bd05db7 388 /* Change the sysclk configuration only if it has been canged */
0a58da1e 389 if (twl6040->sysclk_rate != freq_out) {
2bd05db7
PU		 390 switch (freq_out) {
391 case 17640000:
392 lppllctl |= TWL6040_LPLLFIN;
393 break;
394 case 19200000:
395 lppllctl &= ~TWL6040_LPLLFIN;
396 break;
397 default:
398 dev_err(twl6040->dev,
399 "freq_out %d not supported\n",
400 freq_out);
401 ret = -EINVAL;
402 goto pll_out;
403 }
404 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
405 lppllctl);
f19b2823 406 }
2bd05db7
PU		 407
408 /* The PLL in use has not been change, we can exit */
409 if (twl6040->pll == pll_id)
410 break;
f19b2823
MLC		 411
412 switch (freq_in) {
413 case 32768:
414 lppllctl |= TWL6040_LPLLENA;
415 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
416 lppllctl);
417 mdelay(5);
418 lppllctl &= ~TWL6040_HPLLSEL;
419 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
420 lppllctl);
421 hppllctl &= ~TWL6040_HPLLENA;
422 twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
423 hppllctl);
424 break;
425 default:
2d7c957e 426 dev_err(twl6040->dev,
f19b2823
MLC		 427 "freq_in %d not supported\n", freq_in);
428 ret = -EINVAL;
429 goto pll_out;
430 }
0a58da1e
PU		 431
432 clk_disable_unprepare(twl6040->mclk);
f19b2823 433 break;
cfb7a33b 434 case TWL6040_SYSCLK_SEL_HPPLL:
f19b2823
MLC		 435 /* high-performance PLL can provide only 19.2 MHz */
436 if (freq_out != 19200000) {
2d7c957e 437 dev_err(twl6040->dev,
f19b2823
MLC		 438 "freq_out %d not supported\n", freq_out);
439 ret = -EINVAL;
440 goto pll_out;
441 }
442
0a58da1e 443 if (twl6040->mclk_rate != freq_in) {
2bd05db7
PU		 444 hppllctl &= ~TWL6040_MCLK_MSK;
445
446 switch (freq_in) {
447 case 12000000:
448 /* PLL enabled, active mode */
449 hppllctl |= TWL6040_MCLK_12000KHZ |
450 TWL6040_HPLLENA;
451 break;
452 case 19200000:
ac8320c4
PU		 453 /* PLL enabled, bypass mode */
454 hppllctl |= TWL6040_MCLK_19200KHZ |
455 TWL6040_HPLLBP | TWL6040_HPLLENA;
2bd05db7
PU		 456 break;
457 case 26000000:
458 /* PLL enabled, active mode */
459 hppllctl |= TWL6040_MCLK_26000KHZ |
460 TWL6040_HPLLENA;
461 break;
462 case 38400000:
ac8320c4 463 /* PLL enabled, bypass mode */
2bd05db7 464 hppllctl |= TWL6040_MCLK_38400KHZ |
ac8320c4 465 TWL6040_HPLLBP | TWL6040_HPLLENA;
2bd05db7
PU		 466 break;
467 default:
468 dev_err(twl6040->dev,
469 "freq_in %d not supported\n", freq_in);
470 ret = -EINVAL;
471 goto pll_out;
472 }
f19b2823 473
0a58da1e
PU		 474 /* When switching to HPPLL, enable the mclk first */
475 if (pll_id != twl6040->pll)
476 clk_prepare_enable(twl6040->mclk);
f19b2823 477 /*
2bd05db7
PU		 478 * enable clock slicer to ensure input waveform is
479 * square
f19b2823 480 */
2bd05db7 481 hppllctl |= TWL6040_HPLLSQRENA;
f19b2823 482
2bd05db7
PU		 483 twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
484 hppllctl);
485 usleep_range(500, 700);
486 lppllctl |= TWL6040_HPLLSEL;
487 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
488 lppllctl);
489 lppllctl &= ~TWL6040_LPLLENA;
490 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
491 lppllctl);
0a58da1e
PU		 492
493 twl6040->mclk_rate = freq_in;
2bd05db7 494 }
f19b2823
MLC		 495 break;
496 default:
2d7c957e 497 dev_err(twl6040->dev, "unknown pll id %d\n", pll_id);
f19b2823
MLC		 498 ret = -EINVAL;
499 goto pll_out;
500 }
501
0a58da1e 502 twl6040->sysclk_rate = freq_out;
cfb7a33b 503 twl6040->pll = pll_id;
f19b2823
MLC		 504
505pll_out:
506 mutex_unlock(&twl6040->mutex);
507 return ret;
508}
509EXPORT_SYMBOL(twl6040_set_pll);
510
cfb7a33b 511int twl6040_get_pll(struct twl6040 *twl6040)
f19b2823 512{
cfb7a33b
PU		 513 if (twl6040->power_count)
514 return twl6040->pll;
515 else
516 return -ENODEV;
f19b2823
MLC		 517}
518EXPORT_SYMBOL(twl6040_get_pll);
519
520unsigned int twl6040_get_sysclk(struct twl6040 *twl6040)
521{
0a58da1e 522 return twl6040->sysclk_rate;
f19b2823
MLC		 523}
524EXPORT_SYMBOL(twl6040_get_sysclk);
525
70601ec1
PU		 526/* Get the combined status of the vibra control register */
527int twl6040_get_vibralr_status(struct twl6040 *twl6040)
528{
c6f39257
MB		 529 unsigned int reg;
530 int ret;
70601ec1
PU		 531 u8 status;
532
c6f39257
MB		 533 ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLL, &reg);
534 if (ret != 0)
535 return ret;
536 status = reg;
537
538 ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLR, &reg);
539 if (ret != 0)
540 return ret;
541 status |= reg;
542
70601ec1
PU		 543 status &= (TWL6040_VIBENA | TWL6040_VIBSEL);
544
545 return status;
546}
547EXPORT_SYMBOL(twl6040_get_vibralr_status);
548
0f962ae2
PU		 549static struct resource twl6040_vibra_rsrc[] = {
550 {
551 .flags = IORESOURCE_IRQ,
552 },
553};
554
555static struct resource twl6040_codec_rsrc[] = {
556 {
557 .flags = IORESOURCE_IRQ,
558 },
559};
560
8eaeb939 561static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
f19b2823 562{
8eaeb939
PU		 563 /* Register 0 is not readable */
564 if (!reg)
565 return false;
566 return true;
567}
568
c6f39257
MB		 569static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
570{
571 switch (reg) {
c7f9129d
PU		 572 case TWL6040_REG_ASICID:
573 case TWL6040_REG_ASICREV:
574 case TWL6040_REG_INTID:
575 case TWL6040_REG_LPPLLCTL:
576 case TWL6040_REG_HPPLLCTL:
577 case TWL6040_REG_STATUS:
578 return true;
579 default:
580 return false;
581 }
582}
583
584static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
585{
586 switch (reg) {
587 case TWL6040_REG_ASICID:
588 case TWL6040_REG_ASICREV:
589 case TWL6040_REG_STATUS:
c6f39257
MB		 590 return false;
591 default:
592 return true;
593 }
594}
595
de1e23f8 596static const struct regmap_config twl6040_regmap_config = {
8eaeb939
PU		 597 .reg_bits = 8,
598 .val_bits = 8,
c7f9129d
PU		 599
600 .reg_defaults = twl6040_defaults,
601 .num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
602
8eaeb939
PU		 603 .max_register = TWL6040_REG_STATUS, /* 0x2e */
604
605 .readable_reg = twl6040_readable_reg,
c6f39257 606 .volatile_reg = twl6040_volatile_reg,
c7f9129d 607 .writeable_reg = twl6040_writeable_reg,
c6f39257 608
d99df657 609 .cache_type = REGCACHE_MAPLE,
1c96a2f6
DF		 610 .use_single_read = true,
611 .use_single_write = true,
8eaeb939
PU		 612};
613
ab7edb14
PU		 614static const struct regmap_irq twl6040_irqs[] = {
615 { .reg_offset = 0, .mask = TWL6040_THINT, },
616 { .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
617 { .reg_offset = 0, .mask = TWL6040_HOOKINT, },
618 { .reg_offset = 0, .mask = TWL6040_HFINT, },
619 { .reg_offset = 0, .mask = TWL6040_VIBINT, },
620 { .reg_offset = 0, .mask = TWL6040_READYINT, },
621};
622
3062ba3a 623static const struct regmap_irq_chip twl6040_irq_chip = {
ab7edb14
PU		 624 .name = "twl6040",
625 .irqs = twl6040_irqs,
626 .num_irqs = ARRAY_SIZE(twl6040_irqs),
627
628 .num_regs = 1,
629 .status_base = TWL6040_REG_INTID,
630 .mask_base = TWL6040_REG_INTMR,
631};
632
d85213be 633static int twl6040_probe(struct i2c_client *client)
8eaeb939 634{
37e13cec 635 struct device_node *node = client->dev.of_node;
f19b2823
MLC		 636 struct twl6040 *twl6040;
637 struct mfd_cell *cell = NULL;
1f01d60e 638 int irq, ret, children = 0;
f19b2823 639
df04b624
PU		 640 if (!node) {
641 dev_err(&client->dev, "of node is missing\n");
f19b2823
MLC		 642 return -EINVAL;
643 }
644
d20e1d21 645 /* In order to operate correctly we need valid interrupt config */
6712419d 646 if (!client->irq) {
8eaeb939 647 dev_err(&client->dev, "Invalid IRQ configuration\n");
d20e1d21
PU		 648 return -EINVAL;
649 }
650
8eaeb939
PU		 651 twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040),
652 GFP_KERNEL);
ecc8fa1c
PU		 653 if (!twl6040)
654 return -ENOMEM;
8eaeb939 655
bbf6adc1 656 twl6040->regmap = devm_regmap_init_i2c(client, &twl6040_regmap_config);
ecc8fa1c
PU		 657 if (IS_ERR(twl6040->regmap))
658 return PTR_ERR(twl6040->regmap);
f19b2823 659
8eaeb939 660 i2c_set_clientdata(client, twl6040);
f19b2823 661
68bab866
PU		 662 twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
663 if (IS_ERR(twl6040->clk32k)) {
75c08f17
TL		 664 if (PTR_ERR(twl6040->clk32k) == -EPROBE_DEFER)
665 return -EPROBE_DEFER;
0a58da1e 666 dev_dbg(&client->dev, "clk32k is not handled\n");
68bab866
PU		 667 twl6040->clk32k = NULL;
668 }
669
0a58da1e
PU		 670 twl6040->mclk = devm_clk_get(&client->dev, "mclk");
671 if (IS_ERR(twl6040->mclk)) {
672 if (PTR_ERR(twl6040->mclk) == -EPROBE_DEFER)
673 return -EPROBE_DEFER;
674 dev_dbg(&client->dev, "mclk is not handled\n");
675 twl6040->mclk = NULL;
676 }
677
5af7df6b
PU		 678 twl6040->supplies[0].supply = "vio";
679 twl6040->supplies[1].supply = "v2v1";
990810b0 680 ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
37aefe9f 681 twl6040->supplies);
5af7df6b
PU		 682 if (ret != 0) {
683 dev_err(&client->dev, "Failed to get supplies: %d\n", ret);
501d609a 684 return ret;
5af7df6b
PU		 685 }
686
687 ret = regulator_bulk_enable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
688 if (ret != 0) {
689 dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
501d609a 690 return ret;
5af7df6b
PU		 691 }
692
8eaeb939
PU		 693 twl6040->dev = &client->dev;
694 twl6040->irq = client->irq;
f19b2823
MLC		 695
696 mutex_init(&twl6040->mutex);
f19b2823
MLC		 697 init_completion(&twl6040->ready);
698
006cea3a
PU		 699 regmap_register_patch(twl6040->regmap, twl6040_patch,
700 ARRAY_SIZE(twl6040_patch));
701
f19b2823 702 twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
89d68998
FV		 703 if (twl6040->rev < 0) {
704 dev_err(&client->dev, "Failed to read revision register: %d\n",
705 twl6040->rev);
f2b86781 706 ret = twl6040->rev;
89d68998
FV		 707 goto gpio_err;
708 }
f19b2823 709
77f63e06 710 /* ERRATA: Automatic power-up is not possible in ES1.0 */
3c92699a
DT		 711 if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0) {
712 twl6040->audpwron = devm_gpiod_get_optional(&client->dev,
713 "ti,audpwron",
714 GPIOD_OUT_LOW);
715 ret = PTR_ERR_OR_ZERO(twl6040->audpwron);
f19b2823 716 if (ret)
5af7df6b 717 goto gpio_err;
02d02728 718
3c92699a
DT		 719 gpiod_set_consumer_name(twl6040->audpwron, "audpwron");
720
02d02728
PU		 721 /* Clear any pending interrupt */
722 twl6040_reg_read(twl6040, TWL6040_REG_INTID);
f19b2823
MLC		 723 }
724
37aefe9f 725 ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq, IRQF_ONESHOT,
c06f308a 726 0, &twl6040_irq_chip, &twl6040->irq_data);
ab7edb14 727 if (ret < 0)
990810b0 728 goto gpio_err;
d20e1d21 729
ab7edb14 730 twl6040->irq_ready = regmap_irq_get_virq(twl6040->irq_data,
37aefe9f 731 TWL6040_IRQ_READY);
ab7edb14 732 twl6040->irq_th = regmap_irq_get_virq(twl6040->irq_data,
37aefe9f 733 TWL6040_IRQ_TH);
ab7edb14 734
990810b0 735 ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_ready, NULL,
37aefe9f
PU		 736 twl6040_readyint_handler, IRQF_ONESHOT,
737 "twl6040_irq_ready", twl6040);
d20e1d21 738 if (ret) {
1ac96265
PU		 739 dev_err(twl6040->dev, "READY IRQ request failed: %d\n", ret);
740 goto readyirq_err;
741 }
742
990810b0 743 ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_th, NULL,
37aefe9f
PU		 744 twl6040_thint_handler, IRQF_ONESHOT,
745 "twl6040_irq_th", twl6040);
1ac96265
PU		 746 if (ret) {
747 dev_err(twl6040->dev, "Thermal IRQ request failed: %d\n", ret);
fc5ee96f 748 goto readyirq_err;
f19b2823
MLC		 749 }
750
1f01d60e
PU		 751 /*
752 * The main functionality of twl6040 to provide audio on OMAP4+ systems.
753 * We can add the ASoC codec child whenever this driver has been loaded.
1f01d60e 754 */
ab7edb14 755 irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_PLUG);
1f01d60e
PU		 756 cell = &twl6040->cells[children];
757 cell->name = "twl6040-codec";
758 twl6040_codec_rsrc[0].start = irq;
759 twl6040_codec_rsrc[0].end = irq;
760 cell->resources = twl6040_codec_rsrc;
761 cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
1f01d60e 762 children++;
f19b2823 763
df04b624
PU		 764 /* Vibra input driver support */
765 if (twl6040_has_vibra(node)) {
ab7edb14 766 irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_VIB);
0f962ae2 767
f19b2823
MLC		 768 cell = &twl6040->cells[children];
769 cell->name = "twl6040-vibra";
0f962ae2
PU		 770 twl6040_vibra_rsrc[0].start = irq;
771 twl6040_vibra_rsrc[0].end = irq;
772 cell->resources = twl6040_vibra_rsrc;
773 cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
f19b2823
MLC		 774 children++;
775 }
776
df04b624
PU		 777 /* GPO support */
778 cell = &twl6040->cells[children];
779 cell->name = "twl6040-gpo";
780 children++;
5cbe786a 781
0133d323
PU		 782 /* PDM clock support */
783 cell = &twl6040->cells[children];
784 cell->name = "twl6040-pdmclk";
785 children++;
786
c7f9129d
PU		 787 /* The chip is powered down so mark regmap to cache only and dirty */
788 regcache_cache_only(twl6040->regmap, true);
789 regcache_mark_dirty(twl6040->regmap);
790
1f01d60e 791 ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
55692af5 792 NULL, 0, NULL);
1f01d60e 793 if (ret)
fc5ee96f 794 goto readyirq_err;
f19b2823
MLC		 795
796 return 0;
797
1ac96265 798readyirq_err:
ab7edb14 799 regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
5af7df6b
PU		 800gpio_err:
801 regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
f19b2823
MLC		 802 return ret;
803}
804
ed5c2f5f 805static void twl6040_remove(struct i2c_client *client)
f19b2823 806{
8eaeb939 807 struct twl6040 *twl6040 = i2c_get_clientdata(client);
f19b2823
MLC		 808
809 if (twl6040->power_count)
810 twl6040_power(twl6040, 0);
811
ab7edb14 812 regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
f19b2823 813
8eaeb939 814 mfd_remove_devices(&client->dev);
f19b2823 815
5af7df6b 816 regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
f19b2823
MLC		 817}
818
8eaeb939 819static const struct i2c_device_id twl6040_i2c_id[] = {
5e9ea43c
UKK		 820 { "twl6040" },
821 { "twl6041" },
822 { }
8eaeb939
PU		 823};
824MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id);
825
826static struct i2c_driver twl6040_driver = {
827 .driver = {
828 .name = "twl6040",
8eaeb939 829 },
9816d859 830 .probe = twl6040_probe,
612b95cd 831 .remove = twl6040_remove,
8eaeb939 832 .id_table = twl6040_i2c_id,
f19b2823
MLC		 833};
834
8eaeb939 835module_i2c_driver(twl6040_driver);
f19b2823
MLC		 836
837MODULE_DESCRIPTION("TWL6040 MFD");
838MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
839MODULE_AUTHOR("Jorge Eduardo Candelaria <jorge.candelaria@ti.com>");
Linux 6.x block layer and io_uring tree(s)