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Merge tag 'for-linus-5.3-2' of git://github.com/cminyard/linux-ipmi
[linux-2.6-block.git] / drivers / mfd / twl6040.c
CommitLineData
2b27bdcc 1// SPDX-License-Identifier: GPL-2.0-only
f19b2823
MLC		 2/*
3 * MFD driver for TWL6040 audio device
4 *
5 * Authors: Misael Lopez Cruz <misael.lopez@ti.com>
6 * Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
7 * Peter Ujfalusi <peter.ujfalusi@ti.com>
8 *
9 * Copyright: (C) 2011 Texas Instruments, Inc.
f19b2823
MLC		 10 */
11
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/slab.h>
15#include <linux/kernel.h>
5af7df6b 16#include <linux/err.h>
f19b2823 17#include <linux/platform_device.h>
37e13cec
PU		 18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_gpio.h>
21#include <linux/of_platform.h>
f19b2823
MLC		 22#include <linux/gpio.h>
23#include <linux/delay.h>
8eaeb939
PU		 24#include <linux/i2c.h>
25#include <linux/regmap.h>
f19b2823
MLC		 26#include <linux/mfd/core.h>
27#include <linux/mfd/twl6040.h>
5af7df6b 28#include <linux/regulator/consumer.h>
f19b2823 29
31b402e3 30#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
5af7df6b 31#define TWL6040_NUM_SUPPLIES (2)
31b402e3 32
de1e23f8 33static const struct reg_default twl6040_defaults[] = {
c7f9129d
PU		 34 { 0x01, 0x4B }, /* REG_ASICID (ro) */
35 { 0x02, 0x00 }, /* REG_ASICREV (ro) */
36 { 0x03, 0x00 }, /* REG_INTID */
37 { 0x04, 0x00 }, /* REG_INTMR */
38 { 0x05, 0x00 }, /* REG_NCPCTRL */
39 { 0x06, 0x00 }, /* REG_LDOCTL */
40 { 0x07, 0x60 }, /* REG_HPPLLCTL */
41 { 0x08, 0x00 }, /* REG_LPPLLCTL */
42 { 0x09, 0x4A }, /* REG_LPPLLDIV */
43 { 0x0A, 0x00 }, /* REG_AMICBCTL */
44 { 0x0B, 0x00 }, /* REG_DMICBCTL */
45 { 0x0C, 0x00 }, /* REG_MICLCTL */
46 { 0x0D, 0x00 }, /* REG_MICRCTL */
47 { 0x0E, 0x00 }, /* REG_MICGAIN */
48 { 0x0F, 0x1B }, /* REG_LINEGAIN */
49 { 0x10, 0x00 }, /* REG_HSLCTL */
50 { 0x11, 0x00 }, /* REG_HSRCTL */
51 { 0x12, 0x00 }, /* REG_HSGAIN */
52 { 0x13, 0x00 }, /* REG_EARCTL */
53 { 0x14, 0x00 }, /* REG_HFLCTL */
54 { 0x15, 0x00 }, /* REG_HFLGAIN */
55 { 0x16, 0x00 }, /* REG_HFRCTL */
56 { 0x17, 0x00 }, /* REG_HFRGAIN */
57 { 0x18, 0x00 }, /* REG_VIBCTLL */
58 { 0x19, 0x00 }, /* REG_VIBDATL */
59 { 0x1A, 0x00 }, /* REG_VIBCTLR */
60 { 0x1B, 0x00 }, /* REG_VIBDATR */
61 { 0x1C, 0x00 }, /* REG_HKCTL1 */
62 { 0x1D, 0x00 }, /* REG_HKCTL2 */
63 { 0x1E, 0x00 }, /* REG_GPOCTL */
64 { 0x1F, 0x00 }, /* REG_ALB */
65 { 0x20, 0x00 }, /* REG_DLB */
66 /* 0x28, REG_TRIM1 */
67 /* 0x29, REG_TRIM2 */
68 /* 0x2A, REG_TRIM3 */
69 /* 0x2B, REG_HSOTRIM */
70 /* 0x2C, REG_HFOTRIM */
71 { 0x2D, 0x08 }, /* REG_ACCCTL */
72 { 0x2E, 0x00 }, /* REG_STATUS (ro) */
73};
74
8019ff6c 75static struct reg_sequence twl6040_patch[] = {
11e38e11
PU		 76 /*
77 * Select I2C bus access to dual access registers
78 * Interrupt register is cleared on read
79 * Select fast mode for i2c (400KHz)
80 */
81 { TWL6040_REG_ACCCTL,
82 TWL6040_I2CSEL | TWL6040_INTCLRMODE | TWL6040_I2CMODE(1) },
c7f9129d
PU		 83};
84
85
85e9b13c 86static bool twl6040_has_vibra(struct device_node *parent)
ca2cad6a 87{
85e9b13c
JH		 88 struct device_node *node;
89
90 node = of_get_child_by_name(parent, "vibra");
91 if (node) {
92 of_node_put(node);
ca2cad6a 93 return true;
85e9b13c
JH		 94 }
95
ca2cad6a
SO		 96 return false;
97}
98
f19b2823
MLC		 99int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
100{
101 int ret;
8eaeb939 102 unsigned int val;
f19b2823 103
c6f39257
MB		 104 ret = regmap_read(twl6040->regmap, reg, &val);
105 if (ret < 0)
106 return ret;
f19b2823
MLC		 107
108 return val;
109}
110EXPORT_SYMBOL(twl6040_reg_read);
111
112int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
113{
114 int ret;
115
8eaeb939 116 ret = regmap_write(twl6040->regmap, reg, val);
f19b2823
MLC		 117
118 return ret;
119}
120EXPORT_SYMBOL(twl6040_reg_write);
121
122int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
123{
c600040f 124 return regmap_update_bits(twl6040->regmap, reg, mask, mask);
f19b2823
MLC		 125}
126EXPORT_SYMBOL(twl6040_set_bits);
127
128int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
129{
c600040f 130 return regmap_update_bits(twl6040->regmap, reg, mask, 0);
f19b2823
MLC		 131}
132EXPORT_SYMBOL(twl6040_clear_bits);
133
134/* twl6040 codec manual power-up sequence */
f9be1343 135static int twl6040_power_up_manual(struct twl6040 *twl6040)
f19b2823
MLC		 136{
137 u8 ldoctl, ncpctl, lppllctl;
138 int ret;
139
140 /* enable high-side LDO, reference system and internal oscillator */
141 ldoctl = TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA;
142 ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
143 if (ret)
144 return ret;
145 usleep_range(10000, 10500);
146
147 /* enable negative charge pump */
148 ncpctl = TWL6040_NCPENA;
149 ret = twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
150 if (ret)
151 goto ncp_err;
152 usleep_range(1000, 1500);
153
154 /* enable low-side LDO */
155 ldoctl |= TWL6040_LSLDOENA;
156 ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
157 if (ret)
158 goto lsldo_err;
159 usleep_range(1000, 1500);
160
161 /* enable low-power PLL */
162 lppllctl = TWL6040_LPLLENA;
163 ret = twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
164 if (ret)
165 goto lppll_err;
166 usleep_range(5000, 5500);
167
168 /* disable internal oscillator */
169 ldoctl &= ~TWL6040_OSCENA;
170 ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
171 if (ret)
172 goto osc_err;
173
174 return 0;
175
176osc_err:
177 lppllctl &= ~TWL6040_LPLLENA;
178 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
179lppll_err:
180 ldoctl &= ~TWL6040_LSLDOENA;
181 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
182lsldo_err:
183 ncpctl &= ~TWL6040_NCPENA;
184 twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
185ncp_err:
186 ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
187 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
188
f9be1343 189 dev_err(twl6040->dev, "manual power-up failed\n");
f19b2823
MLC		 190 return ret;
191}
192
193/* twl6040 manual power-down sequence */
f9be1343 194static void twl6040_power_down_manual(struct twl6040 *twl6040)
f19b2823
MLC		 195{
196 u8 ncpctl, ldoctl, lppllctl;
197
198 ncpctl = twl6040_reg_read(twl6040, TWL6040_REG_NCPCTL);
199 ldoctl = twl6040_reg_read(twl6040, TWL6040_REG_LDOCTL);
200 lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
201
202 /* enable internal oscillator */
203 ldoctl |= TWL6040_OSCENA;
204 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
205 usleep_range(1000, 1500);
206
207 /* disable low-power PLL */
208 lppllctl &= ~TWL6040_LPLLENA;
209 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
210
211 /* disable low-side LDO */
212 ldoctl &= ~TWL6040_LSLDOENA;
213 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
214
215 /* disable negative charge pump */
216 ncpctl &= ~TWL6040_NCPENA;
217 twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
218
219 /* disable high-side LDO, reference system and internal oscillator */
220 ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
221 twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
222}
223
1ac96265 224static irqreturn_t twl6040_readyint_handler(int irq, void *data)
f19b2823
MLC		 225{
226 struct twl6040 *twl6040 = data;
f19b2823 227
1ac96265 228 complete(&twl6040->ready);
f19b2823 229
1ac96265
PU		 230 return IRQ_HANDLED;
231}
f19b2823 232
1ac96265
PU		 233static irqreturn_t twl6040_thint_handler(int irq, void *data)
234{
235 struct twl6040 *twl6040 = data;
236 u8 status;
237
238 status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
239 if (status & TWL6040_TSHUTDET) {
240 dev_warn(twl6040->dev, "Thermal shutdown, powering-off");
241 twl6040_power(twl6040, 0);
242 } else {
243 dev_warn(twl6040->dev, "Leaving thermal shutdown, powering-on");
244 twl6040_power(twl6040, 1);
f19b2823
MLC		 245 }
246
247 return IRQ_HANDLED;
248}
249
f9be1343 250static int twl6040_power_up_automatic(struct twl6040 *twl6040)
f19b2823
MLC		 251{
252 int time_left;
f9be1343
PU		 253
254 gpio_set_value(twl6040->audpwron, 1);
f19b2823
MLC		 255
256 time_left = wait_for_completion_timeout(&twl6040->ready,
257 msecs_to_jiffies(144));
258 if (!time_left) {
f9be1343
PU		 259 u8 intid;
260
261 dev_warn(twl6040->dev, "timeout waiting for READYINT\n");
f19b2823
MLC		 262 intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
263 if (!(intid & TWL6040_READYINT)) {
f9be1343
PU		 264 dev_err(twl6040->dev, "automatic power-up failed\n");
265 gpio_set_value(twl6040->audpwron, 0);
f19b2823
MLC		 266 return -ETIMEDOUT;
267 }
268 }
269
270 return 0;
271}
272
273int twl6040_power(struct twl6040 *twl6040, int on)
274{
f19b2823
MLC		 275 int ret = 0;
276
277 mutex_lock(&twl6040->mutex);
278
279 if (on) {
280 /* already powered-up */
281 if (twl6040->power_count++)
282 goto out;
283
32852bca
JMC		 284 ret = clk_prepare_enable(twl6040->clk32k);
285 if (ret) {
286 twl6040->power_count = 0;
287 goto out;
288 }
68bab866 289
c7f9129d
PU		 290 /* Allow writes to the chip */
291 regcache_cache_only(twl6040->regmap, false);
292
f9be1343
PU		 293 if (gpio_is_valid(twl6040->audpwron)) {
294 /* use automatic power-up sequence */
295 ret = twl6040_power_up_automatic(twl6040);
f19b2823 296 if (ret) {
d6441dc5 297 clk_disable_unprepare(twl6040->clk32k);
f19b2823
MLC		 298 twl6040->power_count = 0;
299 goto out;
300 }
301 } else {
302 /* use manual power-up sequence */
f9be1343 303 ret = twl6040_power_up_manual(twl6040);
f19b2823 304 if (ret) {
d6441dc5 305 clk_disable_unprepare(twl6040->clk32k);
f19b2823
MLC		 306 twl6040->power_count = 0;
307 goto out;
308 }
309 }
c7f9129d 310
48171d0e
TL		 311 /*
312 * Register access can produce errors after power-up unless we
313 * wait at least 8ms based on measurements on duovero.
314 */
315 usleep_range(10000, 12000);
316
c7f9129d 317 /* Sync with the HW */
48171d0e
TL		 318 ret = regcache_sync(twl6040->regmap);
319 if (ret) {
320 dev_err(twl6040->dev, "Failed to sync with the HW: %i\n",
321 ret);
322 goto out;
323 }
c7f9129d 324
cfb7a33b
PU		 325 /* Default PLL configuration after power up */
326 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
0a58da1e 327 twl6040->sysclk_rate = 19200000;
f19b2823
MLC		 328 } else {
329 /* already powered-down */
330 if (!twl6040->power_count) {
2d7c957e 331 dev_err(twl6040->dev,
f19b2823
MLC		 332 "device is already powered-off\n");
333 ret = -EPERM;
334 goto out;
335 }
336
337 if (--twl6040->power_count)
338 goto out;
339
f9be1343 340 if (gpio_is_valid(twl6040->audpwron)) {
f19b2823 341 /* use AUDPWRON line */
f9be1343 342 gpio_set_value(twl6040->audpwron, 0);
f19b2823
MLC		 343
344 /* power-down sequence latency */
345 usleep_range(500, 700);
346 } else {
347 /* use manual power-down sequence */
f9be1343 348 twl6040_power_down_manual(twl6040);
f19b2823 349 }
c7f9129d
PU		 350
351 /* Set regmap to cache only and mark it as dirty */
352 regcache_cache_only(twl6040->regmap, true);
353 regcache_mark_dirty(twl6040->regmap);
354
0a58da1e
PU		 355 twl6040->sysclk_rate = 0;
356
357 if (twl6040->pll == TWL6040_SYSCLK_SEL_HPPLL) {
358 clk_disable_unprepare(twl6040->mclk);
359 twl6040->mclk_rate = 0;
360 }
68bab866
PU		 361
362 clk_disable_unprepare(twl6040->clk32k);
f19b2823
MLC		 363 }
364
365out:
366 mutex_unlock(&twl6040->mutex);
367 return ret;
368}
369EXPORT_SYMBOL(twl6040_power);
370
cfb7a33b 371int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
f19b2823
MLC		 372 unsigned int freq_in, unsigned int freq_out)
373{
374 u8 hppllctl, lppllctl;
375 int ret = 0;
376
377 mutex_lock(&twl6040->mutex);
378
379 hppllctl = twl6040_reg_read(twl6040, TWL6040_REG_HPPLLCTL);
380 lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
381
2bd05db7
PU		 382 /* Force full reconfiguration when switching between PLL */
383 if (pll_id != twl6040->pll) {
0a58da1e
PU		 384 twl6040->sysclk_rate = 0;
385 twl6040->mclk_rate = 0;
2bd05db7
PU		 386 }
387
cfb7a33b
PU		 388 switch (pll_id) {
389 case TWL6040_SYSCLK_SEL_LPPLL:
f19b2823 390 /* low-power PLL divider */
2bd05db7 391 /* Change the sysclk configuration only if it has been canged */
0a58da1e 392 if (twl6040->sysclk_rate != freq_out) {
2bd05db7
PU		 393 switch (freq_out) {
394 case 17640000:
395 lppllctl |= TWL6040_LPLLFIN;
396 break;
397 case 19200000:
398 lppllctl &= ~TWL6040_LPLLFIN;
399 break;
400 default:
401 dev_err(twl6040->dev,
402 "freq_out %d not supported\n",
403 freq_out);
404 ret = -EINVAL;
405 goto pll_out;
406 }
407 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
408 lppllctl);
f19b2823 409 }
2bd05db7
PU		 410
411 /* The PLL in use has not been change, we can exit */
412 if (twl6040->pll == pll_id)
413 break;
f19b2823
MLC		 414
415 switch (freq_in) {
416 case 32768:
417 lppllctl |= TWL6040_LPLLENA;
418 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
419 lppllctl);
420 mdelay(5);
421 lppllctl &= ~TWL6040_HPLLSEL;
422 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
423 lppllctl);
424 hppllctl &= ~TWL6040_HPLLENA;
425 twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
426 hppllctl);
427 break;
428 default:
2d7c957e 429 dev_err(twl6040->dev,
f19b2823
MLC		 430 "freq_in %d not supported\n", freq_in);
431 ret = -EINVAL;
432 goto pll_out;
433 }
0a58da1e
PU		 434
435 clk_disable_unprepare(twl6040->mclk);
f19b2823 436 break;
cfb7a33b 437 case TWL6040_SYSCLK_SEL_HPPLL:
f19b2823
MLC		 438 /* high-performance PLL can provide only 19.2 MHz */
439 if (freq_out != 19200000) {
2d7c957e 440 dev_err(twl6040->dev,
f19b2823
MLC		 441 "freq_out %d not supported\n", freq_out);
442 ret = -EINVAL;
443 goto pll_out;
444 }
445
0a58da1e 446 if (twl6040->mclk_rate != freq_in) {
2bd05db7
PU		 447 hppllctl &= ~TWL6040_MCLK_MSK;
448
449 switch (freq_in) {
450 case 12000000:
451 /* PLL enabled, active mode */
452 hppllctl |= TWL6040_MCLK_12000KHZ |
453 TWL6040_HPLLENA;
454 break;
455 case 19200000:
ac8320c4
PU		 456 /* PLL enabled, bypass mode */
457 hppllctl |= TWL6040_MCLK_19200KHZ |
458 TWL6040_HPLLBP | TWL6040_HPLLENA;
2bd05db7
PU		 459 break;
460 case 26000000:
461 /* PLL enabled, active mode */
462 hppllctl |= TWL6040_MCLK_26000KHZ |
463 TWL6040_HPLLENA;
464 break;
465 case 38400000:
ac8320c4 466 /* PLL enabled, bypass mode */
2bd05db7 467 hppllctl |= TWL6040_MCLK_38400KHZ |
ac8320c4 468 TWL6040_HPLLBP | TWL6040_HPLLENA;
2bd05db7
PU		 469 break;
470 default:
471 dev_err(twl6040->dev,
472 "freq_in %d not supported\n", freq_in);
473 ret = -EINVAL;
474 goto pll_out;
475 }
f19b2823 476
0a58da1e
PU		 477 /* When switching to HPPLL, enable the mclk first */
478 if (pll_id != twl6040->pll)
479 clk_prepare_enable(twl6040->mclk);
f19b2823 480 /*
2bd05db7
PU		 481 * enable clock slicer to ensure input waveform is
482 * square
f19b2823 483 */
2bd05db7 484 hppllctl |= TWL6040_HPLLSQRENA;
f19b2823 485
2bd05db7
PU		 486 twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
487 hppllctl);
488 usleep_range(500, 700);
489 lppllctl |= TWL6040_HPLLSEL;
490 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
491 lppllctl);
492 lppllctl &= ~TWL6040_LPLLENA;
493 twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
494 lppllctl);
0a58da1e
PU		 495
496 twl6040->mclk_rate = freq_in;
2bd05db7 497 }
f19b2823
MLC		 498 break;
499 default:
2d7c957e 500 dev_err(twl6040->dev, "unknown pll id %d\n", pll_id);
f19b2823
MLC		 501 ret = -EINVAL;
502 goto pll_out;
503 }
504
0a58da1e 505 twl6040->sysclk_rate = freq_out;
cfb7a33b 506 twl6040->pll = pll_id;
f19b2823
MLC		 507
508pll_out:
509 mutex_unlock(&twl6040->mutex);
510 return ret;
511}
512EXPORT_SYMBOL(twl6040_set_pll);
513
cfb7a33b 514int twl6040_get_pll(struct twl6040 *twl6040)
f19b2823 515{
cfb7a33b
PU		 516 if (twl6040->power_count)
517 return twl6040->pll;
518 else
519 return -ENODEV;
f19b2823
MLC		 520}
521EXPORT_SYMBOL(twl6040_get_pll);
522
523unsigned int twl6040_get_sysclk(struct twl6040 *twl6040)
524{
0a58da1e 525 return twl6040->sysclk_rate;
f19b2823
MLC		 526}
527EXPORT_SYMBOL(twl6040_get_sysclk);
528
70601ec1
PU		 529/* Get the combined status of the vibra control register */
530int twl6040_get_vibralr_status(struct twl6040 *twl6040)
531{
c6f39257
MB		 532 unsigned int reg;
533 int ret;
70601ec1
PU		 534 u8 status;
535
c6f39257
MB		 536 ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLL, &reg);
537 if (ret != 0)
538 return ret;
539 status = reg;
540
541 ret = regmap_read(twl6040->regmap, TWL6040_REG_VIBCTLR, &reg);
542 if (ret != 0)
543 return ret;
544 status |= reg;
545
70601ec1
PU		 546 status &= (TWL6040_VIBENA | TWL6040_VIBSEL);
547
548 return status;
549}
550EXPORT_SYMBOL(twl6040_get_vibralr_status);
551
0f962ae2
PU		 552static struct resource twl6040_vibra_rsrc[] = {
553 {
554 .flags = IORESOURCE_IRQ,
555 },
556};
557
558static struct resource twl6040_codec_rsrc[] = {
559 {
560 .flags = IORESOURCE_IRQ,
561 },
562};
563
8eaeb939 564static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
f19b2823 565{
8eaeb939
PU		 566 /* Register 0 is not readable */
567 if (!reg)
568 return false;
569 return true;
570}
571
c6f39257
MB		 572static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
573{
574 switch (reg) {
c7f9129d
PU		 575 case TWL6040_REG_ASICID:
576 case TWL6040_REG_ASICREV:
577 case TWL6040_REG_INTID:
578 case TWL6040_REG_LPPLLCTL:
579 case TWL6040_REG_HPPLLCTL:
580 case TWL6040_REG_STATUS:
581 return true;
582 default:
583 return false;
584 }
585}
586
587static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
588{
589 switch (reg) {
590 case TWL6040_REG_ASICID:
591 case TWL6040_REG_ASICREV:
592 case TWL6040_REG_STATUS:
c6f39257
MB		 593 return false;
594 default:
595 return true;
596 }
597}
598
de1e23f8 599static const struct regmap_config twl6040_regmap_config = {
8eaeb939
PU		 600 .reg_bits = 8,
601 .val_bits = 8,
c7f9129d
PU		 602
603 .reg_defaults = twl6040_defaults,
604 .num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
605
8eaeb939
PU		 606 .max_register = TWL6040_REG_STATUS, /* 0x2e */
607
608 .readable_reg = twl6040_readable_reg,
c6f39257 609 .volatile_reg = twl6040_volatile_reg,
c7f9129d 610 .writeable_reg = twl6040_writeable_reg,
c6f39257
MB		 611
612 .cache_type = REGCACHE_RBTREE,
1c96a2f6
DF		 613 .use_single_read = true,
614 .use_single_write = true,
8eaeb939
PU		 615};
616
ab7edb14
PU		 617static const struct regmap_irq twl6040_irqs[] = {
618 { .reg_offset = 0, .mask = TWL6040_THINT, },
619 { .reg_offset = 0, .mask = TWL6040_PLUGINT | TWL6040_UNPLUGINT, },
620 { .reg_offset = 0, .mask = TWL6040_HOOKINT, },
621 { .reg_offset = 0, .mask = TWL6040_HFINT, },
622 { .reg_offset = 0, .mask = TWL6040_VIBINT, },
623 { .reg_offset = 0, .mask = TWL6040_READYINT, },
624};
625
626static struct regmap_irq_chip twl6040_irq_chip = {
627 .name = "twl6040",
628 .irqs = twl6040_irqs,
629 .num_irqs = ARRAY_SIZE(twl6040_irqs),
630
631 .num_regs = 1,
632 .status_base = TWL6040_REG_INTID,
633 .mask_base = TWL6040_REG_INTMR,
634};
635
612b95cd
GKH		 636static int twl6040_probe(struct i2c_client *client,
637 const struct i2c_device_id *id)
8eaeb939 638{
37e13cec 639 struct device_node *node = client->dev.of_node;
f19b2823
MLC		 640 struct twl6040 *twl6040;
641 struct mfd_cell *cell = NULL;
1f01d60e 642 int irq, ret, children = 0;
f19b2823 643
df04b624
PU		 644 if (!node) {
645 dev_err(&client->dev, "of node is missing\n");
f19b2823
MLC		 646 return -EINVAL;
647 }
648
d20e1d21 649 /* In order to operate correctly we need valid interrupt config */
6712419d 650 if (!client->irq) {
8eaeb939 651 dev_err(&client->dev, "Invalid IRQ configuration\n");
d20e1d21
PU		 652 return -EINVAL;
653 }
654
8eaeb939
PU		 655 twl6040 = devm_kzalloc(&client->dev, sizeof(struct twl6040),
656 GFP_KERNEL);
ecc8fa1c
PU		 657 if (!twl6040)
658 return -ENOMEM;
8eaeb939 659
bbf6adc1 660 twl6040->regmap = devm_regmap_init_i2c(client, &twl6040_regmap_config);
ecc8fa1c
PU		 661 if (IS_ERR(twl6040->regmap))
662 return PTR_ERR(twl6040->regmap);
f19b2823 663
8eaeb939 664 i2c_set_clientdata(client, twl6040);
f19b2823 665
68bab866
PU		 666 twl6040->clk32k = devm_clk_get(&client->dev, "clk32k");
667 if (IS_ERR(twl6040->clk32k)) {
75c08f17
TL		 668 if (PTR_ERR(twl6040->clk32k) == -EPROBE_DEFER)
669 return -EPROBE_DEFER;
0a58da1e 670 dev_dbg(&client->dev, "clk32k is not handled\n");
68bab866
PU		 671 twl6040->clk32k = NULL;
672 }
673
0a58da1e
PU		 674 twl6040->mclk = devm_clk_get(&client->dev, "mclk");
675 if (IS_ERR(twl6040->mclk)) {
676 if (PTR_ERR(twl6040->mclk) == -EPROBE_DEFER)
677 return -EPROBE_DEFER;
678 dev_dbg(&client->dev, "mclk is not handled\n");
679 twl6040->mclk = NULL;
680 }
681
5af7df6b
PU		 682 twl6040->supplies[0].supply = "vio";
683 twl6040->supplies[1].supply = "v2v1";
990810b0 684 ret = devm_regulator_bulk_get(&client->dev, TWL6040_NUM_SUPPLIES,
37aefe9f 685 twl6040->supplies);
5af7df6b
PU		 686 if (ret != 0) {
687 dev_err(&client->dev, "Failed to get supplies: %d\n", ret);
501d609a 688 return ret;
5af7df6b
PU		 689 }
690
691 ret = regulator_bulk_enable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
692 if (ret != 0) {
693 dev_err(&client->dev, "Failed to enable supplies: %d\n", ret);
501d609a 694 return ret;
5af7df6b
PU		 695 }
696
8eaeb939
PU		 697 twl6040->dev = &client->dev;
698 twl6040->irq = client->irq;
f19b2823
MLC		 699
700 mutex_init(&twl6040->mutex);
f19b2823
MLC		 701 init_completion(&twl6040->ready);
702
006cea3a
PU		 703 regmap_register_patch(twl6040->regmap, twl6040_patch,
704 ARRAY_SIZE(twl6040_patch));
705
f19b2823 706 twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
89d68998
FV		 707 if (twl6040->rev < 0) {
708 dev_err(&client->dev, "Failed to read revision register: %d\n",
709 twl6040->rev);
f2b86781 710 ret = twl6040->rev;
89d68998
FV		 711 goto gpio_err;
712 }
f19b2823 713
77f63e06 714 /* ERRATA: Automatic power-up is not possible in ES1.0 */
df04b624
PU		 715 if (twl6040_get_revid(twl6040) > TWL6040_REV_ES1_0)
716 twl6040->audpwron = of_get_named_gpio(node,
717 "ti,audpwron-gpio", 0);
718 else
77f63e06
PU		 719 twl6040->audpwron = -EINVAL;
720
f19b2823 721 if (gpio_is_valid(twl6040->audpwron)) {
990810b0 722 ret = devm_gpio_request_one(&client->dev, twl6040->audpwron,
37aefe9f 723 GPIOF_OUT_INIT_LOW, "audpwron");
f19b2823 724 if (ret)
5af7df6b 725 goto gpio_err;
02d02728
PU		 726
727 /* Clear any pending interrupt */
728 twl6040_reg_read(twl6040, TWL6040_REG_INTID);
f19b2823
MLC		 729 }
730
37aefe9f 731 ret = regmap_add_irq_chip(twl6040->regmap, twl6040->irq, IRQF_ONESHOT,
c06f308a 732 0, &twl6040_irq_chip, &twl6040->irq_data);
ab7edb14 733 if (ret < 0)
990810b0 734 goto gpio_err;
d20e1d21 735
ab7edb14 736 twl6040->irq_ready = regmap_irq_get_virq(twl6040->irq_data,
37aefe9f 737 TWL6040_IRQ_READY);
ab7edb14 738 twl6040->irq_th = regmap_irq_get_virq(twl6040->irq_data,
37aefe9f 739 TWL6040_IRQ_TH);
ab7edb14 740
990810b0 741 ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_ready, NULL,
37aefe9f
PU		 742 twl6040_readyint_handler, IRQF_ONESHOT,
743 "twl6040_irq_ready", twl6040);
d20e1d21 744 if (ret) {
1ac96265
PU		 745 dev_err(twl6040->dev, "READY IRQ request failed: %d\n", ret);
746 goto readyirq_err;
747 }
748
990810b0 749 ret = devm_request_threaded_irq(twl6040->dev, twl6040->irq_th, NULL,
37aefe9f
PU		 750 twl6040_thint_handler, IRQF_ONESHOT,
751 "twl6040_irq_th", twl6040);
1ac96265
PU		 752 if (ret) {
753 dev_err(twl6040->dev, "Thermal IRQ request failed: %d\n", ret);
fc5ee96f 754 goto readyirq_err;
f19b2823
MLC		 755 }
756
1f01d60e
PU		 757 /*
758 * The main functionality of twl6040 to provide audio on OMAP4+ systems.
759 * We can add the ASoC codec child whenever this driver has been loaded.
1f01d60e 760 */
ab7edb14 761 irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_PLUG);
1f01d60e
PU		 762 cell = &twl6040->cells[children];
763 cell->name = "twl6040-codec";
764 twl6040_codec_rsrc[0].start = irq;
765 twl6040_codec_rsrc[0].end = irq;
766 cell->resources = twl6040_codec_rsrc;
767 cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
1f01d60e 768 children++;
f19b2823 769
df04b624
PU		 770 /* Vibra input driver support */
771 if (twl6040_has_vibra(node)) {
ab7edb14 772 irq = regmap_irq_get_virq(twl6040->irq_data, TWL6040_IRQ_VIB);
0f962ae2 773
f19b2823
MLC		 774 cell = &twl6040->cells[children];
775 cell->name = "twl6040-vibra";
0f962ae2
PU		 776 twl6040_vibra_rsrc[0].start = irq;
777 twl6040_vibra_rsrc[0].end = irq;
778 cell->resources = twl6040_vibra_rsrc;
779 cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
f19b2823
MLC		 780 children++;
781 }
782
df04b624
PU		 783 /* GPO support */
784 cell = &twl6040->cells[children];
785 cell->name = "twl6040-gpo";
786 children++;
5cbe786a 787
0133d323
PU		 788 /* PDM clock support */
789 cell = &twl6040->cells[children];
790 cell->name = "twl6040-pdmclk";
791 children++;
792
c7f9129d
PU		 793 /* The chip is powered down so mark regmap to cache only and dirty */
794 regcache_cache_only(twl6040->regmap, true);
795 regcache_mark_dirty(twl6040->regmap);
796
1f01d60e 797 ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
55692af5 798 NULL, 0, NULL);
1f01d60e 799 if (ret)
fc5ee96f 800 goto readyirq_err;
f19b2823
MLC		 801
802 return 0;
803
1ac96265 804readyirq_err:
ab7edb14 805 regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
5af7df6b
PU		 806gpio_err:
807 regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
f19b2823
MLC		 808 return ret;
809}
810
612b95cd 811static int twl6040_remove(struct i2c_client *client)
f19b2823 812{
8eaeb939 813 struct twl6040 *twl6040 = i2c_get_clientdata(client);
f19b2823
MLC		 814
815 if (twl6040->power_count)
816 twl6040_power(twl6040, 0);
817
ab7edb14 818 regmap_del_irq_chip(twl6040->irq, twl6040->irq_data);
f19b2823 819
8eaeb939 820 mfd_remove_devices(&client->dev);
f19b2823 821
5af7df6b 822 regulator_bulk_disable(TWL6040_NUM_SUPPLIES, twl6040->supplies);
5af7df6b 823
f19b2823
MLC		 824 return 0;
825}
826
8eaeb939
PU		 827static const struct i2c_device_id twl6040_i2c_id[] = {
828 { "twl6040", 0, },
1fc74aef 829 { "twl6041", 0, },
8eaeb939
PU		 830 { },
831};
832MODULE_DEVICE_TABLE(i2c, twl6040_i2c_id);
833
834static struct i2c_driver twl6040_driver = {
835 .driver = {
836 .name = "twl6040",
8eaeb939 837 },
f19b2823 838 .probe = twl6040_probe,
612b95cd 839 .remove = twl6040_remove,
8eaeb939 840 .id_table = twl6040_i2c_id,
f19b2823
MLC		 841};
842
8eaeb939 843module_i2c_driver(twl6040_driver);
f19b2823
MLC		 844
845MODULE_DESCRIPTION("TWL6040 MFD");
846MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
847MODULE_AUTHOR("Jorge Eduardo Candelaria <jorge.candelaria@ti.com>");
848MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)