[linux-2.6-block.git] / drivers / mfd / twl4030-power.c

/*
 * linux/drivers/i2c/chips/twl4030-power.c
 *
 * Handle TWL4030 Power initialization
 *
 * Copyright (C) 2008 Nokia Corporation
 * Copyright (C) 2006 Texas Instruments, Inc
 *
 * Written by 	Kalle Jokiniemi
 *		Peter De Schrijver <peter.de-schrijver@nokia.com>
 * Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License. See the file "COPYING" in the main directory of this
 * archive for more details.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/module.h>
#include <linux/pm.h>
#include <linux/i2c/twl.h>
#include <linux/platform_device.h>
#include <linux/of.h>

#include <asm/mach-types.h>

static u8 twl4030_start_script_address = 0x2b;

#define PWR_P1_SW_EVENTS	0x10
#define PWR_DEVOFF		(1 << 0)
#define SEQ_OFFSYNC		(1 << 0)

#define PHY_TO_OFF_PM_MASTER(p)		(p - 0x36)
#define PHY_TO_OFF_PM_RECEIVER(p)	(p - 0x5b)

/* resource - hfclk */
#define R_HFCLKOUT_DEV_GRP 	PHY_TO_OFF_PM_RECEIVER(0xe6)

/* PM events */
#define R_P1_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x46)
#define R_P2_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x47)
#define R_P3_SW_EVENTS		PHY_TO_OFF_PM_MASTER(0x48)
#define R_CFG_P1_TRANSITION	PHY_TO_OFF_PM_MASTER(0x36)
#define R_CFG_P2_TRANSITION	PHY_TO_OFF_PM_MASTER(0x37)
#define R_CFG_P3_TRANSITION	PHY_TO_OFF_PM_MASTER(0x38)

#define LVL_WAKEUP	0x08

#define ENABLE_WARMRESET (1<<4)

#define END_OF_SCRIPT		0x3f

#define R_SEQ_ADD_A2S		PHY_TO_OFF_PM_MASTER(0x55)
#define R_SEQ_ADD_S2A12		PHY_TO_OFF_PM_MASTER(0x56)
#define	R_SEQ_ADD_S2A3		PHY_TO_OFF_PM_MASTER(0x57)
#define	R_SEQ_ADD_WARM		PHY_TO_OFF_PM_MASTER(0x58)
#define R_MEMORY_ADDRESS	PHY_TO_OFF_PM_MASTER(0x59)
#define R_MEMORY_DATA		PHY_TO_OFF_PM_MASTER(0x5a)

/* resource configuration registers
   <RESOURCE>_DEV_GRP   at address 'n+0'
   <RESOURCE>_TYPE      at address 'n+1'
   <RESOURCE>_REMAP     at address 'n+2'
   <RESOURCE>_DEDICATED at address 'n+3'
*/
#define DEV_GRP_OFFSET		0
#define TYPE_OFFSET		1
#define REMAP_OFFSET		2
#define DEDICATED_OFFSET	3

/* Bit positions in the registers */

/* <RESOURCE>_DEV_GRP */
#define DEV_GRP_SHIFT		5
#define DEV_GRP_MASK		(7 << DEV_GRP_SHIFT)

/* <RESOURCE>_TYPE */
#define TYPE_SHIFT		0
#define TYPE_MASK		(7 << TYPE_SHIFT)
#define TYPE2_SHIFT		3
#define TYPE2_MASK		(3 << TYPE2_SHIFT)

/* <RESOURCE>_REMAP */
#define SLEEP_STATE_SHIFT	0
#define SLEEP_STATE_MASK	(0xf << SLEEP_STATE_SHIFT)
#define OFF_STATE_SHIFT		4
#define OFF_STATE_MASK		(0xf << OFF_STATE_SHIFT)

static u8 res_config_addrs[] = {
	[RES_VAUX1]	= 0x17,
	[RES_VAUX2]	= 0x1b,
	[RES_VAUX3]	= 0x1f,
	[RES_VAUX4]	= 0x23,
	[RES_VMMC1]	= 0x27,
	[RES_VMMC2]	= 0x2b,
	[RES_VPLL1]	= 0x2f,
	[RES_VPLL2]	= 0x33,
	[RES_VSIM]	= 0x37,
	[RES_VDAC]	= 0x3b,
	[RES_VINTANA1]	= 0x3f,
	[RES_VINTANA2]	= 0x43,
	[RES_VINTDIG]	= 0x47,
	[RES_VIO]	= 0x4b,
	[RES_VDD1]	= 0x55,
	[RES_VDD2]	= 0x63,
	[RES_VUSB_1V5]	= 0x71,
	[RES_VUSB_1V8]	= 0x74,
	[RES_VUSB_3V1]	= 0x77,
	[RES_VUSBCP]	= 0x7a,
	[RES_REGEN]	= 0x7f,
	[RES_NRES_PWRON] = 0x82,
	[RES_CLKEN]	= 0x85,
	[RES_SYSEN]	= 0x88,
	[RES_HFCLKOUT]	= 0x8b,
	[RES_32KCLKOUT]	= 0x8e,
	[RES_RESET]	= 0x91,
	[RES_MAIN_REF]	= 0x94,
};

static int twl4030_write_script_byte(u8 address, u8 byte)
{
	int err;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
	if (err)
		goto out;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
out:
	return err;
}

static int twl4030_write_script_ins(u8 address, u16 pmb_message,
					   u8 delay, u8 next)
{
	int err;

	address *= 4;
	err = twl4030_write_script_byte(address++, pmb_message >> 8);
	if (err)
		goto out;
	err = twl4030_write_script_byte(address++, pmb_message & 0xff);
	if (err)
		goto out;
	err = twl4030_write_script_byte(address++, delay);
	if (err)
		goto out;
	err = twl4030_write_script_byte(address++, next);
out:
	return err;
}

static int twl4030_write_script(u8 address, struct twl4030_ins *script,
				       int len)
{
	int err = -EINVAL;

	for (; len; len--, address++, script++) {
		if (len == 1) {
			err = twl4030_write_script_ins(address,
						script->pmb_message,
						script->delay,
						END_OF_SCRIPT);
			if (err)
				break;
		} else {
			err = twl4030_write_script_ins(address,
						script->pmb_message,
						script->delay,
						address + 1);
			if (err)
				break;
		}
	}
	return err;
}

static int twl4030_config_wakeup3_sequence(u8 address)
{
	int err;
	u8 data;

	/* Set SLEEP to ACTIVE SEQ address for P3 */
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
	if (err)
		goto out;

	/* P3 LVL_WAKEUP should be on LEVEL */
	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
	if (err)
		goto out;
	data |= LVL_WAKEUP;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
out:
	if (err)
		pr_err("TWL4030 wakeup sequence for P3 config error\n");
	return err;
}

static int twl4030_config_wakeup12_sequence(u8 address)
{
	int err = 0;
	u8 data;

	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
	if (err)
		goto out;

	/* P1/P2 LVL_WAKEUP should be on LEVEL */
	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	data |= LVL_WAKEUP;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	data |= LVL_WAKEUP;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	if (machine_is_omap_3430sdp() || machine_is_omap_ldp()) {
		/* Disabling AC charger effect on sleep-active transitions */
		err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
				      R_CFG_P1_TRANSITION);
		if (err)
			goto out;
		data &= ~(1<<1);
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
				       R_CFG_P1_TRANSITION);
		if (err)
			goto out;
	}

out:
	if (err)
		pr_err("TWL4030 wakeup sequence for P1 and P2" \
			"config error\n");
	return err;
}

static int twl4030_config_sleep_sequence(u8 address)
{
	int err;

	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);

	if (err)
		pr_err("TWL4030 sleep sequence config error\n");

	return err;
}

static int twl4030_config_warmreset_sequence(u8 address)
{
	int err;
	u8 rd_data;

	/* Set WARM RESET SEQ address for P1 */
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
	if (err)
		goto out;

	/* P1/P2/P3 enable WARMRESET */
	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	rd_data |= ENABLE_WARMRESET;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
	if (err)
		goto out;

	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	rd_data |= ENABLE_WARMRESET;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
	if (err)
		goto out;

	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
	if (err)
		goto out;

	rd_data |= ENABLE_WARMRESET;
	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
out:
	if (err)
		pr_err("TWL4030 warmreset seq config error\n");
	return err;
}

static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
{
	int rconfig_addr;
	int err;
	u8 type;
	u8 grp;
	u8 remap;

	if (rconfig->resource > TOTAL_RESOURCES) {
		pr_err("TWL4030 Resource %d does not exist\n",
			rconfig->resource);
		return -EINVAL;
	}

	rconfig_addr = res_config_addrs[rconfig->resource];

	/* Set resource group */
	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
			      rconfig_addr + DEV_GRP_OFFSET);
	if (err) {
		pr_err("TWL4030 Resource %d group could not be read\n",
			rconfig->resource);
		return err;
	}

	if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
		grp &= ~DEV_GRP_MASK;
		grp |= rconfig->devgroup << DEV_GRP_SHIFT;
		err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
				       grp, rconfig_addr + DEV_GRP_OFFSET);
		if (err < 0) {
			pr_err("TWL4030 failed to program devgroup\n");
			return err;
		}
	}

	/* Set resource types */
	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
				rconfig_addr + TYPE_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 Resource %d type could not be read\n",
			rconfig->resource);
		return err;
	}

	if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
		type &= ~TYPE_MASK;
		type |= rconfig->type << TYPE_SHIFT;
	}

	if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
		type &= ~TYPE2_MASK;
		type |= rconfig->type2 << TYPE2_SHIFT;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
				type, rconfig_addr + TYPE_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 failed to program resource type\n");
		return err;
	}

	/* Set remap states */
	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
			      rconfig_addr + REMAP_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 Resource %d remap could not be read\n",
			rconfig->resource);
		return err;
	}

	if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
		remap &= ~OFF_STATE_MASK;
		remap |= rconfig->remap_off << OFF_STATE_SHIFT;
	}

	if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
		remap &= ~SLEEP_STATE_MASK;
		remap |= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
			       remap,
			       rconfig_addr + REMAP_OFFSET);
	if (err < 0) {
		pr_err("TWL4030 failed to program remap\n");
		return err;
	}

	return 0;
}

static int load_twl4030_script(struct twl4030_script *tscript,
	       u8 address)
{
	int err;
	static int order;

	/* Make sure the script isn't going beyond last valid address (0x3f) */
	if ((address + tscript->size) > END_OF_SCRIPT) {
		pr_err("TWL4030 scripts too big error\n");
		return -EINVAL;
	}

	err = twl4030_write_script(address, tscript->script, tscript->size);
	if (err)
		goto out;

	if (tscript->flags & TWL4030_WRST_SCRIPT) {
		err = twl4030_config_warmreset_sequence(address);
		if (err)
			goto out;
	}
	if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
		/* Reset any existing sleep script to avoid hangs on reboot */
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_A2S);
		if (err)
			goto out;

		err = twl4030_config_wakeup12_sequence(address);
		if (err)
			goto out;
		order = 1;
	}
	if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
		err = twl4030_config_wakeup3_sequence(address);
		if (err)
			goto out;
	}
	if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
		if (!order)
			pr_warning("TWL4030: Bad order of scripts (sleep "\
					"script before wakeup) Leads to boot"\
					"failure on some boards\n");
		err = twl4030_config_sleep_sequence(address);
	}
out:
	return err;
}

int twl4030_remove_script(u8 flags)
{
	int err = 0;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err) {
		pr_err("twl4030: unable to unlock PROTECT_KEY\n");
		return err;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err) {
		pr_err("twl4030: unable to unlock PROTECT_KEY\n");
		return err;
	}

	if (flags & TWL4030_WRST_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_WARM);
		if (err)
			return err;
	}
	if (flags & TWL4030_WAKEUP12_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_S2A12);
		if (err)
			return err;
	}
	if (flags & TWL4030_WAKEUP3_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_S2A3);
		if (err)
			return err;
	}
	if (flags & TWL4030_SLEEP_SCRIPT) {
		err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
				       R_SEQ_ADD_A2S);
		if (err)
			return err;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err)
		pr_err("TWL4030 Unable to relock registers\n");

	return err;
}

static int twl4030_power_configure_scripts(struct twl4030_power_data *pdata)
{
	int err;
	int i;
	u8 address = twl4030_start_script_address;

	for (i = 0; i < pdata->num; i++) {
		err = load_twl4030_script(pdata->scripts[i], address);
		if (err)
			return err;
		address += pdata->scripts[i]->size;
	}

	return 0;
}

static int twl4030_power_configure_resources(struct twl4030_power_data *pdata)
{
	struct twl4030_resconfig *resconfig = pdata->resource_config;
	int err;

	if (resconfig) {
		while (resconfig->resource) {
			err = twl4030_configure_resource(resconfig);
			if (err)
				return err;
			resconfig++;
		}
	}

	return 0;
}

/*
 * In master mode, start the power off sequence.
 * After a successful execution, TWL shuts down the power to the SoC
 * and all peripherals connected to it.
 */
void twl4030_power_off(void)
{
	int err;

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
			       TWL4030_PM_MASTER_P1_SW_EVENTS);
	if (err)
		pr_err("TWL4030 Unable to power off\n");
}

static bool twl4030_power_use_poweroff(struct twl4030_power_data *pdata,
					struct device_node *node)
{
	if (pdata && pdata->use_poweroff)
		return true;

	if (of_property_read_bool(node, "ti,use_poweroff"))
		return true;

	return false;
}

static int twl4030_power_probe(struct platform_device *pdev)
{
	struct twl4030_power_data *pdata = dev_get_platdata(&pdev->dev);
	struct device_node *node = pdev->dev.of_node;
	int err = 0;
	int err2 = 0;
	u8 val;

	if (!pdata && !node) {
		dev_err(&pdev->dev, "Platform data is missing\n");
		return -EINVAL;
	}

	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	err |= twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
			       TWL4030_PM_MASTER_KEY_CFG2,
			       TWL4030_PM_MASTER_PROTECT_KEY);

	if (err) {
		pr_err("TWL4030 Unable to unlock registers\n");
		return err;
	}

	if (pdata) {
		/* TODO: convert to device tree */
		err = twl4030_power_configure_scripts(pdata);
		if (err) {
			pr_err("TWL4030 failed to load scripts\n");
			goto relock;
		}
		err = twl4030_power_configure_resources(pdata);
		if (err) {
			pr_err("TWL4030 failed to configure resource\n");
			goto relock;
		}
	}

	/* Board has to be wired properly to use this feature */
	if (twl4030_power_use_poweroff(pdata, node) && !pm_power_off) {
		/* Default for SEQ_OFFSYNC is set, lets ensure this */
		err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
				      TWL4030_PM_MASTER_CFG_P123_TRANSITION);
		if (err) {
			pr_warning("TWL4030 Unable to read registers\n");

		} else if (!(val & SEQ_OFFSYNC)) {
			val |= SEQ_OFFSYNC;
			err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
					TWL4030_PM_MASTER_CFG_P123_TRANSITION);
			if (err) {
				pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
				goto relock;
			}
		}

		pm_power_off = twl4030_power_off;
	}

relock:
	err2 = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
			       TWL4030_PM_MASTER_PROTECT_KEY);
	if (err2) {
		pr_err("TWL4030 Unable to relock registers\n");
		return err2;
	}

	return err;
}

static int twl4030_power_remove(struct platform_device *pdev)
{
	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id twl4030_power_of_match[] = {
	{.compatible = "ti,twl4030-power", },
	{ },
};
MODULE_DEVICE_TABLE(of, twl4030_power_of_match);
#endif

static struct platform_driver twl4030_power_driver = {
	.driver = {
		.name	= "twl4030_power",
		.owner	= THIS_MODULE,
		.of_match_table = of_match_ptr(twl4030_power_of_match),
	},
	.probe		= twl4030_power_probe,
	.remove		= twl4030_power_remove,
};

module_platform_driver(twl4030_power_driver);

MODULE_AUTHOR("Nokia Corporation");
MODULE_AUTHOR("Texas Instruments, Inc.");
MODULE_DESCRIPTION("Power management for TWL4030");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:twl4030_power");
Commit	Line	Data
ebf0bd36 AK	1	/*
	2	* linux/drivers/i2c/chips/twl4030-power.c
	3	*
	4	* Handle TWL4030 Power initialization
	5	*
	6	* Copyright (C) 2008 Nokia Corporation
	7	* Copyright (C) 2006 Texas Instruments, Inc
	8	*
	9	* Written by Kalle Jokiniemi
	10	* Peter De Schrijver <peter.de-schrijver@nokia.com>
	11	* Several fixes by Amit Kucheria <amit.kucheria@verdurent.com>
	12	*
	13	* This file is subject to the terms and conditions of the GNU General
	14	* Public License. See the file "COPYING" in the main directory of this
	15	* archive for more details.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	25	*/
	26
	27	#include <linux/module.h>
	28	#include <linux/pm.h>
b07682b6	29	#include <linux/i2c/twl.h>
ebf0bd36	30	#include <linux/platform_device.h>
b0fc1da4	31	#include <linux/of.h>
ebf0bd36 AK	32
	33	#include <asm/mach-types.h>
	34
	35	static u8 twl4030_start_script_address = 0x2b;
	36
	37	#define PWR_P1_SW_EVENTS 0x10
26cc3ab9 IG	38	#define PWR_DEVOFF (1 << 0)
26cc3ab9 IG	39	#define SEQ_OFFSYNC (1 << 0)
ebf0bd36 AK	40
	41	#define PHY_TO_OFF_PM_MASTER(p) (p - 0x36)
	42	#define PHY_TO_OFF_PM_RECEIVER(p) (p - 0x5b)
	43
	44	/* resource - hfclk */
	45	#define R_HFCLKOUT_DEV_GRP PHY_TO_OFF_PM_RECEIVER(0xe6)
	46
	47	/* PM events */
	48	#define R_P1_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x46)
	49	#define R_P2_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x47)
	50	#define R_P3_SW_EVENTS PHY_TO_OFF_PM_MASTER(0x48)
	51	#define R_CFG_P1_TRANSITION PHY_TO_OFF_PM_MASTER(0x36)
	52	#define R_CFG_P2_TRANSITION PHY_TO_OFF_PM_MASTER(0x37)
	53	#define R_CFG_P3_TRANSITION PHY_TO_OFF_PM_MASTER(0x38)
	54
	55	#define LVL_WAKEUP 0x08
	56
	57	#define ENABLE_WARMRESET (1<<4)
	58
	59	#define END_OF_SCRIPT 0x3f
	60
	61	#define R_SEQ_ADD_A2S PHY_TO_OFF_PM_MASTER(0x55)
	62	#define R_SEQ_ADD_S2A12 PHY_TO_OFF_PM_MASTER(0x56)
	63	#define R_SEQ_ADD_S2A3 PHY_TO_OFF_PM_MASTER(0x57)
	64	#define R_SEQ_ADD_WARM PHY_TO_OFF_PM_MASTER(0x58)
	65	#define R_MEMORY_ADDRESS PHY_TO_OFF_PM_MASTER(0x59)
	66	#define R_MEMORY_DATA PHY_TO_OFF_PM_MASTER(0x5a)
	67
890463f0 AK	68	/* resource configuration registers
	69	<RESOURCE>_DEV_GRP at address 'n+0'
	70	<RESOURCE>_TYPE at address 'n+1'
	71	<RESOURCE>_REMAP at address 'n+2'
	72	<RESOURCE>_DEDICATED at address 'n+3'
	73	*/
e97d1546	74	#define DEV_GRP_OFFSET 0
ebf0bd36	75	#define TYPE_OFFSET 1
b4ead61e AK	76	#define REMAP_OFFSET 2
b4ead61e AK	77	#define DEDICATED_OFFSET 3
ebf0bd36	78
e97d1546	79	/* Bit positions in the registers */
890463f0 AK	80
890463f0 AK	81	/* <RESOURCE>_DEV_GRP */
e97d1546 AK	82	#define DEV_GRP_SHIFT 5
e97d1546 AK	83	#define DEV_GRP_MASK (7 << DEV_GRP_SHIFT)
890463f0 AK	84
890463f0 AK	85	/* <RESOURCE>_TYPE */
ebf0bd36 AK	86	#define TYPE_SHIFT 0
	87	#define TYPE_MASK (7 << TYPE_SHIFT)
	88	#define TYPE2_SHIFT 3
	89	#define TYPE2_MASK (3 << TYPE2_SHIFT)
	90
b4ead61e AK	91	/* <RESOURCE>_REMAP */
	92	#define SLEEP_STATE_SHIFT 0
	93	#define SLEEP_STATE_MASK (0xf << SLEEP_STATE_SHIFT)
	94	#define OFF_STATE_SHIFT 4
	95	#define OFF_STATE_MASK (0xf << OFF_STATE_SHIFT)
	96
ebf0bd36 AK	97	static u8 res_config_addrs[] = {
	98	[RES_VAUX1] = 0x17,
	99	[RES_VAUX2] = 0x1b,
	100	[RES_VAUX3] = 0x1f,
	101	[RES_VAUX4] = 0x23,
	102	[RES_VMMC1] = 0x27,
	103	[RES_VMMC2] = 0x2b,
	104	[RES_VPLL1] = 0x2f,
	105	[RES_VPLL2] = 0x33,
	106	[RES_VSIM] = 0x37,
	107	[RES_VDAC] = 0x3b,
	108	[RES_VINTANA1] = 0x3f,
	109	[RES_VINTANA2] = 0x43,
	110	[RES_VINTDIG] = 0x47,
	111	[RES_VIO] = 0x4b,
	112	[RES_VDD1] = 0x55,
	113	[RES_VDD2] = 0x63,
	114	[RES_VUSB_1V5] = 0x71,
	115	[RES_VUSB_1V8] = 0x74,
	116	[RES_VUSB_3V1] = 0x77,
	117	[RES_VUSBCP] = 0x7a,
	118	[RES_REGEN] = 0x7f,
	119	[RES_NRES_PWRON] = 0x82,
	120	[RES_CLKEN] = 0x85,
	121	[RES_SYSEN] = 0x88,
	122	[RES_HFCLKOUT] = 0x8b,
	123	[RES_32KCLKOUT] = 0x8e,
	124	[RES_RESET] = 0x91,
d7ac829f	125	[RES_MAIN_REF] = 0x94,
ebf0bd36 AK	126	};
ebf0bd36 AK	127
f791be49	128	static int twl4030_write_script_byte(u8 address, u8 byte)
ebf0bd36 AK	129	{
	130	int err;
	131
4850f124	132	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_MEMORY_ADDRESS);
ebf0bd36 AK	133	if (err)
ebf0bd36 AK	134	goto out;
4850f124	135	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, byte, R_MEMORY_DATA);
ebf0bd36 AK	136	out:
	137	return err;
	138	}
	139
f791be49	140	static int twl4030_write_script_ins(u8 address, u16 pmb_message,
ebf0bd36 AK	141	u8 delay, u8 next)
	142	{
	143	int err;
	144
	145	address *= 4;
	146	err = twl4030_write_script_byte(address++, pmb_message >> 8);
	147	if (err)
	148	goto out;
	149	err = twl4030_write_script_byte(address++, pmb_message & 0xff);
	150	if (err)
	151	goto out;
	152	err = twl4030_write_script_byte(address++, delay);
	153	if (err)
	154	goto out;
	155	err = twl4030_write_script_byte(address++, next);
	156	out:
	157	return err;
	158	}
	159
f791be49	160	static int twl4030_write_script(u8 address, struct twl4030_ins *script,
ebf0bd36 AK	161	int len)
ebf0bd36 AK	162	{
f65e9eac	163	int err = -EINVAL;
ebf0bd36 AK	164
	165	for (; len; len--, address++, script++) {
	166	if (len == 1) {
	167	err = twl4030_write_script_ins(address,
	168	script->pmb_message,
	169	script->delay,
	170	END_OF_SCRIPT);
	171	if (err)
	172	break;
	173	} else {
	174	err = twl4030_write_script_ins(address,
	175	script->pmb_message,
	176	script->delay,
	177	address + 1);
	178	if (err)
	179	break;
	180	}
	181	}
	182	return err;
	183	}
	184
f791be49	185	static int twl4030_config_wakeup3_sequence(u8 address)
ebf0bd36 AK	186	{
	187	int err;
	188	u8 data;
	189
	190	/* Set SLEEP to ACTIVE SEQ address for P3 */
4850f124	191	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A3);
ebf0bd36 AK	192	if (err)
	193	goto out;
	194
	195	/* P3 LVL_WAKEUP should be on LEVEL */
4850f124	196	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P3_SW_EVENTS);
ebf0bd36 AK	197	if (err)
	198	goto out;
	199	data \|= LVL_WAKEUP;
4850f124	200	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P3_SW_EVENTS);
ebf0bd36 AK	201	out:
	202	if (err)
	203	pr_err("TWL4030 wakeup sequence for P3 config error\n");
	204	return err;
	205	}
	206
f791be49	207	static int twl4030_config_wakeup12_sequence(u8 address)
ebf0bd36 AK	208	{
	209	int err = 0;
	210	u8 data;
	211
	212	/* Set SLEEP to ACTIVE SEQ address for P1 and P2 */
4850f124	213	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_S2A12);
ebf0bd36 AK	214	if (err)
	215	goto out;
	216
	217	/* P1/P2 LVL_WAKEUP should be on LEVEL */
4850f124	218	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P1_SW_EVENTS);
ebf0bd36 AK	219	if (err)
	220	goto out;
	221
	222	data \|= LVL_WAKEUP;
4850f124	223	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P1_SW_EVENTS);
ebf0bd36 AK	224	if (err)
	225	goto out;
	226
4850f124	227	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data, R_P2_SW_EVENTS);
ebf0bd36 AK	228	if (err)
	229	goto out;
	230
	231	data \|= LVL_WAKEUP;
4850f124	232	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data, R_P2_SW_EVENTS);
ebf0bd36 AK	233	if (err)
	234	goto out;
	235
	236	if (machine_is_omap_3430sdp() \|\| machine_is_omap_ldp()) {
	237	/* Disabling AC charger effect on sleep-active transitions */
4850f124 PU	238	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &data,
4850f124 PU	239	R_CFG_P1_TRANSITION);
ebf0bd36 AK	240	if (err)
	241	goto out;
	242	data &= ~(1<<1);
4850f124 PU	243	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, data,
4850f124 PU	244	R_CFG_P1_TRANSITION);
ebf0bd36 AK	245	if (err)
	246	goto out;
	247	}
	248
	249	out:
	250	if (err)
	251	pr_err("TWL4030 wakeup sequence for P1 and P2" \
	252	"config error\n");
	253	return err;
	254	}
	255
f791be49	256	static int twl4030_config_sleep_sequence(u8 address)
ebf0bd36 AK	257	{
	258	int err;
	259
	260	/* Set ACTIVE to SLEEP SEQ address in T2 memory*/
4850f124	261	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_A2S);
ebf0bd36 AK	262
	263	if (err)
	264	pr_err("TWL4030 sleep sequence config error\n");
	265
	266	return err;
	267	}
	268
f791be49	269	static int twl4030_config_warmreset_sequence(u8 address)
ebf0bd36 AK	270	{
	271	int err;
	272	u8 rd_data;
	273
	274	/* Set WARM RESET SEQ address for P1 */
4850f124	275	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, address, R_SEQ_ADD_WARM);
ebf0bd36 AK	276	if (err)
	277	goto out;
	278
	279	/* P1/P2/P3 enable WARMRESET */
4850f124	280	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P1_SW_EVENTS);
ebf0bd36 AK	281	if (err)
	282	goto out;
	283
	284	rd_data \|= ENABLE_WARMRESET;
4850f124	285	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P1_SW_EVENTS);
ebf0bd36 AK	286	if (err)
	287	goto out;
	288
4850f124	289	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P2_SW_EVENTS);
ebf0bd36 AK	290	if (err)
	291	goto out;
	292
	293	rd_data \|= ENABLE_WARMRESET;
4850f124	294	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P2_SW_EVENTS);
ebf0bd36 AK	295	if (err)
	296	goto out;
	297
4850f124	298	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &rd_data, R_P3_SW_EVENTS);
ebf0bd36 AK	299	if (err)
	300	goto out;
	301
	302	rd_data \|= ENABLE_WARMRESET;
4850f124	303	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, rd_data, R_P3_SW_EVENTS);
ebf0bd36 AK	304	out:
	305	if (err)
	306	pr_err("TWL4030 warmreset seq config error\n");
	307	return err;
	308	}
	309
f791be49	310	static int twl4030_configure_resource(struct twl4030_resconfig *rconfig)
ebf0bd36 AK	311	{
	312	int rconfig_addr;
	313	int err;
	314	u8 type;
	315	u8 grp;
b4ead61e	316	u8 remap;
ebf0bd36 AK	317
	318	if (rconfig->resource > TOTAL_RESOURCES) {
	319	pr_err("TWL4030 Resource %d does not exist\n",
	320	rconfig->resource);
	321	return -EINVAL;
	322	}
	323
	324	rconfig_addr = res_config_addrs[rconfig->resource];
	325
	326	/* Set resource group */
4850f124	327	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &grp,
fc7b92fc	328	rconfig_addr + DEV_GRP_OFFSET);
ebf0bd36 AK	329	if (err) {
	330	pr_err("TWL4030 Resource %d group could not be read\n",
	331	rconfig->resource);
	332	return err;
	333	}
	334
56baa667	335	if (rconfig->devgroup != TWL4030_RESCONFIG_UNDEF) {
e97d1546 AK	336	grp &= ~DEV_GRP_MASK;
e97d1546 AK	337	grp \|= rconfig->devgroup << DEV_GRP_SHIFT;
4850f124	338	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
fc7b92fc	339	grp, rconfig_addr + DEV_GRP_OFFSET);
ebf0bd36 AK	340	if (err < 0) {
	341	pr_err("TWL4030 failed to program devgroup\n");
	342	return err;
	343	}
	344	}
	345
	346	/* Set resource types */
4850f124	347	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &type,
ebf0bd36 AK	348	rconfig_addr + TYPE_OFFSET);
	349	if (err < 0) {
	350	pr_err("TWL4030 Resource %d type could not be read\n",
	351	rconfig->resource);
	352	return err;
	353	}
	354
56baa667	355	if (rconfig->type != TWL4030_RESCONFIG_UNDEF) {
ebf0bd36 AK	356	type &= ~TYPE_MASK;
	357	type \|= rconfig->type << TYPE_SHIFT;
	358	}
	359
56baa667	360	if (rconfig->type2 != TWL4030_RESCONFIG_UNDEF) {
ebf0bd36 AK	361	type &= ~TYPE2_MASK;
	362	type \|= rconfig->type2 << TYPE2_SHIFT;
	363	}
	364
4850f124	365	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
ebf0bd36 AK	366	type, rconfig_addr + TYPE_OFFSET);
	367	if (err < 0) {
	368	pr_err("TWL4030 failed to program resource type\n");
	369	return err;
	370	}
	371
b4ead61e	372	/* Set remap states */
4850f124	373	err = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &remap,
fc7b92fc	374	rconfig_addr + REMAP_OFFSET);
b4ead61e AK	375	if (err < 0) {
	376	pr_err("TWL4030 Resource %d remap could not be read\n",
	377	rconfig->resource);
	378	return err;
	379	}
	380
53cf9a60	381	if (rconfig->remap_off != TWL4030_RESCONFIG_UNDEF) {
b4ead61e AK	382	remap &= ~OFF_STATE_MASK;
	383	remap \|= rconfig->remap_off << OFF_STATE_SHIFT;
	384	}
	385
53cf9a60	386	if (rconfig->remap_sleep != TWL4030_RESCONFIG_UNDEF) {
b4ead61e	387	remap &= ~SLEEP_STATE_MASK;
1ea933f4	388	remap \|= rconfig->remap_sleep << SLEEP_STATE_SHIFT;
b4ead61e AK	389	}
b4ead61e AK	390
4850f124	391	err = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER,
fc7b92fc B	392	remap,
fc7b92fc B	393	rconfig_addr + REMAP_OFFSET);
b4ead61e AK	394	if (err < 0) {
	395	pr_err("TWL4030 failed to program remap\n");
	396	return err;
	397	}
	398
ebf0bd36 AK	399	return 0;
	400	}
	401
f791be49	402	static int load_twl4030_script(struct twl4030_script *tscript,
ebf0bd36 AK	403	u8 address)
	404	{
	405	int err;
75a74565	406	static int order;
ebf0bd36 AK	407
	408	/* Make sure the script isn't going beyond last valid address (0x3f) */
	409	if ((address + tscript->size) > END_OF_SCRIPT) {
	410	pr_err("TWL4030 scripts too big error\n");
	411	return -EINVAL;
	412	}
	413
	414	err = twl4030_write_script(address, tscript->script, tscript->size);
	415	if (err)
	416	goto out;
	417
	418	if (tscript->flags & TWL4030_WRST_SCRIPT) {
	419	err = twl4030_config_warmreset_sequence(address);
	420	if (err)
	421	goto out;
	422	}
	423	if (tscript->flags & TWL4030_WAKEUP12_SCRIPT) {
fc7d76e4 TL	424	/* Reset any existing sleep script to avoid hangs on reboot */
	425	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
	426	R_SEQ_ADD_A2S);
	427	if (err)
	428	goto out;
	429
ebf0bd36 AK	430	err = twl4030_config_wakeup12_sequence(address);
	431	if (err)
	432	goto out;
75a74565	433	order = 1;
ebf0bd36 AK	434	}
	435	if (tscript->flags & TWL4030_WAKEUP3_SCRIPT) {
	436	err = twl4030_config_wakeup3_sequence(address);
	437	if (err)
	438	goto out;
	439	}
c62dd365	440	if (tscript->flags & TWL4030_SLEEP_SCRIPT) {
1f968ff6	441	if (!order)
75a74565 AK	442	pr_warning("TWL4030: Bad order of scripts (sleep "\
	443	"script before wakeup) Leads to boot"\
	444	"failure on some boards\n");
ebf0bd36	445	err = twl4030_config_sleep_sequence(address);
c62dd365	446	}
ebf0bd36 AK	447	out:
	448	return err;
	449	}
	450
11a441ce MT	451	int twl4030_remove_script(u8 flags)
	452	{
	453	int err = 0;
	454
4850f124 PU	455	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
4850f124 PU	456	TWL4030_PM_MASTER_PROTECT_KEY);
11a441ce MT	457	if (err) {
	458	pr_err("twl4030: unable to unlock PROTECT_KEY\n");
	459	return err;
	460	}
	461
4850f124 PU	462	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
4850f124 PU	463	TWL4030_PM_MASTER_PROTECT_KEY);
11a441ce MT	464	if (err) {
	465	pr_err("twl4030: unable to unlock PROTECT_KEY\n");
	466	return err;
	467	}
	468
	469	if (flags & TWL4030_WRST_SCRIPT) {
4850f124 PU	470	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	471	R_SEQ_ADD_WARM);
11a441ce MT	472	if (err)
	473	return err;
	474	}
	475	if (flags & TWL4030_WAKEUP12_SCRIPT) {
4850f124 PU	476	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	477	R_SEQ_ADD_S2A12);
eac78a21	478	if (err)
11a441ce MT	479	return err;
	480	}
	481	if (flags & TWL4030_WAKEUP3_SCRIPT) {
4850f124 PU	482	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	483	R_SEQ_ADD_S2A3);
11a441ce MT	484	if (err)
	485	return err;
	486	}
	487	if (flags & TWL4030_SLEEP_SCRIPT) {
4850f124 PU	488	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, END_OF_SCRIPT,
4850f124 PU	489	R_SEQ_ADD_A2S);
11a441ce MT	490	if (err)
	491	return err;
	492	}
	493
4850f124 PU	494	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
4850f124 PU	495	TWL4030_PM_MASTER_PROTECT_KEY);
11a441ce MT	496	if (err)
	497	pr_err("TWL4030 Unable to relock registers\n");
	498
	499	return err;
	500	}
	501
fae01582	502	static int twl4030_power_configure_scripts(struct twl4030_power_data *pdata)
f58cb407 FV	503	{
	504	int err;
	505	int i;
	506	u8 address = twl4030_start_script_address;
	507
	508	for (i = 0; i < pdata->num; i++) {
	509	err = load_twl4030_script(pdata->scripts[i], address);
	510	if (err)
	511	return err;
	512	address += pdata->scripts[i]->size;
	513	}
	514
	515	return 0;
	516	}
	517
fae01582	518	static int twl4030_power_configure_resources(struct twl4030_power_data *pdata)
f58cb407 FV	519	{
	520	struct twl4030_resconfig *resconfig = pdata->resource_config;
	521	int err;
	522
	523	if (resconfig) {
	524	while (resconfig->resource) {
	525	err = twl4030_configure_resource(resconfig);
	526	if (err)
	527	return err;
	528	resconfig++;
	529	}
	530	}
	531
	532	return 0;
	533	}
	534
26cc3ab9 IG	535	/*
	536	* In master mode, start the power off sequence.
	537	* After a successful execution, TWL shuts down the power to the SoC
	538	* and all peripherals connected to it.
	539	*/
	540	void twl4030_power_off(void)
	541	{
	542	int err;
	543
4850f124	544	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, PWR_DEVOFF,
26cc3ab9 IG	545	TWL4030_PM_MASTER_P1_SW_EVENTS);
	546	if (err)
	547	pr_err("TWL4030 Unable to power off\n");
	548	}
	549
b0fc1da4 FV	550	static bool twl4030_power_use_poweroff(struct twl4030_power_data *pdata,
	551	struct device_node *node)
	552	{
	553	if (pdata && pdata->use_poweroff)
	554	return true;
	555
	556	if (of_property_read_bool(node, "ti,use_poweroff"))
	557	return true;
	558
	559	return false;
	560	}
	561
fae01582	562	static int twl4030_power_probe(struct platform_device *pdev)
ebf0bd36	563	{
334a41ce	564	struct twl4030_power_data *pdata = dev_get_platdata(&pdev->dev);
b0fc1da4	565	struct device_node *node = pdev->dev.of_node;
ebf0bd36	566	int err = 0;
cb3cabd6	567	int err2 = 0;
f58cb407	568	u8 val;
ebf0bd36	569
b0fc1da4 FV	570	if (!pdata && !node) {
	571	dev_err(&pdev->dev, "Platform data is missing\n");
	572	return -EINVAL;
	573	}
	574
4850f124 PU	575	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
4850f124 PU	576	TWL4030_PM_MASTER_PROTECT_KEY);
e77a4c2f FV	577	err \|= twl_i2c_write_u8(TWL_MODULE_PM_MASTER,
e77a4c2f FV	578	TWL4030_PM_MASTER_KEY_CFG2,
4850f124	579	TWL4030_PM_MASTER_PROTECT_KEY);
e77a4c2f FV	580
	581	if (err) {
	582	pr_err("TWL4030 Unable to unlock registers\n");
	583	return err;
	584	}
ebf0bd36	585
b0fc1da4 FV	586	if (pdata) {
	587	/* TODO: convert to device tree */
	588	err = twl4030_power_configure_scripts(pdata);
e77a4c2f FV	589	if (err) {
e77a4c2f FV	590	pr_err("TWL4030 failed to load scripts\n");
cb3cabd6	591	goto relock;
e77a4c2f	592	}
b0fc1da4	593	err = twl4030_power_configure_resources(pdata);
e77a4c2f FV	594	if (err) {
e77a4c2f FV	595	pr_err("TWL4030 failed to configure resource\n");
cb3cabd6	596	goto relock;
e77a4c2f	597	}
b0fc1da4	598	}
ebf0bd36	599
26cc3ab9	600	/* Board has to be wired properly to use this feature */
b0fc1da4	601	if (twl4030_power_use_poweroff(pdata, node) && !pm_power_off) {
26cc3ab9	602	/* Default for SEQ_OFFSYNC is set, lets ensure this */
4850f124	603	err = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
26cc3ab9 IG	604	TWL4030_PM_MASTER_CFG_P123_TRANSITION);
	605	if (err) {
	606	pr_warning("TWL4030 Unable to read registers\n");
	607
	608	} else if (!(val & SEQ_OFFSYNC)) {
	609	val \|= SEQ_OFFSYNC;
4850f124	610	err = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
26cc3ab9 IG	611	TWL4030_PM_MASTER_CFG_P123_TRANSITION);
	612	if (err) {
	613	pr_err("TWL4030 Unable to setup SEQ_OFFSYNC\n");
	614	goto relock;
	615	}
	616	}
	617
	618	pm_power_off = twl4030_power_off;
	619	}
	620
	621	relock:
cb3cabd6	622	err2 = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
4850f124	623	TWL4030_PM_MASTER_PROTECT_KEY);
cb3cabd6	624	if (err2) {
ebf0bd36	625	pr_err("TWL4030 Unable to relock registers\n");
cb3cabd6 FV	626	return err2;
	627	}
	628
637d6895	629	return err;
637d6895 FV	630	}
	631
	632	static int twl4030_power_remove(struct platform_device *pdev)
	633	{
	634	return 0;
ebf0bd36	635	}
637d6895	636
b0fc1da4 FV	637	#ifdef CONFIG_OF
	638	static const struct of_device_id twl4030_power_of_match[] = {
	639	{.compatible = "ti,twl4030-power", },
	640	{ },
	641	};
	642	MODULE_DEVICE_TABLE(of, twl4030_power_of_match);
	643	#endif
	644
637d6895 FV	645	static struct platform_driver twl4030_power_driver = {
	646	.driver = {
	647	.name = "twl4030_power",
	648	.owner = THIS_MODULE,
b0fc1da4	649	.of_match_table = of_match_ptr(twl4030_power_of_match),
637d6895 FV	650	},
	651	.probe = twl4030_power_probe,
	652	.remove = twl4030_power_remove,
	653	};
	654
	655	module_platform_driver(twl4030_power_driver);
	656
	657	MODULE_AUTHOR("Nokia Corporation");
	658	MODULE_AUTHOR("Texas Instruments, Inc.");
	659	MODULE_DESCRIPTION("Power management for TWL4030");
	660	MODULE_LICENSE("GPL");
	661	MODULE_ALIAS("platform:twl4030_power");