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a30d46c0 DB |
1 | /* |
2 | * twl4030-irq.c - TWL4030/TPS659x0 irq support | |
3 | * | |
4 | * Copyright (C) 2005-2006 Texas Instruments, Inc. | |
5 | * | |
6 | * Modifications to defer interrupt handling to a kernel thread: | |
7 | * Copyright (C) 2006 MontaVista Software, Inc. | |
8 | * | |
9 | * Based on tlv320aic23.c: | |
10 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> | |
11 | * | |
12 | * Code cleanup and modifications to IRQ handler. | |
13 | * by syed khasim <x0khasim@ti.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <linux/init.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/irq.h> | |
5a0e3ad6 | 33 | #include <linux/slab.h> |
a30d46c0 | 34 | |
b07682b6 | 35 | #include <linux/i2c/twl.h> |
a30d46c0 | 36 | |
b0b4a7c2 | 37 | #include "twl-core.h" |
a30d46c0 DB |
38 | |
39 | /* | |
40 | * TWL4030 IRQ handling has two stages in hardware, and thus in software. | |
41 | * The Primary Interrupt Handler (PIH) stage exposes status bits saying | |
42 | * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. | |
43 | * SIH modules are more traditional IRQ components, which support per-IRQ | |
44 | * enable/disable and trigger controls; they do most of the work. | |
45 | * | |
46 | * These chips are designed to support IRQ handling from two different | |
47 | * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status | |
48 | * and mask registers in the PIH and SIH modules. | |
49 | * | |
50 | * We set up IRQs starting at a platform-specified base, always starting | |
51 | * with PIH and the SIH for PWR_INT and then usually adding GPIO: | |
52 | * base + 0 .. base + 7 PIH | |
53 | * base + 8 .. base + 15 SIH for PWR_INT | |
54 | * base + 16 .. base + 33 SIH for GPIO | |
55 | */ | |
56 | ||
57 | /* PIH register offsets */ | |
58 | #define REG_PIH_ISR_P1 0x01 | |
59 | #define REG_PIH_ISR_P2 0x02 | |
60 | #define REG_PIH_SIR 0x03 /* for testing */ | |
61 | ||
a30d46c0 DB |
62 | /* Linux could (eventually) use either IRQ line */ |
63 | static int irq_line; | |
64 | ||
65 | struct sih { | |
66 | char name[8]; | |
67 | u8 module; /* module id */ | |
68 | u8 control_offset; /* for SIH_CTRL */ | |
69 | bool set_cor; | |
70 | ||
71 | u8 bits; /* valid in isr/imr */ | |
72 | u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ | |
73 | ||
74 | u8 edr_offset; | |
75 | u8 bytes_edr; /* bytelen of EDR */ | |
76 | ||
1920a61e IK |
77 | u8 irq_lines; /* number of supported irq lines */ |
78 | ||
a30d46c0 | 79 | /* SIR ignored -- set interrupt, for testing only */ |
35a27e8e | 80 | struct sih_irq_data { |
a30d46c0 DB |
81 | u8 isr_offset; |
82 | u8 imr_offset; | |
83 | } mask[2]; | |
84 | /* + 2 bytes padding */ | |
85 | }; | |
86 | ||
1920a61e IK |
87 | static const struct sih *sih_modules; |
88 | static int nr_sih_modules; | |
89 | ||
a30d46c0 DB |
90 | #define SIH_INITIALIZER(modname, nbits) \ |
91 | .module = TWL4030_MODULE_ ## modname, \ | |
92 | .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ | |
93 | .bits = nbits, \ | |
94 | .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ | |
95 | .edr_offset = TWL4030_ ## modname ## _EDR, \ | |
96 | .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ | |
1920a61e | 97 | .irq_lines = 2, \ |
a30d46c0 DB |
98 | .mask = { { \ |
99 | .isr_offset = TWL4030_ ## modname ## _ISR1, \ | |
100 | .imr_offset = TWL4030_ ## modname ## _IMR1, \ | |
101 | }, \ | |
102 | { \ | |
103 | .isr_offset = TWL4030_ ## modname ## _ISR2, \ | |
104 | .imr_offset = TWL4030_ ## modname ## _IMR2, \ | |
105 | }, }, | |
106 | ||
107 | /* register naming policies are inconsistent ... */ | |
108 | #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 | |
109 | #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD | |
110 | #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT | |
111 | ||
112 | ||
cbcde05e FC |
113 | /* |
114 | * Order in this table matches order in PIH_ISR. That is, | |
a30d46c0 DB |
115 | * BIT(n) in PIH_ISR is sih_modules[n]. |
116 | */ | |
1920a61e IK |
117 | /* sih_modules_twl4030 is used both in twl4030 and twl5030 */ |
118 | static const struct sih sih_modules_twl4030[6] = { | |
a30d46c0 DB |
119 | [0] = { |
120 | .name = "gpio", | |
121 | .module = TWL4030_MODULE_GPIO, | |
122 | .control_offset = REG_GPIO_SIH_CTRL, | |
123 | .set_cor = true, | |
124 | .bits = TWL4030_GPIO_MAX, | |
125 | .bytes_ixr = 3, | |
126 | /* Note: *all* of these IRQs default to no-trigger */ | |
127 | .edr_offset = REG_GPIO_EDR1, | |
128 | .bytes_edr = 5, | |
1920a61e | 129 | .irq_lines = 2, |
a30d46c0 DB |
130 | .mask = { { |
131 | .isr_offset = REG_GPIO_ISR1A, | |
132 | .imr_offset = REG_GPIO_IMR1A, | |
133 | }, { | |
134 | .isr_offset = REG_GPIO_ISR1B, | |
135 | .imr_offset = REG_GPIO_IMR1B, | |
136 | }, }, | |
137 | }, | |
138 | [1] = { | |
139 | .name = "keypad", | |
140 | .set_cor = true, | |
141 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
142 | }, | |
143 | [2] = { | |
144 | .name = "bci", | |
145 | .module = TWL4030_MODULE_INTERRUPTS, | |
146 | .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, | |
8e52e279 | 147 | .set_cor = true, |
a30d46c0 DB |
148 | .bits = 12, |
149 | .bytes_ixr = 2, | |
150 | .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, | |
151 | /* Note: most of these IRQs default to no-trigger */ | |
152 | .bytes_edr = 3, | |
1920a61e | 153 | .irq_lines = 2, |
a30d46c0 DB |
154 | .mask = { { |
155 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, | |
156 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, | |
157 | }, { | |
158 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, | |
159 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, | |
160 | }, }, | |
161 | }, | |
162 | [3] = { | |
163 | .name = "madc", | |
164 | SIH_INITIALIZER(MADC, 4) | |
165 | }, | |
166 | [4] = { | |
167 | /* USB doesn't use the same SIH organization */ | |
168 | .name = "usb", | |
169 | }, | |
170 | [5] = { | |
171 | .name = "power", | |
172 | .set_cor = true, | |
173 | SIH_INITIALIZER(INT_PWR, 8) | |
174 | }, | |
175 | /* there are no SIH modules #6 or #7 ... */ | |
176 | }; | |
177 | ||
1920a61e IK |
178 | static const struct sih sih_modules_twl5031[8] = { |
179 | [0] = { | |
180 | .name = "gpio", | |
181 | .module = TWL4030_MODULE_GPIO, | |
182 | .control_offset = REG_GPIO_SIH_CTRL, | |
183 | .set_cor = true, | |
184 | .bits = TWL4030_GPIO_MAX, | |
185 | .bytes_ixr = 3, | |
186 | /* Note: *all* of these IRQs default to no-trigger */ | |
187 | .edr_offset = REG_GPIO_EDR1, | |
188 | .bytes_edr = 5, | |
189 | .irq_lines = 2, | |
190 | .mask = { { | |
191 | .isr_offset = REG_GPIO_ISR1A, | |
192 | .imr_offset = REG_GPIO_IMR1A, | |
193 | }, { | |
194 | .isr_offset = REG_GPIO_ISR1B, | |
195 | .imr_offset = REG_GPIO_IMR1B, | |
196 | }, }, | |
197 | }, | |
198 | [1] = { | |
199 | .name = "keypad", | |
200 | .set_cor = true, | |
201 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
202 | }, | |
203 | [2] = { | |
204 | .name = "bci", | |
205 | .module = TWL5031_MODULE_INTERRUPTS, | |
206 | .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, | |
207 | .bits = 7, | |
208 | .bytes_ixr = 1, | |
209 | .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, | |
210 | /* Note: most of these IRQs default to no-trigger */ | |
211 | .bytes_edr = 2, | |
212 | .irq_lines = 2, | |
213 | .mask = { { | |
214 | .isr_offset = TWL5031_INTERRUPTS_BCIISR1, | |
215 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, | |
216 | }, { | |
217 | .isr_offset = TWL5031_INTERRUPTS_BCIISR2, | |
218 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, | |
219 | }, }, | |
220 | }, | |
221 | [3] = { | |
222 | .name = "madc", | |
223 | SIH_INITIALIZER(MADC, 4) | |
224 | }, | |
225 | [4] = { | |
226 | /* USB doesn't use the same SIH organization */ | |
227 | .name = "usb", | |
228 | }, | |
229 | [5] = { | |
230 | .name = "power", | |
231 | .set_cor = true, | |
232 | SIH_INITIALIZER(INT_PWR, 8) | |
233 | }, | |
234 | [6] = { | |
235 | /* | |
191211f5 IK |
236 | * ECI/DBI doesn't use the same SIH organization. |
237 | * For example, it supports only one interrupt output line. | |
238 | * That is, the interrupts are seen on both INT1 and INT2 lines. | |
1920a61e | 239 | */ |
191211f5 | 240 | .name = "eci_dbi", |
1920a61e IK |
241 | .module = TWL5031_MODULE_ACCESSORY, |
242 | .bits = 9, | |
243 | .bytes_ixr = 2, | |
244 | .irq_lines = 1, | |
245 | .mask = { { | |
246 | .isr_offset = TWL5031_ACIIDR_LSB, | |
247 | .imr_offset = TWL5031_ACIIMR_LSB, | |
248 | }, }, | |
249 | ||
250 | }, | |
251 | [7] = { | |
191211f5 IK |
252 | /* Audio accessory */ |
253 | .name = "audio", | |
1920a61e IK |
254 | .module = TWL5031_MODULE_ACCESSORY, |
255 | .control_offset = TWL5031_ACCSIHCTRL, | |
256 | .bits = 2, | |
257 | .bytes_ixr = 1, | |
258 | .edr_offset = TWL5031_ACCEDR1, | |
259 | /* Note: most of these IRQs default to no-trigger */ | |
260 | .bytes_edr = 1, | |
261 | .irq_lines = 2, | |
262 | .mask = { { | |
263 | .isr_offset = TWL5031_ACCISR1, | |
264 | .imr_offset = TWL5031_ACCIMR1, | |
265 | }, { | |
266 | .isr_offset = TWL5031_ACCISR2, | |
267 | .imr_offset = TWL5031_ACCIMR2, | |
268 | }, }, | |
269 | }, | |
270 | }; | |
271 | ||
a30d46c0 DB |
272 | #undef TWL4030_MODULE_KEYPAD_KEYP |
273 | #undef TWL4030_MODULE_INT_PWR | |
274 | #undef TWL4030_INT_PWR_EDR | |
275 | ||
276 | /*----------------------------------------------------------------------*/ | |
277 | ||
278 | static unsigned twl4030_irq_base; | |
279 | ||
a30d46c0 DB |
280 | /* |
281 | * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. | |
282 | * This is a chained interrupt, so there is no desc->action method for it. | |
283 | * Now we need to query the interrupt controller in the twl4030 to determine | |
284 | * which module is generating the interrupt request. However, we can't do i2c | |
285 | * transactions in interrupt context, so we must defer that work to a kernel | |
286 | * thread. All we do here is acknowledge and mask the interrupt and wakeup | |
287 | * the kernel thread. | |
288 | */ | |
1cef8e41 | 289 | static irqreturn_t handle_twl4030_pih(int irq, void *devid) |
a30d46c0 | 290 | { |
7750c9b0 FB |
291 | int module_irq; |
292 | irqreturn_t ret; | |
293 | u8 pih_isr; | |
294 | ||
295 | ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, | |
296 | REG_PIH_ISR_P1); | |
297 | if (ret) { | |
298 | pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret); | |
299 | return IRQ_NONE; | |
300 | } | |
301 | ||
302 | /* these handlers deal with the relevant SIH irq status */ | |
303 | for (module_irq = twl4030_irq_base; | |
304 | pih_isr; | |
305 | pih_isr >>= 1, module_irq++) { | |
306 | if (pih_isr & 0x1) | |
925e853c | 307 | handle_nested_irq(module_irq); |
7750c9b0 FB |
308 | } |
309 | ||
1cef8e41 | 310 | return IRQ_HANDLED; |
a30d46c0 | 311 | } |
cbcde05e | 312 | |
a30d46c0 DB |
313 | /*----------------------------------------------------------------------*/ |
314 | ||
315 | /* | |
316 | * twl4030_init_sih_modules() ... start from a known state where no | |
317 | * IRQs will be coming in, and where we can quickly enable them then | |
318 | * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. | |
319 | * | |
320 | * NOTE: we don't touch EDR registers here; they stay with hardware | |
321 | * defaults or whatever the last value was. Note that when both EDR | |
322 | * bits for an IRQ are clear, that's as if its IMR bit is set... | |
323 | */ | |
324 | static int twl4030_init_sih_modules(unsigned line) | |
325 | { | |
326 | const struct sih *sih; | |
327 | u8 buf[4]; | |
328 | int i; | |
329 | int status; | |
330 | ||
331 | /* line 0 == int1_n signal; line 1 == int2_n signal */ | |
332 | if (line > 1) | |
333 | return -EINVAL; | |
334 | ||
335 | irq_line = line; | |
336 | ||
337 | /* disable all interrupts on our line */ | |
338 | memset(buf, 0xff, sizeof buf); | |
339 | sih = sih_modules; | |
1920a61e | 340 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
341 | /* skip USB -- it's funky */ |
342 | if (!sih->bytes_ixr) | |
343 | continue; | |
344 | ||
1920a61e IK |
345 | /* Not all the SIH modules support multiple interrupt lines */ |
346 | if (sih->irq_lines <= line) | |
347 | continue; | |
348 | ||
fc7b92fc | 349 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
350 | sih->mask[line].imr_offset, sih->bytes_ixr); |
351 | if (status < 0) | |
352 | pr_err("twl4030: err %d initializing %s %s\n", | |
353 | status, sih->name, "IMR"); | |
354 | ||
cbcde05e FC |
355 | /* |
356 | * Maybe disable "exclusive" mode; buffer second pending irq; | |
a30d46c0 DB |
357 | * set Clear-On-Read (COR) bit. |
358 | * | |
359 | * NOTE that sometimes COR polarity is documented as being | |
8e52e279 | 360 | * inverted: for MADC, COR=1 means "clear on write". |
a30d46c0 DB |
361 | * And for PWR_INT it's not documented... |
362 | */ | |
363 | if (sih->set_cor) { | |
fc7b92fc | 364 | status = twl_i2c_write_u8(sih->module, |
a30d46c0 DB |
365 | TWL4030_SIH_CTRL_COR_MASK, |
366 | sih->control_offset); | |
367 | if (status < 0) | |
368 | pr_err("twl4030: err %d initializing %s %s\n", | |
369 | status, sih->name, "SIH_CTRL"); | |
370 | } | |
371 | } | |
372 | ||
373 | sih = sih_modules; | |
1920a61e | 374 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
375 | u8 rxbuf[4]; |
376 | int j; | |
377 | ||
378 | /* skip USB */ | |
379 | if (!sih->bytes_ixr) | |
380 | continue; | |
381 | ||
1920a61e IK |
382 | /* Not all the SIH modules support multiple interrupt lines */ |
383 | if (sih->irq_lines <= line) | |
384 | continue; | |
385 | ||
cbcde05e FC |
386 | /* |
387 | * Clear pending interrupt status. Either the read was | |
a30d46c0 DB |
388 | * enough, or we need to write those bits. Repeat, in |
389 | * case an IRQ is pending (PENDDIS=0) ... that's not | |
390 | * uncommon with PWR_INT.PWRON. | |
391 | */ | |
392 | for (j = 0; j < 2; j++) { | |
fc7b92fc | 393 | status = twl_i2c_read(sih->module, rxbuf, |
a30d46c0 DB |
394 | sih->mask[line].isr_offset, sih->bytes_ixr); |
395 | if (status < 0) | |
396 | pr_err("twl4030: err %d initializing %s %s\n", | |
397 | status, sih->name, "ISR"); | |
398 | ||
399 | if (!sih->set_cor) | |
fc7b92fc | 400 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
401 | sih->mask[line].isr_offset, |
402 | sih->bytes_ixr); | |
cbcde05e FC |
403 | /* |
404 | * else COR=1 means read sufficed. | |
a30d46c0 DB |
405 | * (for most SIH modules...) |
406 | */ | |
407 | } | |
408 | } | |
409 | ||
410 | return 0; | |
411 | } | |
412 | ||
413 | static inline void activate_irq(int irq) | |
414 | { | |
415 | #ifdef CONFIG_ARM | |
cbcde05e FC |
416 | /* |
417 | * ARM requires an extra step to clear IRQ_NOREQUEST, which it | |
a30d46c0 DB |
418 | * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. |
419 | */ | |
420 | set_irq_flags(irq, IRQF_VALID); | |
421 | #else | |
422 | /* same effect on other architectures */ | |
d5bb1221 | 423 | irq_set_noprobe(irq); |
a30d46c0 DB |
424 | #endif |
425 | } | |
426 | ||
427 | /*----------------------------------------------------------------------*/ | |
428 | ||
a30d46c0 DB |
429 | struct sih_agent { |
430 | int irq_base; | |
431 | const struct sih *sih; | |
432 | ||
433 | u32 imr; | |
434 | bool imr_change_pending; | |
a30d46c0 DB |
435 | |
436 | u32 edge_change; | |
91e3569f FB |
437 | |
438 | struct mutex irq_lock; | |
c1e61bcf | 439 | char *irq_name; |
a30d46c0 DB |
440 | }; |
441 | ||
a30d46c0 DB |
442 | /*----------------------------------------------------------------------*/ |
443 | ||
444 | /* | |
445 | * All irq_chip methods get issued from code holding irq_desc[irq].lock, | |
446 | * which can't perform the underlying I2C operations (because they sleep). | |
447 | * So we must hand them off to a thread (workqueue) and cope with asynch | |
448 | * completion, potentially including some re-ordering, of these requests. | |
449 | */ | |
450 | ||
845aeab5 | 451 | static void twl4030_sih_mask(struct irq_data *data) |
a30d46c0 | 452 | { |
84868424 | 453 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 | 454 | |
84868424 FB |
455 | agent->imr |= BIT(data->irq - agent->irq_base); |
456 | agent->imr_change_pending = true; | |
a30d46c0 DB |
457 | } |
458 | ||
845aeab5 | 459 | static void twl4030_sih_unmask(struct irq_data *data) |
a30d46c0 | 460 | { |
84868424 | 461 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 | 462 | |
84868424 FB |
463 | agent->imr &= ~BIT(data->irq - agent->irq_base); |
464 | agent->imr_change_pending = true; | |
a30d46c0 DB |
465 | } |
466 | ||
845aeab5 | 467 | static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) |
a30d46c0 | 468 | { |
84868424 | 469 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
470 | |
471 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
472 | return -EINVAL; | |
473 | ||
2f2a7d5e | 474 | if (irqd_get_trigger_type(data) != trigger) |
84868424 | 475 | agent->edge_change |= BIT(data->irq - agent->irq_base); |
91e3569f | 476 | |
a30d46c0 DB |
477 | return 0; |
478 | } | |
479 | ||
91e3569f FB |
480 | static void twl4030_sih_bus_lock(struct irq_data *data) |
481 | { | |
84868424 | 482 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
91e3569f | 483 | |
84868424 | 484 | mutex_lock(&agent->irq_lock); |
91e3569f FB |
485 | } |
486 | ||
487 | static void twl4030_sih_bus_sync_unlock(struct irq_data *data) | |
488 | { | |
84868424 FB |
489 | struct sih_agent *agent = irq_data_get_irq_chip_data(data); |
490 | const struct sih *sih = agent->sih; | |
491 | int status; | |
492 | ||
493 | if (agent->imr_change_pending) { | |
494 | union { | |
495 | u32 word; | |
496 | u8 bytes[4]; | |
497 | } imr; | |
498 | ||
c9531227 | 499 | /* byte[0] gets overwritten as we write ... */ |
84868424 FB |
500 | imr.word = cpu_to_le32(agent->imr << 8); |
501 | agent->imr_change_pending = false; | |
502 | ||
503 | /* write the whole mask ... simpler than subsetting it */ | |
504 | status = twl_i2c_write(sih->module, imr.bytes, | |
505 | sih->mask[irq_line].imr_offset, | |
506 | sih->bytes_ixr); | |
507 | if (status) | |
508 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
509 | "write", status); | |
510 | } | |
91e3569f | 511 | |
2f2a7d5e FB |
512 | if (agent->edge_change) { |
513 | u32 edge_change; | |
514 | u8 bytes[6]; | |
515 | ||
516 | edge_change = agent->edge_change; | |
517 | agent->edge_change = 0; | |
518 | ||
519 | /* | |
520 | * Read, reserving first byte for write scratch. Yes, this | |
521 | * could be cached for some speedup ... but be careful about | |
522 | * any processor on the other IRQ line, EDR registers are | |
523 | * shared. | |
524 | */ | |
525 | status = twl_i2c_read(sih->module, bytes + 1, | |
526 | sih->edr_offset, sih->bytes_edr); | |
527 | if (status) { | |
528 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
529 | "read", status); | |
530 | return; | |
531 | } | |
532 | ||
533 | /* Modify only the bits we know must change */ | |
534 | while (edge_change) { | |
535 | int i = fls(edge_change) - 1; | |
536 | struct irq_data *idata; | |
537 | int byte = 1 + (i >> 2); | |
538 | int off = (i & 0x3) * 2; | |
539 | unsigned int type; | |
540 | ||
541 | idata = irq_get_irq_data(i + agent->irq_base); | |
542 | ||
543 | bytes[byte] &= ~(0x03 << off); | |
544 | ||
545 | type = irqd_get_trigger_type(idata); | |
546 | if (type & IRQ_TYPE_EDGE_RISING) | |
547 | bytes[byte] |= BIT(off + 1); | |
548 | if (type & IRQ_TYPE_EDGE_FALLING) | |
549 | bytes[byte] |= BIT(off + 0); | |
550 | ||
551 | edge_change &= ~BIT(i); | |
552 | } | |
553 | ||
554 | /* Write */ | |
555 | status = twl_i2c_write(sih->module, bytes, | |
556 | sih->edr_offset, sih->bytes_edr); | |
557 | if (status) | |
558 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
559 | "write", status); | |
560 | } | |
561 | ||
84868424 | 562 | mutex_unlock(&agent->irq_lock); |
91e3569f FB |
563 | } |
564 | ||
a30d46c0 DB |
565 | static struct irq_chip twl4030_sih_irq_chip = { |
566 | .name = "twl4030", | |
8cd6af29 | 567 | .irq_mask = twl4030_sih_mask, |
845aeab5 MB |
568 | .irq_unmask = twl4030_sih_unmask, |
569 | .irq_set_type = twl4030_sih_set_type, | |
91e3569f FB |
570 | .irq_bus_lock = twl4030_sih_bus_lock, |
571 | .irq_bus_sync_unlock = twl4030_sih_bus_sync_unlock, | |
a30d46c0 DB |
572 | }; |
573 | ||
574 | /*----------------------------------------------------------------------*/ | |
575 | ||
576 | static inline int sih_read_isr(const struct sih *sih) | |
577 | { | |
578 | int status; | |
579 | union { | |
580 | u8 bytes[4]; | |
581 | u32 word; | |
582 | } isr; | |
583 | ||
584 | /* FIXME need retry-on-error ... */ | |
585 | ||
586 | isr.word = 0; | |
fc7b92fc | 587 | status = twl_i2c_read(sih->module, isr.bytes, |
a30d46c0 DB |
588 | sih->mask[irq_line].isr_offset, sih->bytes_ixr); |
589 | ||
590 | return (status < 0) ? status : le32_to_cpu(isr.word); | |
591 | } | |
592 | ||
593 | /* | |
594 | * Generic handler for SIH interrupts ... we "know" this is called | |
595 | * in task context, with IRQs enabled. | |
596 | */ | |
c1e61bcf | 597 | static irqreturn_t handle_twl4030_sih(int irq, void *data) |
a30d46c0 | 598 | { |
d5bb1221 | 599 | struct sih_agent *agent = irq_get_handler_data(irq); |
a30d46c0 DB |
600 | const struct sih *sih = agent->sih; |
601 | int isr; | |
602 | ||
603 | /* reading ISR acks the IRQs, using clear-on-read mode */ | |
a30d46c0 | 604 | isr = sih_read_isr(sih); |
a30d46c0 DB |
605 | |
606 | if (isr < 0) { | |
607 | pr_err("twl4030: %s SIH, read ISR error %d\n", | |
608 | sih->name, isr); | |
609 | /* REVISIT: recover; eventually mask it all, etc */ | |
c1e61bcf | 610 | return IRQ_HANDLED; |
a30d46c0 DB |
611 | } |
612 | ||
613 | while (isr) { | |
614 | irq = fls(isr); | |
615 | irq--; | |
616 | isr &= ~BIT(irq); | |
617 | ||
618 | if (irq < sih->bits) | |
925e853c | 619 | handle_nested_irq(agent->irq_base + irq); |
a30d46c0 DB |
620 | else |
621 | pr_err("twl4030: %s SIH, invalid ISR bit %d\n", | |
622 | sih->name, irq); | |
623 | } | |
c1e61bcf | 624 | return IRQ_HANDLED; |
a30d46c0 DB |
625 | } |
626 | ||
627 | static unsigned twl4030_irq_next; | |
628 | ||
cbcde05e | 629 | /* returns the first IRQ used by this SIH bank, or negative errno */ |
a30d46c0 DB |
630 | int twl4030_sih_setup(int module) |
631 | { | |
632 | int sih_mod; | |
633 | const struct sih *sih = NULL; | |
634 | struct sih_agent *agent; | |
635 | int i, irq; | |
636 | int status = -EINVAL; | |
637 | unsigned irq_base = twl4030_irq_next; | |
638 | ||
639 | /* only support modules with standard clear-on-read for now */ | |
640 | for (sih_mod = 0, sih = sih_modules; | |
1920a61e | 641 | sih_mod < nr_sih_modules; |
a30d46c0 DB |
642 | sih_mod++, sih++) { |
643 | if (sih->module == module && sih->set_cor) { | |
644 | if (!WARN((irq_base + sih->bits) > NR_IRQS, | |
645 | "irq %d for %s too big\n", | |
646 | irq_base + sih->bits, | |
647 | sih->name)) | |
648 | status = 0; | |
649 | break; | |
650 | } | |
651 | } | |
652 | if (status < 0) | |
653 | return status; | |
654 | ||
655 | agent = kzalloc(sizeof *agent, GFP_KERNEL); | |
656 | if (!agent) | |
657 | return -ENOMEM; | |
658 | ||
659 | status = 0; | |
660 | ||
661 | agent->irq_base = irq_base; | |
662 | agent->sih = sih; | |
663 | agent->imr = ~0; | |
91e3569f | 664 | mutex_init(&agent->irq_lock); |
a30d46c0 DB |
665 | |
666 | for (i = 0; i < sih->bits; i++) { | |
667 | irq = irq_base + i; | |
668 | ||
91e3569f | 669 | irq_set_chip_data(irq, agent); |
d5bb1221 TG |
670 | irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip, |
671 | handle_edge_irq); | |
b18d1f0f | 672 | irq_set_nested_thread(irq, 1); |
a30d46c0 DB |
673 | activate_irq(irq); |
674 | } | |
675 | ||
a30d46c0 DB |
676 | twl4030_irq_next += i; |
677 | ||
678 | /* replace generic PIH handler (handle_simple_irq) */ | |
679 | irq = sih_mod + twl4030_irq_base; | |
d5bb1221 | 680 | irq_set_handler_data(irq, agent); |
c1e61bcf N |
681 | agent->irq_name = kasprintf(GFP_KERNEL, "twl4030_%s", sih->name); |
682 | status = request_threaded_irq(irq, NULL, handle_twl4030_sih, 0, | |
683 | agent->irq_name ?: sih->name, NULL); | |
a30d46c0 DB |
684 | |
685 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, | |
686 | irq, irq_base, twl4030_irq_next - 1); | |
687 | ||
c1e61bcf | 688 | return status < 0 ? status : irq_base; |
a30d46c0 DB |
689 | } |
690 | ||
691 | /* FIXME need a call to reverse twl4030_sih_setup() ... */ | |
692 | ||
a30d46c0 DB |
693 | /*----------------------------------------------------------------------*/ |
694 | ||
695 | /* FIXME pass in which interrupt line we'll use ... */ | |
696 | #define twl_irq_line 0 | |
697 | ||
e8deb28c | 698 | int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) |
a30d46c0 DB |
699 | { |
700 | static struct irq_chip twl4030_irq_chip; | |
701 | ||
702 | int status; | |
703 | int i; | |
a30d46c0 DB |
704 | |
705 | /* | |
706 | * Mask and clear all TWL4030 interrupts since initially we do | |
707 | * not have any TWL4030 module interrupt handlers present | |
708 | */ | |
709 | status = twl4030_init_sih_modules(twl_irq_line); | |
710 | if (status < 0) | |
711 | return status; | |
712 | ||
a30d46c0 DB |
713 | twl4030_irq_base = irq_base; |
714 | ||
cbcde05e FC |
715 | /* |
716 | * install an irq handler for each of the SIH modules; | |
a30d46c0 DB |
717 | * clone dummy irq_chip since PIH can't *do* anything |
718 | */ | |
719 | twl4030_irq_chip = dummy_irq_chip; | |
720 | twl4030_irq_chip.name = "twl4030"; | |
721 | ||
fe212213 | 722 | twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; |
a30d46c0 DB |
723 | |
724 | for (i = irq_base; i < irq_end; i++) { | |
d5bb1221 TG |
725 | irq_set_chip_and_handler(i, &twl4030_irq_chip, |
726 | handle_simple_irq); | |
925e853c | 727 | irq_set_nested_thread(i, 1); |
a30d46c0 DB |
728 | activate_irq(i); |
729 | } | |
730 | twl4030_irq_next = i; | |
731 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", | |
732 | irq_num, irq_base, twl4030_irq_next - 1); | |
733 | ||
734 | /* ... and the PWR_INT module ... */ | |
735 | status = twl4030_sih_setup(TWL4030_MODULE_INT); | |
736 | if (status < 0) { | |
737 | pr_err("twl4030: sih_setup PWR INT --> %d\n", status); | |
738 | goto fail; | |
739 | } | |
740 | ||
741 | /* install an irq handler to demultiplex the TWL4030 interrupt */ | |
286f8f3c N |
742 | status = request_threaded_irq(irq_num, NULL, handle_twl4030_pih, |
743 | IRQF_ONESHOT, | |
744 | "TWL4030-PIH", NULL); | |
1cef8e41 RK |
745 | if (status < 0) { |
746 | pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); | |
747 | goto fail_rqirq; | |
748 | } | |
749 | ||
1cef8e41 | 750 | return status; |
1cef8e41 RK |
751 | fail_rqirq: |
752 | /* clean up twl4030_sih_setup */ | |
a30d46c0 | 753 | fail: |
925e853c FB |
754 | for (i = irq_base; i < irq_end; i++) { |
755 | irq_set_nested_thread(i, 0); | |
d5bb1221 | 756 | irq_set_chip_and_handler(i, NULL, NULL); |
925e853c | 757 | } |
2f2a7d5e | 758 | |
a30d46c0 DB |
759 | return status; |
760 | } | |
761 | ||
e8deb28c | 762 | int twl4030_exit_irq(void) |
a30d46c0 DB |
763 | { |
764 | /* FIXME undo twl_init_irq() */ | |
765 | if (twl4030_irq_base) { | |
766 | pr_err("twl4030: can't yet clean up IRQs?\n"); | |
767 | return -ENOSYS; | |
768 | } | |
769 | return 0; | |
770 | } | |
1920a61e | 771 | |
e8deb28c | 772 | int twl4030_init_chip_irq(const char *chip) |
1920a61e IK |
773 | { |
774 | if (!strcmp(chip, "twl5031")) { | |
775 | sih_modules = sih_modules_twl5031; | |
776 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); | |
777 | } else { | |
778 | sih_modules = sih_modules_twl4030; | |
779 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); | |
780 | } | |
781 | ||
782 | return 0; | |
783 | } |