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a30d46c0 DB |
1 | /* |
2 | * twl4030-irq.c - TWL4030/TPS659x0 irq support | |
3 | * | |
4 | * Copyright (C) 2005-2006 Texas Instruments, Inc. | |
5 | * | |
6 | * Modifications to defer interrupt handling to a kernel thread: | |
7 | * Copyright (C) 2006 MontaVista Software, Inc. | |
8 | * | |
9 | * Based on tlv320aic23.c: | |
10 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> | |
11 | * | |
12 | * Code cleanup and modifications to IRQ handler. | |
13 | * by syed khasim <x0khasim@ti.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <linux/init.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/kthread.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
a30d46c0 | 35 | |
b07682b6 | 36 | #include <linux/i2c/twl.h> |
a30d46c0 | 37 | |
b0b4a7c2 | 38 | #include "twl-core.h" |
a30d46c0 DB |
39 | |
40 | /* | |
41 | * TWL4030 IRQ handling has two stages in hardware, and thus in software. | |
42 | * The Primary Interrupt Handler (PIH) stage exposes status bits saying | |
43 | * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. | |
44 | * SIH modules are more traditional IRQ components, which support per-IRQ | |
45 | * enable/disable and trigger controls; they do most of the work. | |
46 | * | |
47 | * These chips are designed to support IRQ handling from two different | |
48 | * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status | |
49 | * and mask registers in the PIH and SIH modules. | |
50 | * | |
51 | * We set up IRQs starting at a platform-specified base, always starting | |
52 | * with PIH and the SIH for PWR_INT and then usually adding GPIO: | |
53 | * base + 0 .. base + 7 PIH | |
54 | * base + 8 .. base + 15 SIH for PWR_INT | |
55 | * base + 16 .. base + 33 SIH for GPIO | |
56 | */ | |
57 | ||
58 | /* PIH register offsets */ | |
59 | #define REG_PIH_ISR_P1 0x01 | |
60 | #define REG_PIH_ISR_P2 0x02 | |
61 | #define REG_PIH_SIR 0x03 /* for testing */ | |
62 | ||
63 | ||
64 | /* Linux could (eventually) use either IRQ line */ | |
65 | static int irq_line; | |
66 | ||
67 | struct sih { | |
68 | char name[8]; | |
69 | u8 module; /* module id */ | |
70 | u8 control_offset; /* for SIH_CTRL */ | |
71 | bool set_cor; | |
72 | ||
73 | u8 bits; /* valid in isr/imr */ | |
74 | u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ | |
75 | ||
76 | u8 edr_offset; | |
77 | u8 bytes_edr; /* bytelen of EDR */ | |
78 | ||
1920a61e IK |
79 | u8 irq_lines; /* number of supported irq lines */ |
80 | ||
a30d46c0 | 81 | /* SIR ignored -- set interrupt, for testing only */ |
35a27e8e | 82 | struct sih_irq_data { |
a30d46c0 DB |
83 | u8 isr_offset; |
84 | u8 imr_offset; | |
85 | } mask[2]; | |
86 | /* + 2 bytes padding */ | |
87 | }; | |
88 | ||
1920a61e IK |
89 | static const struct sih *sih_modules; |
90 | static int nr_sih_modules; | |
91 | ||
a30d46c0 DB |
92 | #define SIH_INITIALIZER(modname, nbits) \ |
93 | .module = TWL4030_MODULE_ ## modname, \ | |
94 | .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ | |
95 | .bits = nbits, \ | |
96 | .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ | |
97 | .edr_offset = TWL4030_ ## modname ## _EDR, \ | |
98 | .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ | |
1920a61e | 99 | .irq_lines = 2, \ |
a30d46c0 DB |
100 | .mask = { { \ |
101 | .isr_offset = TWL4030_ ## modname ## _ISR1, \ | |
102 | .imr_offset = TWL4030_ ## modname ## _IMR1, \ | |
103 | }, \ | |
104 | { \ | |
105 | .isr_offset = TWL4030_ ## modname ## _ISR2, \ | |
106 | .imr_offset = TWL4030_ ## modname ## _IMR2, \ | |
107 | }, }, | |
108 | ||
109 | /* register naming policies are inconsistent ... */ | |
110 | #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 | |
111 | #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD | |
112 | #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT | |
113 | ||
114 | ||
115 | /* Order in this table matches order in PIH_ISR. That is, | |
116 | * BIT(n) in PIH_ISR is sih_modules[n]. | |
117 | */ | |
1920a61e IK |
118 | /* sih_modules_twl4030 is used both in twl4030 and twl5030 */ |
119 | static const struct sih sih_modules_twl4030[6] = { | |
a30d46c0 DB |
120 | [0] = { |
121 | .name = "gpio", | |
122 | .module = TWL4030_MODULE_GPIO, | |
123 | .control_offset = REG_GPIO_SIH_CTRL, | |
124 | .set_cor = true, | |
125 | .bits = TWL4030_GPIO_MAX, | |
126 | .bytes_ixr = 3, | |
127 | /* Note: *all* of these IRQs default to no-trigger */ | |
128 | .edr_offset = REG_GPIO_EDR1, | |
129 | .bytes_edr = 5, | |
1920a61e | 130 | .irq_lines = 2, |
a30d46c0 DB |
131 | .mask = { { |
132 | .isr_offset = REG_GPIO_ISR1A, | |
133 | .imr_offset = REG_GPIO_IMR1A, | |
134 | }, { | |
135 | .isr_offset = REG_GPIO_ISR1B, | |
136 | .imr_offset = REG_GPIO_IMR1B, | |
137 | }, }, | |
138 | }, | |
139 | [1] = { | |
140 | .name = "keypad", | |
141 | .set_cor = true, | |
142 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
143 | }, | |
144 | [2] = { | |
145 | .name = "bci", | |
146 | .module = TWL4030_MODULE_INTERRUPTS, | |
147 | .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, | |
8e52e279 | 148 | .set_cor = true, |
a30d46c0 DB |
149 | .bits = 12, |
150 | .bytes_ixr = 2, | |
151 | .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, | |
152 | /* Note: most of these IRQs default to no-trigger */ | |
153 | .bytes_edr = 3, | |
1920a61e | 154 | .irq_lines = 2, |
a30d46c0 DB |
155 | .mask = { { |
156 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, | |
157 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, | |
158 | }, { | |
159 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, | |
160 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, | |
161 | }, }, | |
162 | }, | |
163 | [3] = { | |
164 | .name = "madc", | |
165 | SIH_INITIALIZER(MADC, 4) | |
166 | }, | |
167 | [4] = { | |
168 | /* USB doesn't use the same SIH organization */ | |
169 | .name = "usb", | |
170 | }, | |
171 | [5] = { | |
172 | .name = "power", | |
173 | .set_cor = true, | |
174 | SIH_INITIALIZER(INT_PWR, 8) | |
175 | }, | |
176 | /* there are no SIH modules #6 or #7 ... */ | |
177 | }; | |
178 | ||
1920a61e IK |
179 | static const struct sih sih_modules_twl5031[8] = { |
180 | [0] = { | |
181 | .name = "gpio", | |
182 | .module = TWL4030_MODULE_GPIO, | |
183 | .control_offset = REG_GPIO_SIH_CTRL, | |
184 | .set_cor = true, | |
185 | .bits = TWL4030_GPIO_MAX, | |
186 | .bytes_ixr = 3, | |
187 | /* Note: *all* of these IRQs default to no-trigger */ | |
188 | .edr_offset = REG_GPIO_EDR1, | |
189 | .bytes_edr = 5, | |
190 | .irq_lines = 2, | |
191 | .mask = { { | |
192 | .isr_offset = REG_GPIO_ISR1A, | |
193 | .imr_offset = REG_GPIO_IMR1A, | |
194 | }, { | |
195 | .isr_offset = REG_GPIO_ISR1B, | |
196 | .imr_offset = REG_GPIO_IMR1B, | |
197 | }, }, | |
198 | }, | |
199 | [1] = { | |
200 | .name = "keypad", | |
201 | .set_cor = true, | |
202 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
203 | }, | |
204 | [2] = { | |
205 | .name = "bci", | |
206 | .module = TWL5031_MODULE_INTERRUPTS, | |
207 | .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, | |
208 | .bits = 7, | |
209 | .bytes_ixr = 1, | |
210 | .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, | |
211 | /* Note: most of these IRQs default to no-trigger */ | |
212 | .bytes_edr = 2, | |
213 | .irq_lines = 2, | |
214 | .mask = { { | |
215 | .isr_offset = TWL5031_INTERRUPTS_BCIISR1, | |
216 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, | |
217 | }, { | |
218 | .isr_offset = TWL5031_INTERRUPTS_BCIISR2, | |
219 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, | |
220 | }, }, | |
221 | }, | |
222 | [3] = { | |
223 | .name = "madc", | |
224 | SIH_INITIALIZER(MADC, 4) | |
225 | }, | |
226 | [4] = { | |
227 | /* USB doesn't use the same SIH organization */ | |
228 | .name = "usb", | |
229 | }, | |
230 | [5] = { | |
231 | .name = "power", | |
232 | .set_cor = true, | |
233 | SIH_INITIALIZER(INT_PWR, 8) | |
234 | }, | |
235 | [6] = { | |
236 | /* | |
191211f5 IK |
237 | * ECI/DBI doesn't use the same SIH organization. |
238 | * For example, it supports only one interrupt output line. | |
239 | * That is, the interrupts are seen on both INT1 and INT2 lines. | |
1920a61e | 240 | */ |
191211f5 | 241 | .name = "eci_dbi", |
1920a61e IK |
242 | .module = TWL5031_MODULE_ACCESSORY, |
243 | .bits = 9, | |
244 | .bytes_ixr = 2, | |
245 | .irq_lines = 1, | |
246 | .mask = { { | |
247 | .isr_offset = TWL5031_ACIIDR_LSB, | |
248 | .imr_offset = TWL5031_ACIIMR_LSB, | |
249 | }, }, | |
250 | ||
251 | }, | |
252 | [7] = { | |
191211f5 IK |
253 | /* Audio accessory */ |
254 | .name = "audio", | |
1920a61e IK |
255 | .module = TWL5031_MODULE_ACCESSORY, |
256 | .control_offset = TWL5031_ACCSIHCTRL, | |
257 | .bits = 2, | |
258 | .bytes_ixr = 1, | |
259 | .edr_offset = TWL5031_ACCEDR1, | |
260 | /* Note: most of these IRQs default to no-trigger */ | |
261 | .bytes_edr = 1, | |
262 | .irq_lines = 2, | |
263 | .mask = { { | |
264 | .isr_offset = TWL5031_ACCISR1, | |
265 | .imr_offset = TWL5031_ACCIMR1, | |
266 | }, { | |
267 | .isr_offset = TWL5031_ACCISR2, | |
268 | .imr_offset = TWL5031_ACCIMR2, | |
269 | }, }, | |
270 | }, | |
271 | }; | |
272 | ||
a30d46c0 DB |
273 | #undef TWL4030_MODULE_KEYPAD_KEYP |
274 | #undef TWL4030_MODULE_INT_PWR | |
275 | #undef TWL4030_INT_PWR_EDR | |
276 | ||
277 | /*----------------------------------------------------------------------*/ | |
278 | ||
279 | static unsigned twl4030_irq_base; | |
280 | ||
281 | static struct completion irq_event; | |
282 | ||
283 | /* | |
284 | * This thread processes interrupts reported by the Primary Interrupt Handler. | |
285 | */ | |
286 | static int twl4030_irq_thread(void *data) | |
287 | { | |
288 | long irq = (long)data; | |
a30d46c0 | 289 | static unsigned i2c_errors; |
3446d4bb | 290 | static const unsigned max_i2c_errors = 100; |
a30d46c0 | 291 | |
94964f96 | 292 | |
a30d46c0 DB |
293 | current->flags |= PF_NOFREEZE; |
294 | ||
295 | while (!kthread_should_stop()) { | |
296 | int ret; | |
297 | int module_irq; | |
298 | u8 pih_isr; | |
299 | ||
300 | /* Wait for IRQ, then read PIH irq status (also blocking) */ | |
301 | wait_for_completion_interruptible(&irq_event); | |
302 | ||
fc7b92fc | 303 | ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, |
a30d46c0 DB |
304 | REG_PIH_ISR_P1); |
305 | if (ret) { | |
306 | pr_warning("twl4030: I2C error %d reading PIH ISR\n", | |
307 | ret); | |
308 | if (++i2c_errors >= max_i2c_errors) { | |
309 | printk(KERN_ERR "Maximum I2C error count" | |
310 | " exceeded. Terminating %s.\n", | |
311 | __func__); | |
312 | break; | |
313 | } | |
314 | complete(&irq_event); | |
315 | continue; | |
316 | } | |
317 | ||
318 | /* these handlers deal with the relevant SIH irq status */ | |
319 | local_irq_disable(); | |
320 | for (module_irq = twl4030_irq_base; | |
321 | pih_isr; | |
322 | pih_isr >>= 1, module_irq++) { | |
d740f452 TG |
323 | if (pih_isr & 0x1) |
324 | generic_handle_irq(module_irq); | |
a30d46c0 DB |
325 | } |
326 | local_irq_enable(); | |
327 | ||
1cef8e41 | 328 | enable_irq(irq); |
a30d46c0 DB |
329 | } |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | /* | |
335 | * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. | |
336 | * This is a chained interrupt, so there is no desc->action method for it. | |
337 | * Now we need to query the interrupt controller in the twl4030 to determine | |
338 | * which module is generating the interrupt request. However, we can't do i2c | |
339 | * transactions in interrupt context, so we must defer that work to a kernel | |
340 | * thread. All we do here is acknowledge and mask the interrupt and wakeup | |
341 | * the kernel thread. | |
342 | */ | |
1cef8e41 | 343 | static irqreturn_t handle_twl4030_pih(int irq, void *devid) |
a30d46c0 DB |
344 | { |
345 | /* Acknowledge, clear *AND* mask the interrupt... */ | |
1cef8e41 RK |
346 | disable_irq_nosync(irq); |
347 | complete(devid); | |
348 | return IRQ_HANDLED; | |
a30d46c0 | 349 | } |
a30d46c0 DB |
350 | /*----------------------------------------------------------------------*/ |
351 | ||
352 | /* | |
353 | * twl4030_init_sih_modules() ... start from a known state where no | |
354 | * IRQs will be coming in, and where we can quickly enable them then | |
355 | * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. | |
356 | * | |
357 | * NOTE: we don't touch EDR registers here; they stay with hardware | |
358 | * defaults or whatever the last value was. Note that when both EDR | |
359 | * bits for an IRQ are clear, that's as if its IMR bit is set... | |
360 | */ | |
361 | static int twl4030_init_sih_modules(unsigned line) | |
362 | { | |
363 | const struct sih *sih; | |
364 | u8 buf[4]; | |
365 | int i; | |
366 | int status; | |
367 | ||
368 | /* line 0 == int1_n signal; line 1 == int2_n signal */ | |
369 | if (line > 1) | |
370 | return -EINVAL; | |
371 | ||
372 | irq_line = line; | |
373 | ||
374 | /* disable all interrupts on our line */ | |
375 | memset(buf, 0xff, sizeof buf); | |
376 | sih = sih_modules; | |
1920a61e | 377 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
378 | |
379 | /* skip USB -- it's funky */ | |
380 | if (!sih->bytes_ixr) | |
381 | continue; | |
382 | ||
1920a61e IK |
383 | /* Not all the SIH modules support multiple interrupt lines */ |
384 | if (sih->irq_lines <= line) | |
385 | continue; | |
386 | ||
fc7b92fc | 387 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
388 | sih->mask[line].imr_offset, sih->bytes_ixr); |
389 | if (status < 0) | |
390 | pr_err("twl4030: err %d initializing %s %s\n", | |
391 | status, sih->name, "IMR"); | |
392 | ||
393 | /* Maybe disable "exclusive" mode; buffer second pending irq; | |
394 | * set Clear-On-Read (COR) bit. | |
395 | * | |
396 | * NOTE that sometimes COR polarity is documented as being | |
8e52e279 | 397 | * inverted: for MADC, COR=1 means "clear on write". |
a30d46c0 DB |
398 | * And for PWR_INT it's not documented... |
399 | */ | |
400 | if (sih->set_cor) { | |
fc7b92fc | 401 | status = twl_i2c_write_u8(sih->module, |
a30d46c0 DB |
402 | TWL4030_SIH_CTRL_COR_MASK, |
403 | sih->control_offset); | |
404 | if (status < 0) | |
405 | pr_err("twl4030: err %d initializing %s %s\n", | |
406 | status, sih->name, "SIH_CTRL"); | |
407 | } | |
408 | } | |
409 | ||
410 | sih = sih_modules; | |
1920a61e | 411 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
412 | u8 rxbuf[4]; |
413 | int j; | |
414 | ||
415 | /* skip USB */ | |
416 | if (!sih->bytes_ixr) | |
417 | continue; | |
418 | ||
1920a61e IK |
419 | /* Not all the SIH modules support multiple interrupt lines */ |
420 | if (sih->irq_lines <= line) | |
421 | continue; | |
422 | ||
a30d46c0 DB |
423 | /* Clear pending interrupt status. Either the read was |
424 | * enough, or we need to write those bits. Repeat, in | |
425 | * case an IRQ is pending (PENDDIS=0) ... that's not | |
426 | * uncommon with PWR_INT.PWRON. | |
427 | */ | |
428 | for (j = 0; j < 2; j++) { | |
fc7b92fc | 429 | status = twl_i2c_read(sih->module, rxbuf, |
a30d46c0 DB |
430 | sih->mask[line].isr_offset, sih->bytes_ixr); |
431 | if (status < 0) | |
432 | pr_err("twl4030: err %d initializing %s %s\n", | |
433 | status, sih->name, "ISR"); | |
434 | ||
435 | if (!sih->set_cor) | |
fc7b92fc | 436 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
437 | sih->mask[line].isr_offset, |
438 | sih->bytes_ixr); | |
439 | /* else COR=1 means read sufficed. | |
440 | * (for most SIH modules...) | |
441 | */ | |
442 | } | |
443 | } | |
444 | ||
445 | return 0; | |
446 | } | |
447 | ||
448 | static inline void activate_irq(int irq) | |
449 | { | |
450 | #ifdef CONFIG_ARM | |
451 | /* ARM requires an extra step to clear IRQ_NOREQUEST, which it | |
452 | * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. | |
453 | */ | |
454 | set_irq_flags(irq, IRQF_VALID); | |
455 | #else | |
456 | /* same effect on other architectures */ | |
d5bb1221 | 457 | irq_set_noprobe(irq); |
a30d46c0 DB |
458 | #endif |
459 | } | |
460 | ||
461 | /*----------------------------------------------------------------------*/ | |
462 | ||
463 | static DEFINE_SPINLOCK(sih_agent_lock); | |
464 | ||
465 | static struct workqueue_struct *wq; | |
466 | ||
467 | struct sih_agent { | |
468 | int irq_base; | |
469 | const struct sih *sih; | |
470 | ||
471 | u32 imr; | |
472 | bool imr_change_pending; | |
473 | struct work_struct mask_work; | |
474 | ||
475 | u32 edge_change; | |
476 | struct work_struct edge_work; | |
477 | }; | |
478 | ||
479 | static void twl4030_sih_do_mask(struct work_struct *work) | |
480 | { | |
481 | struct sih_agent *agent; | |
482 | const struct sih *sih; | |
483 | union { | |
484 | u8 bytes[4]; | |
485 | u32 word; | |
486 | } imr; | |
487 | int status; | |
488 | ||
489 | agent = container_of(work, struct sih_agent, mask_work); | |
490 | ||
491 | /* see what work we have */ | |
492 | spin_lock_irq(&sih_agent_lock); | |
493 | if (agent->imr_change_pending) { | |
494 | sih = agent->sih; | |
495 | /* byte[0] gets overwritten as we write ... */ | |
496 | imr.word = cpu_to_le32(agent->imr << 8); | |
497 | agent->imr_change_pending = false; | |
498 | } else | |
499 | sih = NULL; | |
500 | spin_unlock_irq(&sih_agent_lock); | |
501 | if (!sih) | |
502 | return; | |
503 | ||
504 | /* write the whole mask ... simpler than subsetting it */ | |
fc7b92fc | 505 | status = twl_i2c_write(sih->module, imr.bytes, |
a30d46c0 DB |
506 | sih->mask[irq_line].imr_offset, sih->bytes_ixr); |
507 | if (status) | |
508 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
509 | "write", status); | |
510 | } | |
511 | ||
512 | static void twl4030_sih_do_edge(struct work_struct *work) | |
513 | { | |
514 | struct sih_agent *agent; | |
515 | const struct sih *sih; | |
516 | u8 bytes[6]; | |
517 | u32 edge_change; | |
518 | int status; | |
519 | ||
520 | agent = container_of(work, struct sih_agent, edge_work); | |
521 | ||
522 | /* see what work we have */ | |
523 | spin_lock_irq(&sih_agent_lock); | |
524 | edge_change = agent->edge_change; | |
df10d646 | 525 | agent->edge_change = 0; |
a30d46c0 DB |
526 | sih = edge_change ? agent->sih : NULL; |
527 | spin_unlock_irq(&sih_agent_lock); | |
528 | if (!sih) | |
529 | return; | |
530 | ||
531 | /* Read, reserving first byte for write scratch. Yes, this | |
532 | * could be cached for some speedup ... but be careful about | |
533 | * any processor on the other IRQ line, EDR registers are | |
534 | * shared. | |
535 | */ | |
fc7b92fc | 536 | status = twl_i2c_read(sih->module, bytes + 1, |
a30d46c0 DB |
537 | sih->edr_offset, sih->bytes_edr); |
538 | if (status) { | |
539 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
540 | "read", status); | |
541 | return; | |
542 | } | |
543 | ||
544 | /* Modify only the bits we know must change */ | |
545 | while (edge_change) { | |
546 | int i = fls(edge_change) - 1; | |
d740f452 | 547 | struct irq_data *idata = irq_get_irq_data(i + agent->irq_base); |
a30d46c0 DB |
548 | int byte = 1 + (i >> 2); |
549 | int off = (i & 0x3) * 2; | |
d740f452 | 550 | unsigned int type; |
94964f96 | 551 | |
a30d46c0 DB |
552 | bytes[byte] &= ~(0x03 << off); |
553 | ||
d740f452 TG |
554 | type = irqd_get_trigger_type(idata); |
555 | if (type & IRQ_TYPE_EDGE_RISING) | |
a30d46c0 | 556 | bytes[byte] |= BIT(off + 1); |
d740f452 | 557 | if (type & IRQ_TYPE_EDGE_FALLING) |
a30d46c0 | 558 | bytes[byte] |= BIT(off + 0); |
a30d46c0 DB |
559 | |
560 | edge_change &= ~BIT(i); | |
561 | } | |
562 | ||
563 | /* Write */ | |
fc7b92fc | 564 | status = twl_i2c_write(sih->module, bytes, |
a30d46c0 DB |
565 | sih->edr_offset, sih->bytes_edr); |
566 | if (status) | |
567 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
568 | "write", status); | |
569 | } | |
570 | ||
571 | /*----------------------------------------------------------------------*/ | |
572 | ||
573 | /* | |
574 | * All irq_chip methods get issued from code holding irq_desc[irq].lock, | |
575 | * which can't perform the underlying I2C operations (because they sleep). | |
576 | * So we must hand them off to a thread (workqueue) and cope with asynch | |
577 | * completion, potentially including some re-ordering, of these requests. | |
578 | */ | |
579 | ||
845aeab5 | 580 | static void twl4030_sih_mask(struct irq_data *data) |
a30d46c0 | 581 | { |
845aeab5 | 582 | struct sih_agent *sih = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
583 | unsigned long flags; |
584 | ||
585 | spin_lock_irqsave(&sih_agent_lock, flags); | |
845aeab5 | 586 | sih->imr |= BIT(data->irq - sih->irq_base); |
a30d46c0 DB |
587 | sih->imr_change_pending = true; |
588 | queue_work(wq, &sih->mask_work); | |
589 | spin_unlock_irqrestore(&sih_agent_lock, flags); | |
590 | } | |
591 | ||
845aeab5 | 592 | static void twl4030_sih_unmask(struct irq_data *data) |
a30d46c0 | 593 | { |
845aeab5 | 594 | struct sih_agent *sih = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
595 | unsigned long flags; |
596 | ||
597 | spin_lock_irqsave(&sih_agent_lock, flags); | |
845aeab5 | 598 | sih->imr &= ~BIT(data->irq - sih->irq_base); |
a30d46c0 DB |
599 | sih->imr_change_pending = true; |
600 | queue_work(wq, &sih->mask_work); | |
601 | spin_unlock_irqrestore(&sih_agent_lock, flags); | |
602 | } | |
603 | ||
845aeab5 | 604 | static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) |
a30d46c0 | 605 | { |
845aeab5 | 606 | struct sih_agent *sih = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
607 | unsigned long flags; |
608 | ||
609 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
610 | return -EINVAL; | |
611 | ||
612 | spin_lock_irqsave(&sih_agent_lock, flags); | |
d740f452 | 613 | if (irqd_get_trigger_type(data) != trigger) { |
845aeab5 | 614 | sih->edge_change |= BIT(data->irq - sih->irq_base); |
a30d46c0 DB |
615 | queue_work(wq, &sih->edge_work); |
616 | } | |
617 | spin_unlock_irqrestore(&sih_agent_lock, flags); | |
618 | return 0; | |
619 | } | |
620 | ||
621 | static struct irq_chip twl4030_sih_irq_chip = { | |
622 | .name = "twl4030", | |
845aeab5 MB |
623 | .irq_mask = twl4030_sih_mask, |
624 | .irq_unmask = twl4030_sih_unmask, | |
625 | .irq_set_type = twl4030_sih_set_type, | |
a30d46c0 DB |
626 | }; |
627 | ||
628 | /*----------------------------------------------------------------------*/ | |
629 | ||
630 | static inline int sih_read_isr(const struct sih *sih) | |
631 | { | |
632 | int status; | |
633 | union { | |
634 | u8 bytes[4]; | |
635 | u32 word; | |
636 | } isr; | |
637 | ||
638 | /* FIXME need retry-on-error ... */ | |
639 | ||
640 | isr.word = 0; | |
fc7b92fc | 641 | status = twl_i2c_read(sih->module, isr.bytes, |
a30d46c0 DB |
642 | sih->mask[irq_line].isr_offset, sih->bytes_ixr); |
643 | ||
644 | return (status < 0) ? status : le32_to_cpu(isr.word); | |
645 | } | |
646 | ||
647 | /* | |
648 | * Generic handler for SIH interrupts ... we "know" this is called | |
649 | * in task context, with IRQs enabled. | |
650 | */ | |
651 | static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) | |
652 | { | |
d5bb1221 | 653 | struct sih_agent *agent = irq_get_handler_data(irq); |
a30d46c0 DB |
654 | const struct sih *sih = agent->sih; |
655 | int isr; | |
656 | ||
657 | /* reading ISR acks the IRQs, using clear-on-read mode */ | |
658 | local_irq_enable(); | |
659 | isr = sih_read_isr(sih); | |
660 | local_irq_disable(); | |
661 | ||
662 | if (isr < 0) { | |
663 | pr_err("twl4030: %s SIH, read ISR error %d\n", | |
664 | sih->name, isr); | |
665 | /* REVISIT: recover; eventually mask it all, etc */ | |
666 | return; | |
667 | } | |
668 | ||
669 | while (isr) { | |
670 | irq = fls(isr); | |
671 | irq--; | |
672 | isr &= ~BIT(irq); | |
673 | ||
674 | if (irq < sih->bits) | |
675 | generic_handle_irq(agent->irq_base + irq); | |
676 | else | |
677 | pr_err("twl4030: %s SIH, invalid ISR bit %d\n", | |
678 | sih->name, irq); | |
679 | } | |
680 | } | |
681 | ||
682 | static unsigned twl4030_irq_next; | |
683 | ||
684 | /* returns the first IRQ used by this SIH bank, | |
685 | * or negative errno | |
686 | */ | |
687 | int twl4030_sih_setup(int module) | |
688 | { | |
689 | int sih_mod; | |
690 | const struct sih *sih = NULL; | |
691 | struct sih_agent *agent; | |
692 | int i, irq; | |
693 | int status = -EINVAL; | |
694 | unsigned irq_base = twl4030_irq_next; | |
695 | ||
696 | /* only support modules with standard clear-on-read for now */ | |
697 | for (sih_mod = 0, sih = sih_modules; | |
1920a61e | 698 | sih_mod < nr_sih_modules; |
a30d46c0 DB |
699 | sih_mod++, sih++) { |
700 | if (sih->module == module && sih->set_cor) { | |
701 | if (!WARN((irq_base + sih->bits) > NR_IRQS, | |
702 | "irq %d for %s too big\n", | |
703 | irq_base + sih->bits, | |
704 | sih->name)) | |
705 | status = 0; | |
706 | break; | |
707 | } | |
708 | } | |
709 | if (status < 0) | |
710 | return status; | |
711 | ||
712 | agent = kzalloc(sizeof *agent, GFP_KERNEL); | |
713 | if (!agent) | |
714 | return -ENOMEM; | |
715 | ||
716 | status = 0; | |
717 | ||
718 | agent->irq_base = irq_base; | |
719 | agent->sih = sih; | |
720 | agent->imr = ~0; | |
721 | INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); | |
722 | INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); | |
723 | ||
724 | for (i = 0; i < sih->bits; i++) { | |
725 | irq = irq_base + i; | |
726 | ||
d5bb1221 TG |
727 | irq_set_chip_and_handler(irq, &twl4030_sih_irq_chip, |
728 | handle_edge_irq); | |
729 | irq_set_chip_data(irq, agent); | |
a30d46c0 DB |
730 | activate_irq(irq); |
731 | } | |
732 | ||
733 | status = irq_base; | |
734 | twl4030_irq_next += i; | |
735 | ||
736 | /* replace generic PIH handler (handle_simple_irq) */ | |
737 | irq = sih_mod + twl4030_irq_base; | |
d5bb1221 TG |
738 | irq_set_handler_data(irq, agent); |
739 | irq_set_chained_handler(irq, handle_twl4030_sih); | |
a30d46c0 DB |
740 | |
741 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, | |
742 | irq, irq_base, twl4030_irq_next - 1); | |
743 | ||
744 | return status; | |
745 | } | |
746 | ||
747 | /* FIXME need a call to reverse twl4030_sih_setup() ... */ | |
748 | ||
749 | ||
750 | /*----------------------------------------------------------------------*/ | |
751 | ||
752 | /* FIXME pass in which interrupt line we'll use ... */ | |
753 | #define twl_irq_line 0 | |
754 | ||
e8deb28c | 755 | int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) |
a30d46c0 DB |
756 | { |
757 | static struct irq_chip twl4030_irq_chip; | |
758 | ||
759 | int status; | |
760 | int i; | |
761 | struct task_struct *task; | |
762 | ||
763 | /* | |
764 | * Mask and clear all TWL4030 interrupts since initially we do | |
765 | * not have any TWL4030 module interrupt handlers present | |
766 | */ | |
767 | status = twl4030_init_sih_modules(twl_irq_line); | |
768 | if (status < 0) | |
769 | return status; | |
770 | ||
771 | wq = create_singlethread_workqueue("twl4030-irqchip"); | |
772 | if (!wq) { | |
773 | pr_err("twl4030: workqueue FAIL\n"); | |
774 | return -ESRCH; | |
775 | } | |
776 | ||
777 | twl4030_irq_base = irq_base; | |
778 | ||
779 | /* install an irq handler for each of the SIH modules; | |
780 | * clone dummy irq_chip since PIH can't *do* anything | |
781 | */ | |
782 | twl4030_irq_chip = dummy_irq_chip; | |
783 | twl4030_irq_chip.name = "twl4030"; | |
784 | ||
fe212213 | 785 | twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; |
a30d46c0 DB |
786 | |
787 | for (i = irq_base; i < irq_end; i++) { | |
d5bb1221 TG |
788 | irq_set_chip_and_handler(i, &twl4030_irq_chip, |
789 | handle_simple_irq); | |
a30d46c0 DB |
790 | activate_irq(i); |
791 | } | |
792 | twl4030_irq_next = i; | |
793 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", | |
794 | irq_num, irq_base, twl4030_irq_next - 1); | |
795 | ||
796 | /* ... and the PWR_INT module ... */ | |
797 | status = twl4030_sih_setup(TWL4030_MODULE_INT); | |
798 | if (status < 0) { | |
799 | pr_err("twl4030: sih_setup PWR INT --> %d\n", status); | |
800 | goto fail; | |
801 | } | |
802 | ||
803 | /* install an irq handler to demultiplex the TWL4030 interrupt */ | |
a30d46c0 | 804 | |
a30d46c0 | 805 | |
1cef8e41 | 806 | init_completion(&irq_event); |
a30d46c0 | 807 | |
1cef8e41 RK |
808 | status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED, |
809 | "TWL4030-PIH", &irq_event); | |
810 | if (status < 0) { | |
811 | pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); | |
812 | goto fail_rqirq; | |
813 | } | |
814 | ||
89f5f9f7 AC |
815 | task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num, |
816 | "twl4030-irq"); | |
1cef8e41 RK |
817 | if (IS_ERR(task)) { |
818 | pr_err("twl4030: could not create irq %d thread!\n", irq_num); | |
819 | status = PTR_ERR(task); | |
820 | goto fail_kthread; | |
821 | } | |
822 | return status; | |
823 | fail_kthread: | |
824 | free_irq(irq_num, &irq_event); | |
825 | fail_rqirq: | |
826 | /* clean up twl4030_sih_setup */ | |
a30d46c0 DB |
827 | fail: |
828 | for (i = irq_base; i < irq_end; i++) | |
d5bb1221 | 829 | irq_set_chip_and_handler(i, NULL, NULL); |
a30d46c0 DB |
830 | destroy_workqueue(wq); |
831 | wq = NULL; | |
832 | return status; | |
833 | } | |
834 | ||
e8deb28c | 835 | int twl4030_exit_irq(void) |
a30d46c0 DB |
836 | { |
837 | /* FIXME undo twl_init_irq() */ | |
838 | if (twl4030_irq_base) { | |
839 | pr_err("twl4030: can't yet clean up IRQs?\n"); | |
840 | return -ENOSYS; | |
841 | } | |
842 | return 0; | |
843 | } | |
1920a61e | 844 | |
e8deb28c | 845 | int twl4030_init_chip_irq(const char *chip) |
1920a61e IK |
846 | { |
847 | if (!strcmp(chip, "twl5031")) { | |
848 | sih_modules = sih_modules_twl5031; | |
849 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); | |
850 | } else { | |
851 | sih_modules = sih_modules_twl4030; | |
852 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); | |
853 | } | |
854 | ||
855 | return 0; | |
856 | } |