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a30d46c0 DB |
1 | /* |
2 | * twl4030-irq.c - TWL4030/TPS659x0 irq support | |
3 | * | |
4 | * Copyright (C) 2005-2006 Texas Instruments, Inc. | |
5 | * | |
6 | * Modifications to defer interrupt handling to a kernel thread: | |
7 | * Copyright (C) 2006 MontaVista Software, Inc. | |
8 | * | |
9 | * Based on tlv320aic23.c: | |
10 | * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> | |
11 | * | |
12 | * Code cleanup and modifications to IRQ handler. | |
13 | * by syed khasim <x0khasim@ti.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
28 | */ | |
29 | ||
30 | #include <linux/init.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/irq.h> | |
33 | #include <linux/kthread.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
a30d46c0 | 35 | |
b07682b6 | 36 | #include <linux/i2c/twl.h> |
a30d46c0 | 37 | |
b0b4a7c2 | 38 | #include "twl-core.h" |
a30d46c0 DB |
39 | |
40 | /* | |
41 | * TWL4030 IRQ handling has two stages in hardware, and thus in software. | |
42 | * The Primary Interrupt Handler (PIH) stage exposes status bits saying | |
43 | * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. | |
44 | * SIH modules are more traditional IRQ components, which support per-IRQ | |
45 | * enable/disable and trigger controls; they do most of the work. | |
46 | * | |
47 | * These chips are designed to support IRQ handling from two different | |
48 | * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status | |
49 | * and mask registers in the PIH and SIH modules. | |
50 | * | |
51 | * We set up IRQs starting at a platform-specified base, always starting | |
52 | * with PIH and the SIH for PWR_INT and then usually adding GPIO: | |
53 | * base + 0 .. base + 7 PIH | |
54 | * base + 8 .. base + 15 SIH for PWR_INT | |
55 | * base + 16 .. base + 33 SIH for GPIO | |
56 | */ | |
57 | ||
58 | /* PIH register offsets */ | |
59 | #define REG_PIH_ISR_P1 0x01 | |
60 | #define REG_PIH_ISR_P2 0x02 | |
61 | #define REG_PIH_SIR 0x03 /* for testing */ | |
62 | ||
63 | ||
64 | /* Linux could (eventually) use either IRQ line */ | |
65 | static int irq_line; | |
66 | ||
67 | struct sih { | |
68 | char name[8]; | |
69 | u8 module; /* module id */ | |
70 | u8 control_offset; /* for SIH_CTRL */ | |
71 | bool set_cor; | |
72 | ||
73 | u8 bits; /* valid in isr/imr */ | |
74 | u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ | |
75 | ||
76 | u8 edr_offset; | |
77 | u8 bytes_edr; /* bytelen of EDR */ | |
78 | ||
1920a61e IK |
79 | u8 irq_lines; /* number of supported irq lines */ |
80 | ||
a30d46c0 | 81 | /* SIR ignored -- set interrupt, for testing only */ |
35a27e8e | 82 | struct sih_irq_data { |
a30d46c0 DB |
83 | u8 isr_offset; |
84 | u8 imr_offset; | |
85 | } mask[2]; | |
86 | /* + 2 bytes padding */ | |
87 | }; | |
88 | ||
1920a61e IK |
89 | static const struct sih *sih_modules; |
90 | static int nr_sih_modules; | |
91 | ||
a30d46c0 DB |
92 | #define SIH_INITIALIZER(modname, nbits) \ |
93 | .module = TWL4030_MODULE_ ## modname, \ | |
94 | .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ | |
95 | .bits = nbits, \ | |
96 | .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ | |
97 | .edr_offset = TWL4030_ ## modname ## _EDR, \ | |
98 | .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ | |
1920a61e | 99 | .irq_lines = 2, \ |
a30d46c0 DB |
100 | .mask = { { \ |
101 | .isr_offset = TWL4030_ ## modname ## _ISR1, \ | |
102 | .imr_offset = TWL4030_ ## modname ## _IMR1, \ | |
103 | }, \ | |
104 | { \ | |
105 | .isr_offset = TWL4030_ ## modname ## _ISR2, \ | |
106 | .imr_offset = TWL4030_ ## modname ## _IMR2, \ | |
107 | }, }, | |
108 | ||
109 | /* register naming policies are inconsistent ... */ | |
110 | #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 | |
111 | #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD | |
112 | #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT | |
113 | ||
114 | ||
115 | /* Order in this table matches order in PIH_ISR. That is, | |
116 | * BIT(n) in PIH_ISR is sih_modules[n]. | |
117 | */ | |
1920a61e IK |
118 | /* sih_modules_twl4030 is used both in twl4030 and twl5030 */ |
119 | static const struct sih sih_modules_twl4030[6] = { | |
a30d46c0 DB |
120 | [0] = { |
121 | .name = "gpio", | |
122 | .module = TWL4030_MODULE_GPIO, | |
123 | .control_offset = REG_GPIO_SIH_CTRL, | |
124 | .set_cor = true, | |
125 | .bits = TWL4030_GPIO_MAX, | |
126 | .bytes_ixr = 3, | |
127 | /* Note: *all* of these IRQs default to no-trigger */ | |
128 | .edr_offset = REG_GPIO_EDR1, | |
129 | .bytes_edr = 5, | |
1920a61e | 130 | .irq_lines = 2, |
a30d46c0 DB |
131 | .mask = { { |
132 | .isr_offset = REG_GPIO_ISR1A, | |
133 | .imr_offset = REG_GPIO_IMR1A, | |
134 | }, { | |
135 | .isr_offset = REG_GPIO_ISR1B, | |
136 | .imr_offset = REG_GPIO_IMR1B, | |
137 | }, }, | |
138 | }, | |
139 | [1] = { | |
140 | .name = "keypad", | |
141 | .set_cor = true, | |
142 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
143 | }, | |
144 | [2] = { | |
145 | .name = "bci", | |
146 | .module = TWL4030_MODULE_INTERRUPTS, | |
147 | .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, | |
8e52e279 | 148 | .set_cor = true, |
a30d46c0 DB |
149 | .bits = 12, |
150 | .bytes_ixr = 2, | |
151 | .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, | |
152 | /* Note: most of these IRQs default to no-trigger */ | |
153 | .bytes_edr = 3, | |
1920a61e | 154 | .irq_lines = 2, |
a30d46c0 DB |
155 | .mask = { { |
156 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, | |
157 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, | |
158 | }, { | |
159 | .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, | |
160 | .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, | |
161 | }, }, | |
162 | }, | |
163 | [3] = { | |
164 | .name = "madc", | |
165 | SIH_INITIALIZER(MADC, 4) | |
166 | }, | |
167 | [4] = { | |
168 | /* USB doesn't use the same SIH organization */ | |
169 | .name = "usb", | |
170 | }, | |
171 | [5] = { | |
172 | .name = "power", | |
173 | .set_cor = true, | |
174 | SIH_INITIALIZER(INT_PWR, 8) | |
175 | }, | |
176 | /* there are no SIH modules #6 or #7 ... */ | |
177 | }; | |
178 | ||
1920a61e IK |
179 | static const struct sih sih_modules_twl5031[8] = { |
180 | [0] = { | |
181 | .name = "gpio", | |
182 | .module = TWL4030_MODULE_GPIO, | |
183 | .control_offset = REG_GPIO_SIH_CTRL, | |
184 | .set_cor = true, | |
185 | .bits = TWL4030_GPIO_MAX, | |
186 | .bytes_ixr = 3, | |
187 | /* Note: *all* of these IRQs default to no-trigger */ | |
188 | .edr_offset = REG_GPIO_EDR1, | |
189 | .bytes_edr = 5, | |
190 | .irq_lines = 2, | |
191 | .mask = { { | |
192 | .isr_offset = REG_GPIO_ISR1A, | |
193 | .imr_offset = REG_GPIO_IMR1A, | |
194 | }, { | |
195 | .isr_offset = REG_GPIO_ISR1B, | |
196 | .imr_offset = REG_GPIO_IMR1B, | |
197 | }, }, | |
198 | }, | |
199 | [1] = { | |
200 | .name = "keypad", | |
201 | .set_cor = true, | |
202 | SIH_INITIALIZER(KEYPAD_KEYP, 4) | |
203 | }, | |
204 | [2] = { | |
205 | .name = "bci", | |
206 | .module = TWL5031_MODULE_INTERRUPTS, | |
207 | .control_offset = TWL5031_INTERRUPTS_BCISIHCTRL, | |
208 | .bits = 7, | |
209 | .bytes_ixr = 1, | |
210 | .edr_offset = TWL5031_INTERRUPTS_BCIEDR1, | |
211 | /* Note: most of these IRQs default to no-trigger */ | |
212 | .bytes_edr = 2, | |
213 | .irq_lines = 2, | |
214 | .mask = { { | |
215 | .isr_offset = TWL5031_INTERRUPTS_BCIISR1, | |
216 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR1, | |
217 | }, { | |
218 | .isr_offset = TWL5031_INTERRUPTS_BCIISR2, | |
219 | .imr_offset = TWL5031_INTERRUPTS_BCIIMR2, | |
220 | }, }, | |
221 | }, | |
222 | [3] = { | |
223 | .name = "madc", | |
224 | SIH_INITIALIZER(MADC, 4) | |
225 | }, | |
226 | [4] = { | |
227 | /* USB doesn't use the same SIH organization */ | |
228 | .name = "usb", | |
229 | }, | |
230 | [5] = { | |
231 | .name = "power", | |
232 | .set_cor = true, | |
233 | SIH_INITIALIZER(INT_PWR, 8) | |
234 | }, | |
235 | [6] = { | |
236 | /* | |
191211f5 IK |
237 | * ECI/DBI doesn't use the same SIH organization. |
238 | * For example, it supports only one interrupt output line. | |
239 | * That is, the interrupts are seen on both INT1 and INT2 lines. | |
1920a61e | 240 | */ |
191211f5 | 241 | .name = "eci_dbi", |
1920a61e IK |
242 | .module = TWL5031_MODULE_ACCESSORY, |
243 | .bits = 9, | |
244 | .bytes_ixr = 2, | |
245 | .irq_lines = 1, | |
246 | .mask = { { | |
247 | .isr_offset = TWL5031_ACIIDR_LSB, | |
248 | .imr_offset = TWL5031_ACIIMR_LSB, | |
249 | }, }, | |
250 | ||
251 | }, | |
252 | [7] = { | |
191211f5 IK |
253 | /* Audio accessory */ |
254 | .name = "audio", | |
1920a61e IK |
255 | .module = TWL5031_MODULE_ACCESSORY, |
256 | .control_offset = TWL5031_ACCSIHCTRL, | |
257 | .bits = 2, | |
258 | .bytes_ixr = 1, | |
259 | .edr_offset = TWL5031_ACCEDR1, | |
260 | /* Note: most of these IRQs default to no-trigger */ | |
261 | .bytes_edr = 1, | |
262 | .irq_lines = 2, | |
263 | .mask = { { | |
264 | .isr_offset = TWL5031_ACCISR1, | |
265 | .imr_offset = TWL5031_ACCIMR1, | |
266 | }, { | |
267 | .isr_offset = TWL5031_ACCISR2, | |
268 | .imr_offset = TWL5031_ACCIMR2, | |
269 | }, }, | |
270 | }, | |
271 | }; | |
272 | ||
a30d46c0 DB |
273 | #undef TWL4030_MODULE_KEYPAD_KEYP |
274 | #undef TWL4030_MODULE_INT_PWR | |
275 | #undef TWL4030_INT_PWR_EDR | |
276 | ||
277 | /*----------------------------------------------------------------------*/ | |
278 | ||
279 | static unsigned twl4030_irq_base; | |
280 | ||
281 | static struct completion irq_event; | |
282 | ||
283 | /* | |
284 | * This thread processes interrupts reported by the Primary Interrupt Handler. | |
285 | */ | |
286 | static int twl4030_irq_thread(void *data) | |
287 | { | |
288 | long irq = (long)data; | |
a30d46c0 | 289 | static unsigned i2c_errors; |
3446d4bb | 290 | static const unsigned max_i2c_errors = 100; |
a30d46c0 | 291 | |
94964f96 | 292 | |
a30d46c0 DB |
293 | current->flags |= PF_NOFREEZE; |
294 | ||
295 | while (!kthread_should_stop()) { | |
296 | int ret; | |
297 | int module_irq; | |
298 | u8 pih_isr; | |
299 | ||
300 | /* Wait for IRQ, then read PIH irq status (also blocking) */ | |
301 | wait_for_completion_interruptible(&irq_event); | |
302 | ||
fc7b92fc | 303 | ret = twl_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, |
a30d46c0 DB |
304 | REG_PIH_ISR_P1); |
305 | if (ret) { | |
306 | pr_warning("twl4030: I2C error %d reading PIH ISR\n", | |
307 | ret); | |
308 | if (++i2c_errors >= max_i2c_errors) { | |
309 | printk(KERN_ERR "Maximum I2C error count" | |
310 | " exceeded. Terminating %s.\n", | |
311 | __func__); | |
312 | break; | |
313 | } | |
314 | complete(&irq_event); | |
315 | continue; | |
316 | } | |
317 | ||
318 | /* these handlers deal with the relevant SIH irq status */ | |
319 | local_irq_disable(); | |
320 | for (module_irq = twl4030_irq_base; | |
321 | pih_isr; | |
322 | pih_isr >>= 1, module_irq++) { | |
323 | if (pih_isr & 0x1) { | |
94964f96 SO |
324 | struct irq_desc *d = irq_to_desc(module_irq); |
325 | ||
326 | if (!d) { | |
327 | pr_err("twl4030: Invalid SIH IRQ: %d\n", | |
328 | module_irq); | |
329 | return -EINVAL; | |
330 | } | |
a30d46c0 DB |
331 | |
332 | /* These can't be masked ... always warn | |
333 | * if we get any surprises. | |
334 | */ | |
335 | if (d->status & IRQ_DISABLED) | |
336 | note_interrupt(module_irq, d, | |
337 | IRQ_NONE); | |
338 | else | |
339 | d->handle_irq(module_irq, d); | |
340 | } | |
341 | } | |
342 | local_irq_enable(); | |
343 | ||
1cef8e41 | 344 | enable_irq(irq); |
a30d46c0 DB |
345 | } |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | /* | |
351 | * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. | |
352 | * This is a chained interrupt, so there is no desc->action method for it. | |
353 | * Now we need to query the interrupt controller in the twl4030 to determine | |
354 | * which module is generating the interrupt request. However, we can't do i2c | |
355 | * transactions in interrupt context, so we must defer that work to a kernel | |
356 | * thread. All we do here is acknowledge and mask the interrupt and wakeup | |
357 | * the kernel thread. | |
358 | */ | |
1cef8e41 | 359 | static irqreturn_t handle_twl4030_pih(int irq, void *devid) |
a30d46c0 DB |
360 | { |
361 | /* Acknowledge, clear *AND* mask the interrupt... */ | |
1cef8e41 RK |
362 | disable_irq_nosync(irq); |
363 | complete(devid); | |
364 | return IRQ_HANDLED; | |
a30d46c0 | 365 | } |
a30d46c0 DB |
366 | /*----------------------------------------------------------------------*/ |
367 | ||
368 | /* | |
369 | * twl4030_init_sih_modules() ... start from a known state where no | |
370 | * IRQs will be coming in, and where we can quickly enable them then | |
371 | * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. | |
372 | * | |
373 | * NOTE: we don't touch EDR registers here; they stay with hardware | |
374 | * defaults or whatever the last value was. Note that when both EDR | |
375 | * bits for an IRQ are clear, that's as if its IMR bit is set... | |
376 | */ | |
377 | static int twl4030_init_sih_modules(unsigned line) | |
378 | { | |
379 | const struct sih *sih; | |
380 | u8 buf[4]; | |
381 | int i; | |
382 | int status; | |
383 | ||
384 | /* line 0 == int1_n signal; line 1 == int2_n signal */ | |
385 | if (line > 1) | |
386 | return -EINVAL; | |
387 | ||
388 | irq_line = line; | |
389 | ||
390 | /* disable all interrupts on our line */ | |
391 | memset(buf, 0xff, sizeof buf); | |
392 | sih = sih_modules; | |
1920a61e | 393 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
394 | |
395 | /* skip USB -- it's funky */ | |
396 | if (!sih->bytes_ixr) | |
397 | continue; | |
398 | ||
1920a61e IK |
399 | /* Not all the SIH modules support multiple interrupt lines */ |
400 | if (sih->irq_lines <= line) | |
401 | continue; | |
402 | ||
fc7b92fc | 403 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
404 | sih->mask[line].imr_offset, sih->bytes_ixr); |
405 | if (status < 0) | |
406 | pr_err("twl4030: err %d initializing %s %s\n", | |
407 | status, sih->name, "IMR"); | |
408 | ||
409 | /* Maybe disable "exclusive" mode; buffer second pending irq; | |
410 | * set Clear-On-Read (COR) bit. | |
411 | * | |
412 | * NOTE that sometimes COR polarity is documented as being | |
8e52e279 | 413 | * inverted: for MADC, COR=1 means "clear on write". |
a30d46c0 DB |
414 | * And for PWR_INT it's not documented... |
415 | */ | |
416 | if (sih->set_cor) { | |
fc7b92fc | 417 | status = twl_i2c_write_u8(sih->module, |
a30d46c0 DB |
418 | TWL4030_SIH_CTRL_COR_MASK, |
419 | sih->control_offset); | |
420 | if (status < 0) | |
421 | pr_err("twl4030: err %d initializing %s %s\n", | |
422 | status, sih->name, "SIH_CTRL"); | |
423 | } | |
424 | } | |
425 | ||
426 | sih = sih_modules; | |
1920a61e | 427 | for (i = 0; i < nr_sih_modules; i++, sih++) { |
a30d46c0 DB |
428 | u8 rxbuf[4]; |
429 | int j; | |
430 | ||
431 | /* skip USB */ | |
432 | if (!sih->bytes_ixr) | |
433 | continue; | |
434 | ||
1920a61e IK |
435 | /* Not all the SIH modules support multiple interrupt lines */ |
436 | if (sih->irq_lines <= line) | |
437 | continue; | |
438 | ||
a30d46c0 DB |
439 | /* Clear pending interrupt status. Either the read was |
440 | * enough, or we need to write those bits. Repeat, in | |
441 | * case an IRQ is pending (PENDDIS=0) ... that's not | |
442 | * uncommon with PWR_INT.PWRON. | |
443 | */ | |
444 | for (j = 0; j < 2; j++) { | |
fc7b92fc | 445 | status = twl_i2c_read(sih->module, rxbuf, |
a30d46c0 DB |
446 | sih->mask[line].isr_offset, sih->bytes_ixr); |
447 | if (status < 0) | |
448 | pr_err("twl4030: err %d initializing %s %s\n", | |
449 | status, sih->name, "ISR"); | |
450 | ||
451 | if (!sih->set_cor) | |
fc7b92fc | 452 | status = twl_i2c_write(sih->module, buf, |
a30d46c0 DB |
453 | sih->mask[line].isr_offset, |
454 | sih->bytes_ixr); | |
455 | /* else COR=1 means read sufficed. | |
456 | * (for most SIH modules...) | |
457 | */ | |
458 | } | |
459 | } | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | static inline void activate_irq(int irq) | |
465 | { | |
466 | #ifdef CONFIG_ARM | |
467 | /* ARM requires an extra step to clear IRQ_NOREQUEST, which it | |
468 | * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. | |
469 | */ | |
470 | set_irq_flags(irq, IRQF_VALID); | |
471 | #else | |
472 | /* same effect on other architectures */ | |
473 | set_irq_noprobe(irq); | |
474 | #endif | |
475 | } | |
476 | ||
477 | /*----------------------------------------------------------------------*/ | |
478 | ||
479 | static DEFINE_SPINLOCK(sih_agent_lock); | |
480 | ||
481 | static struct workqueue_struct *wq; | |
482 | ||
483 | struct sih_agent { | |
484 | int irq_base; | |
485 | const struct sih *sih; | |
486 | ||
487 | u32 imr; | |
488 | bool imr_change_pending; | |
489 | struct work_struct mask_work; | |
490 | ||
491 | u32 edge_change; | |
492 | struct work_struct edge_work; | |
493 | }; | |
494 | ||
495 | static void twl4030_sih_do_mask(struct work_struct *work) | |
496 | { | |
497 | struct sih_agent *agent; | |
498 | const struct sih *sih; | |
499 | union { | |
500 | u8 bytes[4]; | |
501 | u32 word; | |
502 | } imr; | |
503 | int status; | |
504 | ||
505 | agent = container_of(work, struct sih_agent, mask_work); | |
506 | ||
507 | /* see what work we have */ | |
508 | spin_lock_irq(&sih_agent_lock); | |
509 | if (agent->imr_change_pending) { | |
510 | sih = agent->sih; | |
511 | /* byte[0] gets overwritten as we write ... */ | |
512 | imr.word = cpu_to_le32(agent->imr << 8); | |
513 | agent->imr_change_pending = false; | |
514 | } else | |
515 | sih = NULL; | |
516 | spin_unlock_irq(&sih_agent_lock); | |
517 | if (!sih) | |
518 | return; | |
519 | ||
520 | /* write the whole mask ... simpler than subsetting it */ | |
fc7b92fc | 521 | status = twl_i2c_write(sih->module, imr.bytes, |
a30d46c0 DB |
522 | sih->mask[irq_line].imr_offset, sih->bytes_ixr); |
523 | if (status) | |
524 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
525 | "write", status); | |
526 | } | |
527 | ||
528 | static void twl4030_sih_do_edge(struct work_struct *work) | |
529 | { | |
530 | struct sih_agent *agent; | |
531 | const struct sih *sih; | |
532 | u8 bytes[6]; | |
533 | u32 edge_change; | |
534 | int status; | |
535 | ||
536 | agent = container_of(work, struct sih_agent, edge_work); | |
537 | ||
538 | /* see what work we have */ | |
539 | spin_lock_irq(&sih_agent_lock); | |
540 | edge_change = agent->edge_change; | |
df10d646 | 541 | agent->edge_change = 0; |
a30d46c0 DB |
542 | sih = edge_change ? agent->sih : NULL; |
543 | spin_unlock_irq(&sih_agent_lock); | |
544 | if (!sih) | |
545 | return; | |
546 | ||
547 | /* Read, reserving first byte for write scratch. Yes, this | |
548 | * could be cached for some speedup ... but be careful about | |
549 | * any processor on the other IRQ line, EDR registers are | |
550 | * shared. | |
551 | */ | |
fc7b92fc | 552 | status = twl_i2c_read(sih->module, bytes + 1, |
a30d46c0 DB |
553 | sih->edr_offset, sih->bytes_edr); |
554 | if (status) { | |
555 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
556 | "read", status); | |
557 | return; | |
558 | } | |
559 | ||
560 | /* Modify only the bits we know must change */ | |
561 | while (edge_change) { | |
562 | int i = fls(edge_change) - 1; | |
94964f96 | 563 | struct irq_desc *d = irq_to_desc(i + agent->irq_base); |
a30d46c0 DB |
564 | int byte = 1 + (i >> 2); |
565 | int off = (i & 0x3) * 2; | |
566 | ||
94964f96 SO |
567 | if (!d) { |
568 | pr_err("twl4030: Invalid IRQ: %d\n", | |
569 | i + agent->irq_base); | |
570 | return; | |
571 | } | |
572 | ||
a30d46c0 DB |
573 | bytes[byte] &= ~(0x03 << off); |
574 | ||
cd6e125c | 575 | raw_spin_lock_irq(&d->lock); |
a30d46c0 DB |
576 | if (d->status & IRQ_TYPE_EDGE_RISING) |
577 | bytes[byte] |= BIT(off + 1); | |
578 | if (d->status & IRQ_TYPE_EDGE_FALLING) | |
579 | bytes[byte] |= BIT(off + 0); | |
cd6e125c | 580 | raw_spin_unlock_irq(&d->lock); |
a30d46c0 DB |
581 | |
582 | edge_change &= ~BIT(i); | |
583 | } | |
584 | ||
585 | /* Write */ | |
fc7b92fc | 586 | status = twl_i2c_write(sih->module, bytes, |
a30d46c0 DB |
587 | sih->edr_offset, sih->bytes_edr); |
588 | if (status) | |
589 | pr_err("twl4030: %s, %s --> %d\n", __func__, | |
590 | "write", status); | |
591 | } | |
592 | ||
593 | /*----------------------------------------------------------------------*/ | |
594 | ||
595 | /* | |
596 | * All irq_chip methods get issued from code holding irq_desc[irq].lock, | |
597 | * which can't perform the underlying I2C operations (because they sleep). | |
598 | * So we must hand them off to a thread (workqueue) and cope with asynch | |
599 | * completion, potentially including some re-ordering, of these requests. | |
600 | */ | |
601 | ||
845aeab5 | 602 | static void twl4030_sih_mask(struct irq_data *data) |
a30d46c0 | 603 | { |
845aeab5 | 604 | struct sih_agent *sih = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
605 | unsigned long flags; |
606 | ||
607 | spin_lock_irqsave(&sih_agent_lock, flags); | |
845aeab5 | 608 | sih->imr |= BIT(data->irq - sih->irq_base); |
a30d46c0 DB |
609 | sih->imr_change_pending = true; |
610 | queue_work(wq, &sih->mask_work); | |
611 | spin_unlock_irqrestore(&sih_agent_lock, flags); | |
612 | } | |
613 | ||
845aeab5 | 614 | static void twl4030_sih_unmask(struct irq_data *data) |
a30d46c0 | 615 | { |
845aeab5 | 616 | struct sih_agent *sih = irq_data_get_irq_chip_data(data); |
a30d46c0 DB |
617 | unsigned long flags; |
618 | ||
619 | spin_lock_irqsave(&sih_agent_lock, flags); | |
845aeab5 | 620 | sih->imr &= ~BIT(data->irq - sih->irq_base); |
a30d46c0 DB |
621 | sih->imr_change_pending = true; |
622 | queue_work(wq, &sih->mask_work); | |
623 | spin_unlock_irqrestore(&sih_agent_lock, flags); | |
624 | } | |
625 | ||
845aeab5 | 626 | static int twl4030_sih_set_type(struct irq_data *data, unsigned trigger) |
a30d46c0 | 627 | { |
845aeab5 MB |
628 | struct sih_agent *sih = irq_data_get_irq_chip_data(data); |
629 | struct irq_desc *desc = irq_to_desc(data->irq); | |
a30d46c0 DB |
630 | unsigned long flags; |
631 | ||
94964f96 | 632 | if (!desc) { |
845aeab5 | 633 | pr_err("twl4030: Invalid IRQ: %d\n", data->irq); |
94964f96 SO |
634 | return -EINVAL; |
635 | } | |
636 | ||
a30d46c0 DB |
637 | if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
638 | return -EINVAL; | |
639 | ||
640 | spin_lock_irqsave(&sih_agent_lock, flags); | |
641 | if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) { | |
642 | desc->status &= ~IRQ_TYPE_SENSE_MASK; | |
643 | desc->status |= trigger; | |
845aeab5 | 644 | sih->edge_change |= BIT(data->irq - sih->irq_base); |
a30d46c0 DB |
645 | queue_work(wq, &sih->edge_work); |
646 | } | |
647 | spin_unlock_irqrestore(&sih_agent_lock, flags); | |
648 | return 0; | |
649 | } | |
650 | ||
651 | static struct irq_chip twl4030_sih_irq_chip = { | |
652 | .name = "twl4030", | |
845aeab5 MB |
653 | .irq_mask = twl4030_sih_mask, |
654 | .irq_unmask = twl4030_sih_unmask, | |
655 | .irq_set_type = twl4030_sih_set_type, | |
a30d46c0 DB |
656 | }; |
657 | ||
658 | /*----------------------------------------------------------------------*/ | |
659 | ||
660 | static inline int sih_read_isr(const struct sih *sih) | |
661 | { | |
662 | int status; | |
663 | union { | |
664 | u8 bytes[4]; | |
665 | u32 word; | |
666 | } isr; | |
667 | ||
668 | /* FIXME need retry-on-error ... */ | |
669 | ||
670 | isr.word = 0; | |
fc7b92fc | 671 | status = twl_i2c_read(sih->module, isr.bytes, |
a30d46c0 DB |
672 | sih->mask[irq_line].isr_offset, sih->bytes_ixr); |
673 | ||
674 | return (status < 0) ? status : le32_to_cpu(isr.word); | |
675 | } | |
676 | ||
677 | /* | |
678 | * Generic handler for SIH interrupts ... we "know" this is called | |
679 | * in task context, with IRQs enabled. | |
680 | */ | |
681 | static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) | |
682 | { | |
683 | struct sih_agent *agent = get_irq_data(irq); | |
684 | const struct sih *sih = agent->sih; | |
685 | int isr; | |
686 | ||
687 | /* reading ISR acks the IRQs, using clear-on-read mode */ | |
688 | local_irq_enable(); | |
689 | isr = sih_read_isr(sih); | |
690 | local_irq_disable(); | |
691 | ||
692 | if (isr < 0) { | |
693 | pr_err("twl4030: %s SIH, read ISR error %d\n", | |
694 | sih->name, isr); | |
695 | /* REVISIT: recover; eventually mask it all, etc */ | |
696 | return; | |
697 | } | |
698 | ||
699 | while (isr) { | |
700 | irq = fls(isr); | |
701 | irq--; | |
702 | isr &= ~BIT(irq); | |
703 | ||
704 | if (irq < sih->bits) | |
705 | generic_handle_irq(agent->irq_base + irq); | |
706 | else | |
707 | pr_err("twl4030: %s SIH, invalid ISR bit %d\n", | |
708 | sih->name, irq); | |
709 | } | |
710 | } | |
711 | ||
712 | static unsigned twl4030_irq_next; | |
713 | ||
714 | /* returns the first IRQ used by this SIH bank, | |
715 | * or negative errno | |
716 | */ | |
717 | int twl4030_sih_setup(int module) | |
718 | { | |
719 | int sih_mod; | |
720 | const struct sih *sih = NULL; | |
721 | struct sih_agent *agent; | |
722 | int i, irq; | |
723 | int status = -EINVAL; | |
724 | unsigned irq_base = twl4030_irq_next; | |
725 | ||
726 | /* only support modules with standard clear-on-read for now */ | |
727 | for (sih_mod = 0, sih = sih_modules; | |
1920a61e | 728 | sih_mod < nr_sih_modules; |
a30d46c0 DB |
729 | sih_mod++, sih++) { |
730 | if (sih->module == module && sih->set_cor) { | |
731 | if (!WARN((irq_base + sih->bits) > NR_IRQS, | |
732 | "irq %d for %s too big\n", | |
733 | irq_base + sih->bits, | |
734 | sih->name)) | |
735 | status = 0; | |
736 | break; | |
737 | } | |
738 | } | |
739 | if (status < 0) | |
740 | return status; | |
741 | ||
742 | agent = kzalloc(sizeof *agent, GFP_KERNEL); | |
743 | if (!agent) | |
744 | return -ENOMEM; | |
745 | ||
746 | status = 0; | |
747 | ||
748 | agent->irq_base = irq_base; | |
749 | agent->sih = sih; | |
750 | agent->imr = ~0; | |
751 | INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); | |
752 | INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); | |
753 | ||
754 | for (i = 0; i < sih->bits; i++) { | |
755 | irq = irq_base + i; | |
756 | ||
757 | set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip, | |
758 | handle_edge_irq); | |
759 | set_irq_chip_data(irq, agent); | |
760 | activate_irq(irq); | |
761 | } | |
762 | ||
763 | status = irq_base; | |
764 | twl4030_irq_next += i; | |
765 | ||
766 | /* replace generic PIH handler (handle_simple_irq) */ | |
767 | irq = sih_mod + twl4030_irq_base; | |
768 | set_irq_data(irq, agent); | |
769 | set_irq_chained_handler(irq, handle_twl4030_sih); | |
770 | ||
771 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, | |
772 | irq, irq_base, twl4030_irq_next - 1); | |
773 | ||
774 | return status; | |
775 | } | |
776 | ||
777 | /* FIXME need a call to reverse twl4030_sih_setup() ... */ | |
778 | ||
779 | ||
780 | /*----------------------------------------------------------------------*/ | |
781 | ||
782 | /* FIXME pass in which interrupt line we'll use ... */ | |
783 | #define twl_irq_line 0 | |
784 | ||
e8deb28c | 785 | int twl4030_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) |
a30d46c0 DB |
786 | { |
787 | static struct irq_chip twl4030_irq_chip; | |
788 | ||
789 | int status; | |
790 | int i; | |
791 | struct task_struct *task; | |
792 | ||
793 | /* | |
794 | * Mask and clear all TWL4030 interrupts since initially we do | |
795 | * not have any TWL4030 module interrupt handlers present | |
796 | */ | |
797 | status = twl4030_init_sih_modules(twl_irq_line); | |
798 | if (status < 0) | |
799 | return status; | |
800 | ||
801 | wq = create_singlethread_workqueue("twl4030-irqchip"); | |
802 | if (!wq) { | |
803 | pr_err("twl4030: workqueue FAIL\n"); | |
804 | return -ESRCH; | |
805 | } | |
806 | ||
807 | twl4030_irq_base = irq_base; | |
808 | ||
809 | /* install an irq handler for each of the SIH modules; | |
810 | * clone dummy irq_chip since PIH can't *do* anything | |
811 | */ | |
812 | twl4030_irq_chip = dummy_irq_chip; | |
813 | twl4030_irq_chip.name = "twl4030"; | |
814 | ||
fe212213 | 815 | twl4030_sih_irq_chip.irq_ack = dummy_irq_chip.irq_ack; |
a30d46c0 DB |
816 | |
817 | for (i = irq_base; i < irq_end; i++) { | |
818 | set_irq_chip_and_handler(i, &twl4030_irq_chip, | |
819 | handle_simple_irq); | |
820 | activate_irq(i); | |
821 | } | |
822 | twl4030_irq_next = i; | |
823 | pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", | |
824 | irq_num, irq_base, twl4030_irq_next - 1); | |
825 | ||
826 | /* ... and the PWR_INT module ... */ | |
827 | status = twl4030_sih_setup(TWL4030_MODULE_INT); | |
828 | if (status < 0) { | |
829 | pr_err("twl4030: sih_setup PWR INT --> %d\n", status); | |
830 | goto fail; | |
831 | } | |
832 | ||
833 | /* install an irq handler to demultiplex the TWL4030 interrupt */ | |
a30d46c0 | 834 | |
a30d46c0 | 835 | |
1cef8e41 | 836 | init_completion(&irq_event); |
a30d46c0 | 837 | |
1cef8e41 RK |
838 | status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED, |
839 | "TWL4030-PIH", &irq_event); | |
840 | if (status < 0) { | |
841 | pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status); | |
842 | goto fail_rqirq; | |
843 | } | |
844 | ||
89f5f9f7 AC |
845 | task = kthread_run(twl4030_irq_thread, (void *)(long)irq_num, |
846 | "twl4030-irq"); | |
1cef8e41 RK |
847 | if (IS_ERR(task)) { |
848 | pr_err("twl4030: could not create irq %d thread!\n", irq_num); | |
849 | status = PTR_ERR(task); | |
850 | goto fail_kthread; | |
851 | } | |
852 | return status; | |
853 | fail_kthread: | |
854 | free_irq(irq_num, &irq_event); | |
855 | fail_rqirq: | |
856 | /* clean up twl4030_sih_setup */ | |
a30d46c0 DB |
857 | fail: |
858 | for (i = irq_base; i < irq_end; i++) | |
859 | set_irq_chip_and_handler(i, NULL, NULL); | |
860 | destroy_workqueue(wq); | |
861 | wq = NULL; | |
862 | return status; | |
863 | } | |
864 | ||
e8deb28c | 865 | int twl4030_exit_irq(void) |
a30d46c0 DB |
866 | { |
867 | /* FIXME undo twl_init_irq() */ | |
868 | if (twl4030_irq_base) { | |
869 | pr_err("twl4030: can't yet clean up IRQs?\n"); | |
870 | return -ENOSYS; | |
871 | } | |
872 | return 0; | |
873 | } | |
1920a61e | 874 | |
e8deb28c | 875 | int twl4030_init_chip_irq(const char *chip) |
1920a61e IK |
876 | { |
877 | if (!strcmp(chip, "twl5031")) { | |
878 | sih_modules = sih_modules_twl5031; | |
879 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl5031); | |
880 | } else { | |
881 | sih_modules = sih_modules_twl4030; | |
882 | nr_sih_modules = ARRAY_SIZE(sih_modules_twl4030); | |
883 | } | |
884 | ||
885 | return 0; | |
886 | } |