[linux-2.6-block.git] / drivers / mfd / ti_am335x_tscadc.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * TI Touch Screen / ADC MFD driver
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/sched.h>

#include <linux/mfd/ti_am335x_tscadc.h>

static const struct regmap_config tscadc_regmap_config = {
	.name = "ti_tscadc",
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
};

void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->reg_se_cache |= val;
	if (tscadc->adc_waiting)
		wake_up(&tscadc->reg_se_wait);
	else if (!tscadc->adc_in_use)
		regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);

	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);

static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
{
	DEFINE_WAIT(wait);
	u32 reg;

	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
	if (reg & SEQ_STATUS) {
		tscadc->adc_waiting = true;
		prepare_to_wait(&tscadc->reg_se_wait, &wait,
				TASK_UNINTERRUPTIBLE);
		spin_unlock_irq(&tscadc->reg_lock);

		schedule();

		spin_lock_irq(&tscadc->reg_lock);
		finish_wait(&tscadc->reg_se_wait, &wait);

		/*
		 * Sequencer should either be idle or
		 * busy applying the charge step.
		 */
		regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
		WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
		tscadc->adc_waiting = false;
	}
	tscadc->adc_in_use = true;
}

void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
{
	spin_lock_irq(&tscadc->reg_lock);
	am335x_tscadc_need_adc(tscadc);

	regmap_write(tscadc->regmap, REG_SE, val);
	spin_unlock_irq(&tscadc->reg_lock);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);

void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->adc_in_use = false;
	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);

void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->reg_se_cache &= ~val;
	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);

static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
{
	unsigned int idleconfig;

	idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
			STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;

	regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
}

static	int ti_tscadc_probe(struct platform_device *pdev)
{
	struct ti_tscadc_dev *tscadc;
	struct resource *res;
	struct clk *clk;
	struct device_node *node;
	struct mfd_cell *cell;
	struct property *prop;
	const __be32 *cur;
	u32 val;
	int err, ctrl;
	int tsc_wires = 0, adc_channels = 0, total_channels;
	int readouts = 0;

	/* Allocate memory for device */
	tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
	if (!tscadc)
		return -ENOMEM;

	tscadc->dev = &pdev->dev;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "Could not find valid DT data.\n");
		return -EINVAL;
	}

	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
	of_property_read_u32(node, "ti,wires", &tsc_wires);
	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
	of_node_put(node);

	node = of_get_child_by_name(pdev->dev.of_node, "adc");
	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
		adc_channels++;
		if (val > 7) {
			dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
				val);
			of_node_put(node);
			return -EINVAL;
		}
	}

	of_node_put(node);

	total_channels = tsc_wires + adc_channels;
	if (total_channels > 8) {
		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
		return -EINVAL;
	}

	if (total_channels == 0) {
		dev_err(&pdev->dev, "Need atleast one channel.\n");
		return -EINVAL;
	}

	if (readouts * 2 + 2 + adc_channels > 16) {
		dev_err(&pdev->dev, "Too many step configurations requested\n");
		return -EINVAL;
	}

	err = platform_get_irq(pdev, 0);
	if (err < 0)
		return err;
	else
		tscadc->irq = err;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(tscadc->tscadc_base))
		return PTR_ERR(tscadc->tscadc_base);

	tscadc->tscadc_phys_base = res->start;
	tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
					       tscadc->tscadc_base,
					       &tscadc_regmap_config);
	if (IS_ERR(tscadc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(tscadc->regmap);
	}

	spin_lock_init(&tscadc->reg_lock);
	init_waitqueue_head(&tscadc->reg_se_wait);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	/*
	 * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK.
	 * ADCs produce a 12-bit sample every 15 ADC_CLK cycles.
	 * am33xx ADCs expect to capture 200ksps.
	 * We need the ADC clocks to run at 3MHz.
	 * This frequency is valid since TSC_ADC_SS controller design
	 * assumes the OCP clock is at least 6x faster than the ADC clock.
	 */
	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get TSC fck\n");
		err = PTR_ERR(clk);
		goto err_disable_clk;
	}

	tscadc->clk_div = (clk_get_rate(clk) / ADC_CLK) - 1;
	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);

	/* Set the control register bits */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	/* Set register bits for Idle Config Mode */
	if (tsc_wires > 0) {
		tscadc->tsc_wires = tsc_wires;
		if (tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc);
	}

	/* Enable the TSC module enable bit */
	ctrl |= CNTRLREG_TSCSSENB;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	tscadc->used_cells = 0;
	tscadc->tsc_cell = -1;
	tscadc->adc_cell = -1;

	/* TSC Cell */
	if (tsc_wires > 0) {
		tscadc->tsc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-tsc";
		cell->of_compatible = "ti,am3359-tsc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	/* ADC Cell */
	if (adc_channels > 0) {
		tscadc->adc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-adc";
		cell->of_compatible = "ti,am3359-adc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
			      tscadc->cells, tscadc->used_cells, NULL,
			      0, NULL);
	if (err < 0)
		goto err_disable_clk;

	platform_set_drvdata(pdev, tscadc);
	return 0;

err_disable_clk:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	return err;
}

static int ti_tscadc_remove(struct platform_device *pdev)
{
	struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);

	regmap_write(tscadc->regmap, REG_SE, 0x00);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	mfd_remove_devices(tscadc->dev);

	return 0;
}

static int __maybe_unused ti_tscadc_can_wakeup(struct device *dev, void *data)
{
	return device_may_wakeup(dev);
}

static int __maybe_unused tscadc_suspend(struct device *dev)
{
	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);

	regmap_write(tscadc->regmap, REG_SE, 0x00);
	if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) {
		u32 ctrl;

		regmap_read(tscadc->regmap, REG_CTRL, &ctrl);
		ctrl &= ~(CNTRLREG_POWERDOWN);
		ctrl |= CNTRLREG_TSCSSENB;
		regmap_write(tscadc->regmap, REG_CTRL, ctrl);
	}
	pm_runtime_put_sync(dev);

	return 0;
}

static int __maybe_unused tscadc_resume(struct device *dev)
{
	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
	u32 ctrl;

	pm_runtime_get_sync(dev);

	/* context restore */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	if (tscadc->tsc_cell != -1) {
		if (tscadc->tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc);
	}
	ctrl |= CNTRLREG_TSCSSENB;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);

	return 0;
}

static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);

static const struct of_device_id ti_tscadc_dt_ids[] = {
	{ .compatible = "ti,am3359-tscadc", },
	{ }
};
MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);

static struct platform_driver ti_tscadc_driver = {
	.driver = {
		.name   = "ti_am3359-tscadc",
		.pm	= &tscadc_pm_ops,
		.of_match_table = ti_tscadc_dt_ids,
	},
	.probe	= ti_tscadc_probe,
	.remove	= ti_tscadc_remove,

};

module_platform_driver(ti_tscadc_driver);

MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
3bda759f	1	// SPDX-License-Identifier: GPL-2.0-only
01636eb9 PR	2	/*
	3	* TI Touch Screen / ADC MFD driver
	4	*
4f4ed454	5	* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
01636eb9 PR	6	*/
	7
	8	#include <linux/module.h>
01636eb9 PR	9	#include <linux/slab.h>
	10	#include <linux/err.h>
	11	#include <linux/io.h>
	12	#include <linux/clk.h>
	13	#include <linux/regmap.h>
	14	#include <linux/mfd/core.h>
	15	#include <linux/pm_runtime.h>
a6543a1c PR	16	#include <linux/of.h>
a6543a1c PR	17	#include <linux/of_device.h>
7ca6740c	18	#include <linux/sched.h>
01636eb9 PR	19
	20	#include <linux/mfd/ti_am335x_tscadc.h>
	21
01636eb9 PR	22	static const struct regmap_config tscadc_regmap_config = {
	23	.name = "ti_tscadc",
	24	.reg_bits = 32,
	25	.reg_stride = 4,
	26	.val_bits = 32,
	27	};
	28
a318b7d0	29	void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
abeccee4	30	{
317b2099 SAS	31	unsigned long flags;
317b2099 SAS	32
a318b7d0 AD	33	spin_lock_irqsave(&tscadc->reg_lock, flags);
	34	tscadc->reg_se_cache \|= val;
	35	if (tscadc->adc_waiting)
	36	wake_up(&tscadc->reg_se_wait);
	37	else if (!tscadc->adc_in_use)
0d3a7cce	38	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
7ca6740c	39
a318b7d0	40	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
abeccee4	41	}
7e170c6e SAS	42	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
7e170c6e SAS	43
a318b7d0	44	static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
7ca6740c SAS	45	{
	46	DEFINE_WAIT(wait);
	47	u32 reg;
	48
0d3a7cce	49	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
7ca6740c	50	if (reg & SEQ_STATUS) {
a318b7d0 AD	51	tscadc->adc_waiting = true;
a318b7d0 AD	52	prepare_to_wait(&tscadc->reg_se_wait, &wait,
7ca6740c	53	TASK_UNINTERRUPTIBLE);
a318b7d0	54	spin_unlock_irq(&tscadc->reg_lock);
7ca6740c SAS	55
	56	schedule();
	57
a318b7d0 AD	58	spin_lock_irq(&tscadc->reg_lock);
a318b7d0 AD	59	finish_wait(&tscadc->reg_se_wait, &wait);
7ca6740c	60
b10848e6 V	61	/*
	62	* Sequencer should either be idle or
	63	* busy applying the charge step.
	64	*/
0d3a7cce	65	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
b10848e6	66	WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
a318b7d0	67	tscadc->adc_waiting = false;
7ca6740c	68	}
a318b7d0	69	tscadc->adc_in_use = true;
7ca6740c SAS	70	}
7ca6740c SAS	71
a318b7d0	72	void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
7ca6740c	73	{
a318b7d0 AD	74	spin_lock_irq(&tscadc->reg_lock);
a318b7d0 AD	75	am335x_tscadc_need_adc(tscadc);
7ca6740c	76
0d3a7cce	77	regmap_write(tscadc->regmap, REG_SE, val);
a318b7d0	78	spin_unlock_irq(&tscadc->reg_lock);
7ca6740c SAS	79	}
	80	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
	81
a318b7d0	82	void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
7e170c6e SAS	83	{
	84	unsigned long flags;
	85
a318b7d0 AD	86	spin_lock_irqsave(&tscadc->reg_lock, flags);
a318b7d0 AD	87	tscadc->adc_in_use = false;
0d3a7cce	88	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
a318b7d0	89	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
7e170c6e	90	}
7ca6740c	91	EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
abeccee4	92
a318b7d0	93	void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
abeccee4	94	{
317b2099 SAS	95	unsigned long flags;
317b2099 SAS	96
a318b7d0 AD	97	spin_lock_irqsave(&tscadc->reg_lock, flags);
a318b7d0 AD	98	tscadc->reg_se_cache &= ~val;
0d3a7cce	99	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
a318b7d0	100	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
abeccee4 PR	101	}
	102	EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
	103
a318b7d0	104	static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
01636eb9 PR	105	{
	106	unsigned int idleconfig;
	107
	108	idleconfig = STEPCONFIG_YNN \| STEPCONFIG_INM_ADCREFM \|
	109	STEPCONFIG_INP_ADCREFM \| STEPCONFIG_YPN;
	110
0d3a7cce	111	regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
01636eb9 PR	112	}
01636eb9 PR	113
612b95cd	114	static int ti_tscadc_probe(struct platform_device *pdev)
01636eb9	115	{
36e48f07 MR	116	struct ti_tscadc_dev *tscadc;
	117	struct resource *res;
	118	struct clk *clk;
	119	struct device_node *node;
	120	struct mfd_cell *cell;
	121	struct property *prop;
	122	const __be32 *cur;
	123	u32 val;
	124	int err, ctrl;
36e48f07 MR	125	int tsc_wires = 0, adc_channels = 0, total_channels;
36e48f07 MR	126	int readouts = 0;
01636eb9	127
61479479 MR	128	/* Allocate memory for device */
	129	tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
	130	if (!tscadc)
	131	return -ENOMEM;
	132
	133	tscadc->dev = &pdev->dev;
	134
9e5775f3 SAS	135	if (!pdev->dev.of_node) {
9e5775f3 SAS	136	dev_err(&pdev->dev, "Could not find valid DT data.\n");
01636eb9 PR	137	return -EINVAL;
	138	}
	139
9e5775f3 SAS	140	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
9e5775f3 SAS	141	of_property_read_u32(node, "ti,wires", &tsc_wires);
18926ede	142	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
29f95e8b	143	of_node_put(node);
a6543a1c	144
9e5775f3	145	node = of_get_child_by_name(pdev->dev.of_node, "adc");
18926ede SAS	146	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
	147	adc_channels++;
	148	if (val > 7) {
	149	dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
243e3cb9	150	val);
29f95e8b	151	of_node_put(node);
18926ede SAS	152	return -EINVAL;
	153	}
	154	}
29f95e8b MR	155
	156	of_node_put(node);
	157
5e53a69b	158	total_channels = tsc_wires + adc_channels;
5e53a69b PR	159	if (total_channels > 8) {
	160	dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
	161	return -EINVAL;
	162	}
243e3cb9	163
24d5c82f PA	164	if (total_channels == 0) {
	165	dev_err(&pdev->dev, "Need atleast one channel.\n");
	166	return -EINVAL;
	167	}
2b99bafa	168
18926ede SAS	169	if (readouts * 2 + 2 + adc_channels > 16) {
	170	dev_err(&pdev->dev, "Too many step configurations requested\n");
	171	return -EINVAL;
	172	}
	173
3c39c9c6	174	err = platform_get_irq(pdev, 0);
bc239d8d	175	if (err < 0)
287ee127	176	return err;
bc239d8d	177	else
3c39c9c6	178	tscadc->irq = err;
01636eb9	179
924ff918 JH	180	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	181	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	182	if (IS_ERR(tscadc->tscadc_base))
	183	return PTR_ERR(tscadc->tscadc_base);
01636eb9	184
de98a43e	185	tscadc->tscadc_phys_base = res->start;
0d3a7cce	186	tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
243e3cb9 MR	187	tscadc->tscadc_base,
243e3cb9 MR	188	&tscadc_regmap_config);
0d3a7cce	189	if (IS_ERR(tscadc->regmap)) {
01636eb9	190	dev_err(&pdev->dev, "regmap init failed\n");
287ee127	191	return PTR_ERR(tscadc->regmap);
01636eb9 PR	192	}
01636eb9 PR	193
abeccee4	194	spin_lock_init(&tscadc->reg_lock);
7ca6740c SAS	195	init_waitqueue_head(&tscadc->reg_se_wait);
7ca6740c SAS	196
01636eb9 PR	197	pm_runtime_enable(&pdev->dev);
	198	pm_runtime_get_sync(&pdev->dev);
	199
	200	/*
c4359f75 MR	201	* The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK.
	202	* ADCs produce a 12-bit sample every 15 ADC_CLK cycles.
	203	* am33xx ADCs expect to capture 200ksps.
	204	* We need the ADC clocks to run at 3MHz.
	205	* This frequency is valid since TSC_ADC_SS controller design
	206	* assumes the OCP clock is at least 6x faster than the ADC clock.
01636eb9	207	*/
235a96e9	208	clk = devm_clk_get(&pdev->dev, NULL);
01636eb9 PR	209	if (IS_ERR(clk)) {
	210	dev_err(&pdev->dev, "failed to get TSC fck\n");
	211	err = PTR_ERR(clk);
	212	goto err_disable_clk;
	213	}
efe3126a	214
8543537c	215	tscadc->clk_div = (clk_get_rate(clk) / ADC_CLK) - 1;
0d3a7cce	216	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
01636eb9 PR	217
01636eb9 PR	218	/* Set the control register bits */
f0933a60	219	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
0d3a7cce	220	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9 PR	221
01636eb9 PR	222	/* Set register bits for Idle Config Mode */
f0933a60 JL	223	if (tsc_wires > 0) {
	224	tscadc->tsc_wires = tsc_wires;
	225	if (tsc_wires == 5)
	226	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	227	else
	228	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
b5f8b763	229	tscadc_idle_config(tscadc);
f0933a60	230	}
01636eb9 PR	231
01636eb9 PR	232	/* Enable the TSC module enable bit */
01636eb9	233	ctrl \|= CNTRLREG_TSCSSENB;
0d3a7cce	234	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9	235
24d5c82f PA	236	tscadc->used_cells = 0;
	237	tscadc->tsc_cell = -1;
	238	tscadc->adc_cell = -1;
	239
2b99bafa	240	/* TSC Cell */
24d5c82f PA	241	if (tsc_wires > 0) {
	242	tscadc->tsc_cell = tscadc->used_cells;
	243	cell = &tscadc->cells[tscadc->used_cells++];
5f184e63	244	cell->name = "TI-am335x-tsc";
24d5c82f PA	245	cell->of_compatible = "ti,am3359-tsc";
	246	cell->platform_data = &tscadc;
	247	cell->pdata_size = sizeof(tscadc);
	248	}
2b99bafa	249
5e53a69b	250	/* ADC Cell */
24d5c82f PA	251	if (adc_channels > 0) {
	252	tscadc->adc_cell = tscadc->used_cells;
	253	cell = &tscadc->cells[tscadc->used_cells++];
9f99928f	254	cell->name = "TI-am335x-adc";
24d5c82f PA	255	cell->of_compatible = "ti,am3359-adc";
	256	cell->platform_data = &tscadc;
	257	cell->pdata_size = sizeof(tscadc);
	258	}
5e53a69b	259
b40ee006 V	260	err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
	261	tscadc->cells, tscadc->used_cells, NULL,
	262	0, NULL);
01636eb9 PR	263	if (err < 0)
	264	goto err_disable_clk;
	265
01636eb9	266	platform_set_drvdata(pdev, tscadc);
01636eb9 PR	267	return 0;
	268
	269	err_disable_clk:
	270	pm_runtime_put_sync(&pdev->dev);
	271	pm_runtime_disable(&pdev->dev);
287ee127	272
01636eb9 PR	273	return err;
	274	}
	275
612b95cd	276	static int ti_tscadc_remove(struct platform_device *pdev)
01636eb9	277	{
36e48f07	278	struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
01636eb9	279
0d3a7cce	280	regmap_write(tscadc->regmap, REG_SE, 0x00);
01636eb9 PR	281
	282	pm_runtime_put_sync(&pdev->dev);
	283	pm_runtime_disable(&pdev->dev);
	284
	285	mfd_remove_devices(tscadc->dev);
	286
	287	return 0;
	288	}
	289
c974ac77 V	290	static int __maybe_unused ti_tscadc_can_wakeup(struct device dev, void data)
	291	{
	292	return device_may_wakeup(dev);
	293	}
	294
dae936a0	295	static int __maybe_unused tscadc_suspend(struct device *dev)
01636eb9	296	{
36e48f07	297	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
01636eb9	298
0d3a7cce	299	regmap_write(tscadc->regmap, REG_SE, 0x00);
c974ac77 V	300	if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) {
	301	u32 ctrl;
	302
	303	regmap_read(tscadc->regmap, REG_CTRL, &ctrl);
	304	ctrl &= ~(CNTRLREG_POWERDOWN);
	305	ctrl \|= CNTRLREG_TSCSSENB;
	306	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
	307	}
01636eb9 PR	308	pm_runtime_put_sync(dev);
	309
	310	return 0;
	311	}
	312
dae936a0	313	static int __maybe_unused tscadc_resume(struct device *dev)
01636eb9	314	{
36e48f07	315	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
f0933a60	316	u32 ctrl;
01636eb9 PR	317
	318	pm_runtime_get_sync(dev);
	319
	320	/* context restore */
b5f8b763	321	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
0d3a7cce	322	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
b5f8b763	323
a318b7d0 AD	324	if (tscadc->tsc_cell != -1) {
a318b7d0 AD	325	if (tscadc->tsc_wires == 5)
f0933a60 JL	326	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	327	else
	328	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
a318b7d0	329	tscadc_idle_config(tscadc);
f0933a60 JL	330	}
f0933a60 JL	331	ctrl \|= CNTRLREG_TSCSSENB;
0d3a7cce	332	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9	333
0d3a7cce	334	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
e90f8754	335
01636eb9 PR	336	return 0;
	337	}
	338
dae936a0	339	static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);
01636eb9	340
a6543a1c PR	341	static const struct of_device_id ti_tscadc_dt_ids[] = {
	342	{ .compatible = "ti,am3359-tscadc", },
	343	{ }
	344	};
	345	MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
	346
01636eb9 PR	347	static struct platform_driver ti_tscadc_driver = {
01636eb9 PR	348	.driver = {
a6543a1c	349	.name = "ti_am3359-tscadc",
dae936a0	350	.pm = &tscadc_pm_ops,
131221bc	351	.of_match_table = ti_tscadc_dt_ids,
01636eb9 PR	352	},
01636eb9 PR	353	.probe = ti_tscadc_probe,
612b95cd	354	.remove = ti_tscadc_remove,
01636eb9 PR	355
	356	};
	357
	358	module_platform_driver(ti_tscadc_driver);
	359
	360	MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
	361	MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
	362	MODULE_LICENSE("GPL");