[linux-2.6-block.git] / drivers / mfd / ti_am335x_tscadc.c

/*
 * TI Touch Screen / ADC MFD driver
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>

#include <linux/mfd/ti_am335x_tscadc.h>

static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
{
	unsigned int val;

	regmap_read(tsadc->regmap_tscadc, reg, &val);
	return val;
}

static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
					unsigned int val)
{
	regmap_write(tsadc->regmap_tscadc, reg, val);
}

static const struct regmap_config tscadc_regmap_config = {
	.name = "ti_tscadc",
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
};

static void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc)
{
	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
}

void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tsadc->reg_lock, flags);
	tsadc->reg_se_cache |= val;
	am335x_tsc_se_update(tsadc);
	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);

void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tsadc->reg_lock, flags);
	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache | val);
	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);

void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tsadc->reg_lock, flags);
	tsadc->reg_se_cache &= ~val;
	am335x_tsc_se_update(tsadc);
	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);

static void tscadc_idle_config(struct ti_tscadc_dev *config)
{
	unsigned int idleconfig;

	idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
			STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;

	tscadc_writel(config, REG_IDLECONFIG, idleconfig);
}

static	int ti_tscadc_probe(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc;
	struct resource		*res;
	struct clk		*clk;
	struct device_node	*node = pdev->dev.of_node;
	struct mfd_cell		*cell;
	struct property         *prop;
	const __be32            *cur;
	u32			val;
	int			err, ctrl;
	int			clock_rate;
	int			tsc_wires = 0, adc_channels = 0, total_channels;
	int			readouts = 0;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "Could not find valid DT data.\n");
		return -EINVAL;
	}

	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
	of_property_read_u32(node, "ti,wires", &tsc_wires);
	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);

	node = of_get_child_by_name(pdev->dev.of_node, "adc");
	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
		adc_channels++;
		if (val > 7) {
			dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
					val);
			return -EINVAL;
		}
	}
	total_channels = tsc_wires + adc_channels;
	if (total_channels > 8) {
		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
		return -EINVAL;
	}
	if (total_channels == 0) {
		dev_err(&pdev->dev, "Need atleast one channel.\n");
		return -EINVAL;
	}

	if (readouts * 2 + 2 + adc_channels > 16) {
		dev_err(&pdev->dev, "Too many step configurations requested\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "no memory resource defined.\n");
		return -EINVAL;
	}

	/* Allocate memory for device */
	tscadc = devm_kzalloc(&pdev->dev,
			sizeof(struct ti_tscadc_dev), GFP_KERNEL);
	if (!tscadc) {
		dev_err(&pdev->dev, "failed to allocate memory.\n");
		return -ENOMEM;
	}
	tscadc->dev = &pdev->dev;

	err = platform_get_irq(pdev, 0);
	if (err < 0) {
		dev_err(&pdev->dev, "no irq ID is specified.\n");
		goto ret;
	} else
		tscadc->irq = err;

	res = devm_request_mem_region(&pdev->dev,
			res->start, resource_size(res), pdev->name);
	if (!res) {
		dev_err(&pdev->dev, "failed to reserve registers.\n");
		return -EBUSY;
	}

	tscadc->tscadc_base = devm_ioremap(&pdev->dev,
			res->start, resource_size(res));
	if (!tscadc->tscadc_base) {
		dev_err(&pdev->dev, "failed to map registers.\n");
		return -ENOMEM;
	}

	tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
			tscadc->tscadc_base, &tscadc_regmap_config);
	if (IS_ERR(tscadc->regmap_tscadc)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		err = PTR_ERR(tscadc->regmap_tscadc);
		goto ret;
	}

	spin_lock_init(&tscadc->reg_lock);
	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	/*
	 * The TSC_ADC_Subsystem has 2 clock domains
	 * OCP_CLK and ADC_CLK.
	 * The ADC clock is expected to run at target of 3MHz,
	 * and expected to capture 12-bit data at a rate of 200 KSPS.
	 * The TSC_ADC_SS controller design assumes the OCP clock is
	 * at least 6x faster than the ADC clock.
	 */
	clk = clk_get(&pdev->dev, "adc_tsc_fck");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get TSC fck\n");
		err = PTR_ERR(clk);
		goto err_disable_clk;
	}
	clock_rate = clk_get_rate(clk);
	clk_put(clk);
	tscadc->clk_div = clock_rate / ADC_CLK;

	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
	tscadc->clk_div--;
	tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);

	/* Set the control register bits */
	ctrl = CNTRLREG_STEPCONFIGWRT |
			CNTRLREG_STEPID;
	if (tsc_wires > 0)
		ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
	tscadc_writel(tscadc, REG_CTRL, ctrl);

	/* Set register bits for Idle Config Mode */
	if (tsc_wires > 0)
		tscadc_idle_config(tscadc);

	/* Enable the TSC module enable bit */
	ctrl = tscadc_readl(tscadc, REG_CTRL);
	ctrl |= CNTRLREG_TSCSSENB;
	tscadc_writel(tscadc, REG_CTRL, ctrl);

	tscadc->used_cells = 0;
	tscadc->tsc_cell = -1;
	tscadc->adc_cell = -1;

	/* TSC Cell */
	if (tsc_wires > 0) {
		tscadc->tsc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-tsc";
		cell->of_compatible = "ti,am3359-tsc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	/* ADC Cell */
	if (adc_channels > 0) {
		tscadc->adc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-adc";
		cell->of_compatible = "ti,am3359-adc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
			tscadc->used_cells, NULL, 0, NULL);
	if (err < 0)
		goto err_disable_clk;

	device_init_wakeup(&pdev->dev, true);
	platform_set_drvdata(pdev, tscadc);
	return 0;

err_disable_clk:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
ret:
	return err;
}

static int ti_tscadc_remove(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc = platform_get_drvdata(pdev);

	tscadc_writel(tscadc, REG_SE, 0x00);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	mfd_remove_devices(tscadc->dev);

	return 0;
}

#ifdef CONFIG_PM
static int tscadc_suspend(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc_dev = dev_get_drvdata(dev);

	tscadc_writel(tscadc_dev, REG_SE, 0x00);
	pm_runtime_put_sync(dev);

	return 0;
}

static int tscadc_resume(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc_dev = dev_get_drvdata(dev);
	unsigned int restore, ctrl;

	pm_runtime_get_sync(dev);

	/* context restore */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	if (tscadc_dev->tsc_cell != -1)
		ctrl |= CNTRLREG_TSCENB | CNTRLREG_4WIRE;
	tscadc_writel(tscadc_dev, REG_CTRL, ctrl);

	if (tscadc_dev->tsc_cell != -1)
		tscadc_idle_config(tscadc_dev);
	restore = tscadc_readl(tscadc_dev, REG_CTRL);
	tscadc_writel(tscadc_dev, REG_CTRL,
			(restore | CNTRLREG_TSCSSENB));

	tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);

	return 0;
}

static const struct dev_pm_ops tscadc_pm_ops = {
	.suspend = tscadc_suspend,
	.resume = tscadc_resume,
};
#define TSCADC_PM_OPS (&tscadc_pm_ops)
#else
#define TSCADC_PM_OPS NULL
#endif

static const struct of_device_id ti_tscadc_dt_ids[] = {
	{ .compatible = "ti,am3359-tscadc", },
	{ }
};
MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);

static struct platform_driver ti_tscadc_driver = {
	.driver = {
		.name   = "ti_am3359-tscadc",
		.owner	= THIS_MODULE,
		.pm	= TSCADC_PM_OPS,
		.of_match_table = ti_tscadc_dt_ids,
	},
	.probe	= ti_tscadc_probe,
	.remove	= ti_tscadc_remove,

};

module_platform_driver(ti_tscadc_driver);

MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
01636eb9 PR	1	/*
	2	* TI Touch Screen / ADC MFD driver
	3	*
	4	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/init.h>
	18	#include <linux/slab.h>
	19	#include <linux/err.h>
	20	#include <linux/io.h>
	21	#include <linux/clk.h>
	22	#include <linux/regmap.h>
	23	#include <linux/mfd/core.h>
	24	#include <linux/pm_runtime.h>
a6543a1c PR	25	#include <linux/of.h>
a6543a1c PR	26	#include <linux/of_device.h>
01636eb9 PR	27
	28	#include <linux/mfd/ti_am335x_tscadc.h>
	29
	30	static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
	31	{
	32	unsigned int val;
	33
	34	regmap_read(tsadc->regmap_tscadc, reg, &val);
	35	return val;
	36	}
	37
	38	static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
	39	unsigned int val)
	40	{
	41	regmap_write(tsadc->regmap_tscadc, reg, val);
	42	}
	43
	44	static const struct regmap_config tscadc_regmap_config = {
	45	.name = "ti_tscadc",
	46	.reg_bits = 32,
	47	.reg_stride = 4,
	48	.val_bits = 32,
	49	};
	50
3466bd22	51	static void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc)
abeccee4 PR	52	{
	53	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
	54	}
abeccee4	55
7e170c6e	56	void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
abeccee4	57	{
317b2099 SAS	58	unsigned long flags;
	59
	60	spin_lock_irqsave(&tsadc->reg_lock, flags);
abeccee4	61	tsadc->reg_se_cache \|= val;
abeccee4	62	am335x_tsc_se_update(tsadc);
317b2099	63	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
abeccee4	64	}
7e170c6e SAS	65	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
	66
	67	void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
	68	{
	69	unsigned long flags;
	70
	71	spin_lock_irqsave(&tsadc->reg_lock, flags);
	72	tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache \| val);
	73	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
	74	}
	75	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
abeccee4 PR	76
	77	void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
	78	{
317b2099 SAS	79	unsigned long flags;
	80
	81	spin_lock_irqsave(&tsadc->reg_lock, flags);
abeccee4	82	tsadc->reg_se_cache &= ~val;
abeccee4	83	am335x_tsc_se_update(tsadc);
317b2099	84	spin_unlock_irqrestore(&tsadc->reg_lock, flags);
abeccee4 PR	85	}
	86	EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
	87
01636eb9 PR	88	static void tscadc_idle_config(struct ti_tscadc_dev *config)
	89	{
	90	unsigned int idleconfig;
	91
	92	idleconfig = STEPCONFIG_YNN \| STEPCONFIG_INM_ADCREFM \|
	93	STEPCONFIG_INP_ADCREFM \| STEPCONFIG_YPN;
	94
	95	tscadc_writel(config, REG_IDLECONFIG, idleconfig);
	96	}
	97
612b95cd	98	static int ti_tscadc_probe(struct platform_device *pdev)
01636eb9 PR	99	{
	100	struct ti_tscadc_dev *tscadc;
	101	struct resource *res;
	102	struct clk *clk;
a6543a1c	103	struct device_node *node = pdev->dev.of_node;
2b99bafa	104	struct mfd_cell *cell;
18926ede SAS	105	struct property *prop;
	106	const __be32 *cur;
	107	u32 val;
01636eb9	108	int err, ctrl;
e90f8754	109	int clock_rate;
a6543a1c	110	int tsc_wires = 0, adc_channels = 0, total_channels;
18926ede	111	int readouts = 0;
01636eb9	112
9e5775f3 SAS	113	if (!pdev->dev.of_node) {
9e5775f3 SAS	114	dev_err(&pdev->dev, "Could not find valid DT data.\n");
01636eb9 PR	115	return -EINVAL;
	116	}
	117
9e5775f3 SAS	118	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
9e5775f3 SAS	119	of_property_read_u32(node, "ti,wires", &tsc_wires);
18926ede	120	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
a6543a1c	121
9e5775f3	122	node = of_get_child_by_name(pdev->dev.of_node, "adc");
18926ede SAS	123	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
	124	adc_channels++;
	125	if (val > 7) {
	126	dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
	127	val);
	128	return -EINVAL;
	129	}
	130	}
5e53a69b	131	total_channels = tsc_wires + adc_channels;
5e53a69b PR	132	if (total_channels > 8) {
	133	dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
	134	return -EINVAL;
	135	}
24d5c82f PA	136	if (total_channels == 0) {
	137	dev_err(&pdev->dev, "Need atleast one channel.\n");
	138	return -EINVAL;
	139	}
2b99bafa	140
18926ede SAS	141	if (readouts * 2 + 2 + adc_channels > 16) {
	142	dev_err(&pdev->dev, "Too many step configurations requested\n");
	143	return -EINVAL;
	144	}
	145
01636eb9 PR	146	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	147	if (!res) {
	148	dev_err(&pdev->dev, "no memory resource defined.\n");
	149	return -EINVAL;
	150	}
	151
01636eb9 PR	152	/* Allocate memory for device */
	153	tscadc = devm_kzalloc(&pdev->dev,
	154	sizeof(struct ti_tscadc_dev), GFP_KERNEL);
	155	if (!tscadc) {
	156	dev_err(&pdev->dev, "failed to allocate memory.\n");
	157	return -ENOMEM;
	158	}
	159	tscadc->dev = &pdev->dev;
3c39c9c6 PR	160
	161	err = platform_get_irq(pdev, 0);
	162	if (err < 0) {
	163	dev_err(&pdev->dev, "no irq ID is specified.\n");
	164	goto ret;
	165	} else
	166	tscadc->irq = err;
01636eb9 PR	167
	168	res = devm_request_mem_region(&pdev->dev,
	169	res->start, resource_size(res), pdev->name);
	170	if (!res) {
	171	dev_err(&pdev->dev, "failed to reserve registers.\n");
3c39c9c6	172	return -EBUSY;
01636eb9 PR	173	}
	174
	175	tscadc->tscadc_base = devm_ioremap(&pdev->dev,
	176	res->start, resource_size(res));
	177	if (!tscadc->tscadc_base) {
	178	dev_err(&pdev->dev, "failed to map registers.\n");
3c39c9c6	179	return -ENOMEM;
01636eb9 PR	180	}
	181
	182	tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
	183	tscadc->tscadc_base, &tscadc_regmap_config);
	184	if (IS_ERR(tscadc->regmap_tscadc)) {
	185	dev_err(&pdev->dev, "regmap init failed\n");
	186	err = PTR_ERR(tscadc->regmap_tscadc);
3c39c9c6	187	goto ret;
01636eb9 PR	188	}
01636eb9 PR	189
abeccee4	190	spin_lock_init(&tscadc->reg_lock);
01636eb9 PR	191	pm_runtime_enable(&pdev->dev);
	192	pm_runtime_get_sync(&pdev->dev);
	193
	194	/*
	195	* The TSC_ADC_Subsystem has 2 clock domains
	196	* OCP_CLK and ADC_CLK.
	197	* The ADC clock is expected to run at target of 3MHz,
	198	* and expected to capture 12-bit data at a rate of 200 KSPS.
	199	* The TSC_ADC_SS controller design assumes the OCP clock is
	200	* at least 6x faster than the ADC clock.
	201	*/
	202	clk = clk_get(&pdev->dev, "adc_tsc_fck");
	203	if (IS_ERR(clk)) {
	204	dev_err(&pdev->dev, "failed to get TSC fck\n");
	205	err = PTR_ERR(clk);
	206	goto err_disable_clk;
	207	}
	208	clock_rate = clk_get_rate(clk);
	209	clk_put(clk);
e90f8754	210	tscadc->clk_div = clock_rate / ADC_CLK;
efe3126a	211
01636eb9	212	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
e90f8754 MK	213	tscadc->clk_div--;
e90f8754 MK	214	tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);
01636eb9 PR	215
	216	/* Set the control register bits */
	217	ctrl = CNTRLREG_STEPCONFIGWRT \|
b5f8b763 PR	218	CNTRLREG_STEPID;
	219	if (tsc_wires > 0)
	220	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
01636eb9 PR	221	tscadc_writel(tscadc, REG_CTRL, ctrl);
	222
	223	/* Set register bits for Idle Config Mode */
b5f8b763 PR	224	if (tsc_wires > 0)
b5f8b763 PR	225	tscadc_idle_config(tscadc);
01636eb9 PR	226
	227	/* Enable the TSC module enable bit */
	228	ctrl = tscadc_readl(tscadc, REG_CTRL);
	229	ctrl \|= CNTRLREG_TSCSSENB;
	230	tscadc_writel(tscadc, REG_CTRL, ctrl);
	231
24d5c82f PA	232	tscadc->used_cells = 0;
	233	tscadc->tsc_cell = -1;
	234	tscadc->adc_cell = -1;
	235
2b99bafa	236	/* TSC Cell */
24d5c82f PA	237	if (tsc_wires > 0) {
	238	tscadc->tsc_cell = tscadc->used_cells;
	239	cell = &tscadc->cells[tscadc->used_cells++];
5f184e63	240	cell->name = "TI-am335x-tsc";
24d5c82f PA	241	cell->of_compatible = "ti,am3359-tsc";
	242	cell->platform_data = &tscadc;
	243	cell->pdata_size = sizeof(tscadc);
	244	}
2b99bafa	245
5e53a69b	246	/* ADC Cell */
24d5c82f PA	247	if (adc_channels > 0) {
	248	tscadc->adc_cell = tscadc->used_cells;
	249	cell = &tscadc->cells[tscadc->used_cells++];
9f99928f	250	cell->name = "TI-am335x-adc";
24d5c82f PA	251	cell->of_compatible = "ti,am3359-adc";
	252	cell->platform_data = &tscadc;
	253	cell->pdata_size = sizeof(tscadc);
	254	}
5e53a69b	255
01636eb9	256	err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
24d5c82f	257	tscadc->used_cells, NULL, 0, NULL);
01636eb9 PR	258	if (err < 0)
	259	goto err_disable_clk;
	260
	261	device_init_wakeup(&pdev->dev, true);
	262	platform_set_drvdata(pdev, tscadc);
01636eb9 PR	263	return 0;
	264
	265	err_disable_clk:
	266	pm_runtime_put_sync(&pdev->dev);
	267	pm_runtime_disable(&pdev->dev);
3c39c9c6	268	ret:
01636eb9 PR	269	return err;
	270	}
	271
612b95cd	272	static int ti_tscadc_remove(struct platform_device *pdev)
01636eb9 PR	273	{
	274	struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
	275
	276	tscadc_writel(tscadc, REG_SE, 0x00);
	277
	278	pm_runtime_put_sync(&pdev->dev);
	279	pm_runtime_disable(&pdev->dev);
	280
	281	mfd_remove_devices(tscadc->dev);
	282
	283	return 0;
	284	}
	285
	286	#ifdef CONFIG_PM
	287	static int tscadc_suspend(struct device *dev)
	288	{
	289	struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
	290
	291	tscadc_writel(tscadc_dev, REG_SE, 0x00);
	292	pm_runtime_put_sync(dev);
	293
	294	return 0;
	295	}
	296
	297	static int tscadc_resume(struct device *dev)
	298	{
	299	struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
	300	unsigned int restore, ctrl;
	301
	302	pm_runtime_get_sync(dev);
	303
	304	/* context restore */
b5f8b763 PR	305	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
	306	if (tscadc_dev->tsc_cell != -1)
	307	ctrl \|= CNTRLREG_TSCENB \| CNTRLREG_4WIRE;
01636eb9	308	tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
b5f8b763 PR	309
	310	if (tscadc_dev->tsc_cell != -1)
	311	tscadc_idle_config(tscadc_dev);
01636eb9 PR	312	restore = tscadc_readl(tscadc_dev, REG_CTRL);
	313	tscadc_writel(tscadc_dev, REG_CTRL,
	314	(restore \| CNTRLREG_TSCSSENB));
	315
e90f8754 MK	316	tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);
e90f8754 MK	317
01636eb9 PR	318	return 0;
	319	}
	320
	321	static const struct dev_pm_ops tscadc_pm_ops = {
	322	.suspend = tscadc_suspend,
	323	.resume = tscadc_resume,
	324	};
	325	#define TSCADC_PM_OPS (&tscadc_pm_ops)
	326	#else
	327	#define TSCADC_PM_OPS NULL
	328	#endif
	329
a6543a1c PR	330	static const struct of_device_id ti_tscadc_dt_ids[] = {
	331	{ .compatible = "ti,am3359-tscadc", },
	332	{ }
	333	};
	334	MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
	335
01636eb9 PR	336	static struct platform_driver ti_tscadc_driver = {
01636eb9 PR	337	.driver = {
a6543a1c	338	.name = "ti_am3359-tscadc",
01636eb9 PR	339	.owner = THIS_MODULE,
01636eb9 PR	340	.pm = TSCADC_PM_OPS,
131221bc	341	.of_match_table = ti_tscadc_dt_ids,
01636eb9 PR	342	},
01636eb9 PR	343	.probe = ti_tscadc_probe,
612b95cd	344	.remove = ti_tscadc_remove,
01636eb9 PR	345
	346	};
	347
	348	module_platform_driver(ti_tscadc_driver);
	349
	350	MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
	351	MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
	352	MODULE_LICENSE("GPL");