Commit | Line | Data |
---|---|---|
3bda759f | 1 | // SPDX-License-Identifier: GPL-2.0-only |
01636eb9 PR |
2 | /* |
3 | * TI Touch Screen / ADC MFD driver | |
4 | * | |
4f4ed454 | 5 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
01636eb9 PR |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
01636eb9 PR |
9 | #include <linux/slab.h> |
10 | #include <linux/err.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/regmap.h> | |
14 | #include <linux/mfd/core.h> | |
15 | #include <linux/pm_runtime.h> | |
a6543a1c PR |
16 | #include <linux/of.h> |
17 | #include <linux/of_device.h> | |
7ca6740c | 18 | #include <linux/sched.h> |
01636eb9 PR |
19 | |
20 | #include <linux/mfd/ti_am335x_tscadc.h> | |
21 | ||
01636eb9 PR |
22 | static const struct regmap_config tscadc_regmap_config = { |
23 | .name = "ti_tscadc", | |
24 | .reg_bits = 32, | |
25 | .reg_stride = 4, | |
26 | .val_bits = 32, | |
27 | }; | |
28 | ||
a318b7d0 | 29 | void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val) |
abeccee4 | 30 | { |
317b2099 SAS |
31 | unsigned long flags; |
32 | ||
a318b7d0 AD |
33 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
34 | tscadc->reg_se_cache |= val; | |
35 | if (tscadc->adc_waiting) | |
36 | wake_up(&tscadc->reg_se_wait); | |
37 | else if (!tscadc->adc_in_use) | |
0d3a7cce | 38 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
7ca6740c | 39 | |
a318b7d0 | 40 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
abeccee4 | 41 | } |
7e170c6e SAS |
42 | EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache); |
43 | ||
a318b7d0 | 44 | static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc) |
7ca6740c SAS |
45 | { |
46 | DEFINE_WAIT(wait); | |
47 | u32 reg; | |
48 | ||
0d3a7cce | 49 | regmap_read(tscadc->regmap, REG_ADCFSM, ®); |
7ca6740c | 50 | if (reg & SEQ_STATUS) { |
a318b7d0 AD |
51 | tscadc->adc_waiting = true; |
52 | prepare_to_wait(&tscadc->reg_se_wait, &wait, | |
7ca6740c | 53 | TASK_UNINTERRUPTIBLE); |
a318b7d0 | 54 | spin_unlock_irq(&tscadc->reg_lock); |
7ca6740c SAS |
55 | |
56 | schedule(); | |
57 | ||
a318b7d0 AD |
58 | spin_lock_irq(&tscadc->reg_lock); |
59 | finish_wait(&tscadc->reg_se_wait, &wait); | |
7ca6740c | 60 | |
b10848e6 V |
61 | /* |
62 | * Sequencer should either be idle or | |
63 | * busy applying the charge step. | |
64 | */ | |
0d3a7cce | 65 | regmap_read(tscadc->regmap, REG_ADCFSM, ®); |
b10848e6 | 66 | WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP)); |
a318b7d0 | 67 | tscadc->adc_waiting = false; |
7ca6740c | 68 | } |
a318b7d0 | 69 | tscadc->adc_in_use = true; |
7ca6740c SAS |
70 | } |
71 | ||
a318b7d0 | 72 | void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val) |
7ca6740c | 73 | { |
a318b7d0 AD |
74 | spin_lock_irq(&tscadc->reg_lock); |
75 | am335x_tscadc_need_adc(tscadc); | |
7ca6740c | 76 | |
0d3a7cce | 77 | regmap_write(tscadc->regmap, REG_SE, val); |
a318b7d0 | 78 | spin_unlock_irq(&tscadc->reg_lock); |
7ca6740c SAS |
79 | } |
80 | EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once); | |
81 | ||
a318b7d0 | 82 | void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc) |
7e170c6e SAS |
83 | { |
84 | unsigned long flags; | |
85 | ||
a318b7d0 AD |
86 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
87 | tscadc->adc_in_use = false; | |
0d3a7cce | 88 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
a318b7d0 | 89 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
7e170c6e | 90 | } |
7ca6740c | 91 | EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done); |
abeccee4 | 92 | |
a318b7d0 | 93 | void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val) |
abeccee4 | 94 | { |
317b2099 SAS |
95 | unsigned long flags; |
96 | ||
a318b7d0 AD |
97 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
98 | tscadc->reg_se_cache &= ~val; | |
0d3a7cce | 99 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
a318b7d0 | 100 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
abeccee4 PR |
101 | } |
102 | EXPORT_SYMBOL_GPL(am335x_tsc_se_clr); | |
103 | ||
a318b7d0 | 104 | static void tscadc_idle_config(struct ti_tscadc_dev *tscadc) |
01636eb9 PR |
105 | { |
106 | unsigned int idleconfig; | |
107 | ||
108 | idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM | | |
109 | STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN; | |
110 | ||
0d3a7cce | 111 | regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig); |
01636eb9 PR |
112 | } |
113 | ||
612b95cd | 114 | static int ti_tscadc_probe(struct platform_device *pdev) |
01636eb9 PR |
115 | { |
116 | struct ti_tscadc_dev *tscadc; | |
117 | struct resource *res; | |
118 | struct clk *clk; | |
e368866e | 119 | struct device_node *node; |
2b99bafa | 120 | struct mfd_cell *cell; |
18926ede SAS |
121 | struct property *prop; |
122 | const __be32 *cur; | |
123 | u32 val; | |
01636eb9 | 124 | int err, ctrl; |
e90f8754 | 125 | int clock_rate; |
a6543a1c | 126 | int tsc_wires = 0, adc_channels = 0, total_channels; |
18926ede | 127 | int readouts = 0; |
01636eb9 | 128 | |
9e5775f3 SAS |
129 | if (!pdev->dev.of_node) { |
130 | dev_err(&pdev->dev, "Could not find valid DT data.\n"); | |
01636eb9 PR |
131 | return -EINVAL; |
132 | } | |
133 | ||
9e5775f3 SAS |
134 | node = of_get_child_by_name(pdev->dev.of_node, "tsc"); |
135 | of_property_read_u32(node, "ti,wires", &tsc_wires); | |
18926ede | 136 | of_property_read_u32(node, "ti,coordiante-readouts", &readouts); |
29f95e8b | 137 | of_node_put(node); |
a6543a1c | 138 | |
9e5775f3 | 139 | node = of_get_child_by_name(pdev->dev.of_node, "adc"); |
18926ede SAS |
140 | of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { |
141 | adc_channels++; | |
142 | if (val > 7) { | |
143 | dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n", | |
243e3cb9 | 144 | val); |
29f95e8b | 145 | of_node_put(node); |
18926ede SAS |
146 | return -EINVAL; |
147 | } | |
148 | } | |
29f95e8b MR |
149 | |
150 | of_node_put(node); | |
151 | ||
5e53a69b | 152 | total_channels = tsc_wires + adc_channels; |
5e53a69b PR |
153 | if (total_channels > 8) { |
154 | dev_err(&pdev->dev, "Number of i/p channels more than 8\n"); | |
155 | return -EINVAL; | |
156 | } | |
243e3cb9 | 157 | |
24d5c82f PA |
158 | if (total_channels == 0) { |
159 | dev_err(&pdev->dev, "Need atleast one channel.\n"); | |
160 | return -EINVAL; | |
161 | } | |
2b99bafa | 162 | |
18926ede SAS |
163 | if (readouts * 2 + 2 + adc_channels > 16) { |
164 | dev_err(&pdev->dev, "Too many step configurations requested\n"); | |
165 | return -EINVAL; | |
166 | } | |
167 | ||
01636eb9 | 168 | /* Allocate memory for device */ |
dea1c703 | 169 | tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL); |
a2e87fee | 170 | if (!tscadc) |
01636eb9 | 171 | return -ENOMEM; |
a2e87fee | 172 | |
01636eb9 | 173 | tscadc->dev = &pdev->dev; |
3c39c9c6 PR |
174 | |
175 | err = platform_get_irq(pdev, 0); | |
bc239d8d | 176 | if (err < 0) |
3c39c9c6 | 177 | goto ret; |
bc239d8d | 178 | else |
3c39c9c6 | 179 | tscadc->irq = err; |
01636eb9 | 180 | |
924ff918 JH |
181 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
182 | tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res); | |
183 | if (IS_ERR(tscadc->tscadc_base)) | |
184 | return PTR_ERR(tscadc->tscadc_base); | |
01636eb9 | 185 | |
de98a43e | 186 | tscadc->tscadc_phys_base = res->start; |
0d3a7cce | 187 | tscadc->regmap = devm_regmap_init_mmio(&pdev->dev, |
243e3cb9 MR |
188 | tscadc->tscadc_base, |
189 | &tscadc_regmap_config); | |
0d3a7cce | 190 | if (IS_ERR(tscadc->regmap)) { |
01636eb9 | 191 | dev_err(&pdev->dev, "regmap init failed\n"); |
0d3a7cce | 192 | err = PTR_ERR(tscadc->regmap); |
3c39c9c6 | 193 | goto ret; |
01636eb9 PR |
194 | } |
195 | ||
abeccee4 | 196 | spin_lock_init(&tscadc->reg_lock); |
7ca6740c SAS |
197 | init_waitqueue_head(&tscadc->reg_se_wait); |
198 | ||
01636eb9 PR |
199 | pm_runtime_enable(&pdev->dev); |
200 | pm_runtime_get_sync(&pdev->dev); | |
201 | ||
202 | /* | |
203 | * The TSC_ADC_Subsystem has 2 clock domains | |
204 | * OCP_CLK and ADC_CLK. | |
205 | * The ADC clock is expected to run at target of 3MHz, | |
206 | * and expected to capture 12-bit data at a rate of 200 KSPS. | |
207 | * The TSC_ADC_SS controller design assumes the OCP clock is | |
208 | * at least 6x faster than the ADC clock. | |
209 | */ | |
c2b1509c | 210 | clk = devm_clk_get(&pdev->dev, "adc_tsc_fck"); |
01636eb9 PR |
211 | if (IS_ERR(clk)) { |
212 | dev_err(&pdev->dev, "failed to get TSC fck\n"); | |
213 | err = PTR_ERR(clk); | |
214 | goto err_disable_clk; | |
215 | } | |
216 | clock_rate = clk_get_rate(clk); | |
e90f8754 | 217 | tscadc->clk_div = clock_rate / ADC_CLK; |
efe3126a | 218 | |
01636eb9 | 219 | /* TSCADC_CLKDIV needs to be configured to the value minus 1 */ |
e90f8754 | 220 | tscadc->clk_div--; |
0d3a7cce | 221 | regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div); |
01636eb9 PR |
222 | |
223 | /* Set the control register bits */ | |
f0933a60 | 224 | ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID; |
0d3a7cce | 225 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
01636eb9 PR |
226 | |
227 | /* Set register bits for Idle Config Mode */ | |
f0933a60 JL |
228 | if (tsc_wires > 0) { |
229 | tscadc->tsc_wires = tsc_wires; | |
230 | if (tsc_wires == 5) | |
231 | ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB; | |
232 | else | |
233 | ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB; | |
b5f8b763 | 234 | tscadc_idle_config(tscadc); |
f0933a60 | 235 | } |
01636eb9 PR |
236 | |
237 | /* Enable the TSC module enable bit */ | |
01636eb9 | 238 | ctrl |= CNTRLREG_TSCSSENB; |
0d3a7cce | 239 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
01636eb9 | 240 | |
24d5c82f PA |
241 | tscadc->used_cells = 0; |
242 | tscadc->tsc_cell = -1; | |
243 | tscadc->adc_cell = -1; | |
244 | ||
2b99bafa | 245 | /* TSC Cell */ |
24d5c82f PA |
246 | if (tsc_wires > 0) { |
247 | tscadc->tsc_cell = tscadc->used_cells; | |
248 | cell = &tscadc->cells[tscadc->used_cells++]; | |
5f184e63 | 249 | cell->name = "TI-am335x-tsc"; |
24d5c82f PA |
250 | cell->of_compatible = "ti,am3359-tsc"; |
251 | cell->platform_data = &tscadc; | |
252 | cell->pdata_size = sizeof(tscadc); | |
253 | } | |
2b99bafa | 254 | |
5e53a69b | 255 | /* ADC Cell */ |
24d5c82f PA |
256 | if (adc_channels > 0) { |
257 | tscadc->adc_cell = tscadc->used_cells; | |
258 | cell = &tscadc->cells[tscadc->used_cells++]; | |
9f99928f | 259 | cell->name = "TI-am335x-adc"; |
24d5c82f PA |
260 | cell->of_compatible = "ti,am3359-adc"; |
261 | cell->platform_data = &tscadc; | |
262 | cell->pdata_size = sizeof(tscadc); | |
263 | } | |
5e53a69b | 264 | |
b40ee006 V |
265 | err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, |
266 | tscadc->cells, tscadc->used_cells, NULL, | |
267 | 0, NULL); | |
01636eb9 PR |
268 | if (err < 0) |
269 | goto err_disable_clk; | |
270 | ||
01636eb9 | 271 | platform_set_drvdata(pdev, tscadc); |
01636eb9 PR |
272 | return 0; |
273 | ||
274 | err_disable_clk: | |
275 | pm_runtime_put_sync(&pdev->dev); | |
276 | pm_runtime_disable(&pdev->dev); | |
3c39c9c6 | 277 | ret: |
01636eb9 PR |
278 | return err; |
279 | } | |
280 | ||
612b95cd | 281 | static int ti_tscadc_remove(struct platform_device *pdev) |
01636eb9 PR |
282 | { |
283 | struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev); | |
284 | ||
0d3a7cce | 285 | regmap_write(tscadc->regmap, REG_SE, 0x00); |
01636eb9 PR |
286 | |
287 | pm_runtime_put_sync(&pdev->dev); | |
288 | pm_runtime_disable(&pdev->dev); | |
289 | ||
290 | mfd_remove_devices(tscadc->dev); | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
c974ac77 V |
295 | static int __maybe_unused ti_tscadc_can_wakeup(struct device *dev, void *data) |
296 | { | |
297 | return device_may_wakeup(dev); | |
298 | } | |
299 | ||
dae936a0 | 300 | static int __maybe_unused tscadc_suspend(struct device *dev) |
01636eb9 | 301 | { |
a318b7d0 | 302 | struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev); |
01636eb9 | 303 | |
0d3a7cce | 304 | regmap_write(tscadc->regmap, REG_SE, 0x00); |
c974ac77 V |
305 | if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) { |
306 | u32 ctrl; | |
307 | ||
308 | regmap_read(tscadc->regmap, REG_CTRL, &ctrl); | |
309 | ctrl &= ~(CNTRLREG_POWERDOWN); | |
310 | ctrl |= CNTRLREG_TSCSSENB; | |
311 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); | |
312 | } | |
01636eb9 PR |
313 | pm_runtime_put_sync(dev); |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
dae936a0 | 318 | static int __maybe_unused tscadc_resume(struct device *dev) |
01636eb9 | 319 | { |
a318b7d0 | 320 | struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev); |
f0933a60 | 321 | u32 ctrl; |
01636eb9 PR |
322 | |
323 | pm_runtime_get_sync(dev); | |
324 | ||
325 | /* context restore */ | |
b5f8b763 | 326 | ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID; |
0d3a7cce | 327 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
b5f8b763 | 328 | |
a318b7d0 AD |
329 | if (tscadc->tsc_cell != -1) { |
330 | if (tscadc->tsc_wires == 5) | |
f0933a60 JL |
331 | ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB; |
332 | else | |
333 | ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB; | |
a318b7d0 | 334 | tscadc_idle_config(tscadc); |
f0933a60 JL |
335 | } |
336 | ctrl |= CNTRLREG_TSCSSENB; | |
0d3a7cce | 337 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
01636eb9 | 338 | |
0d3a7cce | 339 | regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div); |
e90f8754 | 340 | |
01636eb9 PR |
341 | return 0; |
342 | } | |
343 | ||
dae936a0 | 344 | static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume); |
01636eb9 | 345 | |
a6543a1c PR |
346 | static const struct of_device_id ti_tscadc_dt_ids[] = { |
347 | { .compatible = "ti,am3359-tscadc", }, | |
348 | { } | |
349 | }; | |
350 | MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids); | |
351 | ||
01636eb9 PR |
352 | static struct platform_driver ti_tscadc_driver = { |
353 | .driver = { | |
a6543a1c | 354 | .name = "ti_am3359-tscadc", |
dae936a0 | 355 | .pm = &tscadc_pm_ops, |
131221bc | 356 | .of_match_table = ti_tscadc_dt_ids, |
01636eb9 PR |
357 | }, |
358 | .probe = ti_tscadc_probe, | |
612b95cd | 359 | .remove = ti_tscadc_remove, |
01636eb9 PR |
360 | |
361 | }; | |
362 | ||
363 | module_platform_driver(ti_tscadc_driver); | |
364 | ||
365 | MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver"); | |
366 | MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); | |
367 | MODULE_LICENSE("GPL"); |