[linux-2.6-block.git] / drivers / mfd / ti_am335x_tscadc.c

/*
 * TI Touch Screen / ADC MFD driver
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/sched.h>

#include <linux/mfd/ti_am335x_tscadc.h>

static const struct regmap_config tscadc_regmap_config = {
	.name = "ti_tscadc",
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
};

void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->reg_se_cache |= val;
	if (tscadc->adc_waiting)
		wake_up(&tscadc->reg_se_wait);
	else if (!tscadc->adc_in_use)
		regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);

	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);

static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
{
	DEFINE_WAIT(wait);
	u32 reg;

	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
	if (reg & SEQ_STATUS) {
		tscadc->adc_waiting = true;
		prepare_to_wait(&tscadc->reg_se_wait, &wait,
				TASK_UNINTERRUPTIBLE);
		spin_unlock_irq(&tscadc->reg_lock);

		schedule();

		spin_lock_irq(&tscadc->reg_lock);
		finish_wait(&tscadc->reg_se_wait, &wait);

		/*
		 * Sequencer should either be idle or
		 * busy applying the charge step.
		 */
		regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
		WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
		tscadc->adc_waiting = false;
	}
	tscadc->adc_in_use = true;
}

void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
{
	spin_lock_irq(&tscadc->reg_lock);
	am335x_tscadc_need_adc(tscadc);

	regmap_write(tscadc->regmap, REG_SE, val);
	spin_unlock_irq(&tscadc->reg_lock);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);

void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->adc_in_use = false;
	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);

void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
{
	unsigned long flags;

	spin_lock_irqsave(&tscadc->reg_lock, flags);
	tscadc->reg_se_cache &= ~val;
	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
}
EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);

static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
{
	unsigned int idleconfig;

	idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
			STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;

	regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
}

static	int ti_tscadc_probe(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc;
	struct resource		*res;
	struct clk		*clk;
	struct device_node	*node;
	struct mfd_cell		*cell;
	struct property         *prop;
	const __be32            *cur;
	u32			val;
	int			err, ctrl;
	int			clock_rate;
	int			tsc_wires = 0, adc_channels = 0, total_channels;
	int			readouts = 0;

	if (!pdev->dev.of_node) {
		dev_err(&pdev->dev, "Could not find valid DT data.\n");
		return -EINVAL;
	}

	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
	of_property_read_u32(node, "ti,wires", &tsc_wires);
	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);

	node = of_get_child_by_name(pdev->dev.of_node, "adc");
	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
		adc_channels++;
		if (val > 7) {
			dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
					val);
			return -EINVAL;
		}
	}
	total_channels = tsc_wires + adc_channels;
	if (total_channels > 8) {
		dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
		return -EINVAL;
	}
	if (total_channels == 0) {
		dev_err(&pdev->dev, "Need atleast one channel.\n");
		return -EINVAL;
	}

	if (readouts * 2 + 2 + adc_channels > 16) {
		dev_err(&pdev->dev, "Too many step configurations requested\n");
		return -EINVAL;
	}

	/* Allocate memory for device */
	tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
	if (!tscadc)
		return -ENOMEM;

	tscadc->dev = &pdev->dev;

	err = platform_get_irq(pdev, 0);
	if (err < 0) {
		dev_err(&pdev->dev, "no irq ID is specified.\n");
		goto ret;
	} else
		tscadc->irq = err;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tscadc->tscadc_phys_base = res->start;
	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(tscadc->tscadc_base))
		return PTR_ERR(tscadc->tscadc_base);

	tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
			tscadc->tscadc_base, &tscadc_regmap_config);
	if (IS_ERR(tscadc->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		err = PTR_ERR(tscadc->regmap);
		goto ret;
	}

	spin_lock_init(&tscadc->reg_lock);
	init_waitqueue_head(&tscadc->reg_se_wait);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	/*
	 * The TSC_ADC_Subsystem has 2 clock domains
	 * OCP_CLK and ADC_CLK.
	 * The ADC clock is expected to run at target of 3MHz,
	 * and expected to capture 12-bit data at a rate of 200 KSPS.
	 * The TSC_ADC_SS controller design assumes the OCP clock is
	 * at least 6x faster than the ADC clock.
	 */
	clk = devm_clk_get(&pdev->dev, "adc_tsc_fck");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get TSC fck\n");
		err = PTR_ERR(clk);
		goto err_disable_clk;
	}
	clock_rate = clk_get_rate(clk);
	tscadc->clk_div = clock_rate / ADC_CLK;

	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
	tscadc->clk_div--;
	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);

	/* Set the control register bits */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	/* Set register bits for Idle Config Mode */
	if (tsc_wires > 0) {
		tscadc->tsc_wires = tsc_wires;
		if (tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc);
	}

	/* Enable the TSC module enable bit */
	ctrl |= CNTRLREG_TSCSSENB;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	tscadc->used_cells = 0;
	tscadc->tsc_cell = -1;
	tscadc->adc_cell = -1;

	/* TSC Cell */
	if (tsc_wires > 0) {
		tscadc->tsc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-tsc";
		cell->of_compatible = "ti,am3359-tsc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	/* ADC Cell */
	if (adc_channels > 0) {
		tscadc->adc_cell = tscadc->used_cells;
		cell = &tscadc->cells[tscadc->used_cells++];
		cell->name = "TI-am335x-adc";
		cell->of_compatible = "ti,am3359-adc";
		cell->platform_data = &tscadc;
		cell->pdata_size = sizeof(tscadc);
	}

	err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
			      tscadc->cells, tscadc->used_cells, NULL,
			      0, NULL);
	if (err < 0)
		goto err_disable_clk;

	platform_set_drvdata(pdev, tscadc);
	return 0;

err_disable_clk:
	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
ret:
	return err;
}

static int ti_tscadc_remove(struct platform_device *pdev)
{
	struct ti_tscadc_dev	*tscadc = platform_get_drvdata(pdev);

	regmap_write(tscadc->regmap, REG_SE, 0x00);

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	mfd_remove_devices(tscadc->dev);

	return 0;
}

static int __maybe_unused ti_tscadc_can_wakeup(struct device *dev, void *data)
{
	return device_may_wakeup(dev);
}

static int __maybe_unused tscadc_suspend(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc = dev_get_drvdata(dev);

	regmap_write(tscadc->regmap, REG_SE, 0x00);
	if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) {
		u32 ctrl;

		regmap_read(tscadc->regmap, REG_CTRL, &ctrl);
		ctrl &= ~(CNTRLREG_POWERDOWN);
		ctrl |= CNTRLREG_TSCSSENB;
		regmap_write(tscadc->regmap, REG_CTRL, ctrl);
	}
	pm_runtime_put_sync(dev);

	return 0;
}

static int __maybe_unused tscadc_resume(struct device *dev)
{
	struct ti_tscadc_dev	*tscadc = dev_get_drvdata(dev);
	u32 ctrl;

	pm_runtime_get_sync(dev);

	/* context restore */
	ctrl = CNTRLREG_STEPCONFIGWRT |	CNTRLREG_STEPID;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	if (tscadc->tsc_cell != -1) {
		if (tscadc->tsc_wires == 5)
			ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
		else
			ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
		tscadc_idle_config(tscadc);
	}
	ctrl |= CNTRLREG_TSCSSENB;
	regmap_write(tscadc->regmap, REG_CTRL, ctrl);

	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);

	return 0;
}

static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);

static const struct of_device_id ti_tscadc_dt_ids[] = {
	{ .compatible = "ti,am3359-tscadc", },
	{ }
};
MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);

static struct platform_driver ti_tscadc_driver = {
	.driver = {
		.name   = "ti_am3359-tscadc",
		.pm	= &tscadc_pm_ops,
		.of_match_table = ti_tscadc_dt_ids,
	},
	.probe	= ti_tscadc_probe,
	.remove	= ti_tscadc_remove,

};

module_platform_driver(ti_tscadc_driver);

MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
01636eb9 PR	1	/*
	2	* TI Touch Screen / ADC MFD driver
	3	*
	4	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/module.h>
01636eb9 PR	17	#include <linux/slab.h>
	18	#include <linux/err.h>
	19	#include <linux/io.h>
	20	#include <linux/clk.h>
	21	#include <linux/regmap.h>
	22	#include <linux/mfd/core.h>
	23	#include <linux/pm_runtime.h>
a6543a1c PR	24	#include <linux/of.h>
a6543a1c PR	25	#include <linux/of_device.h>
7ca6740c	26	#include <linux/sched.h>
01636eb9 PR	27
	28	#include <linux/mfd/ti_am335x_tscadc.h>
	29
01636eb9 PR	30	static const struct regmap_config tscadc_regmap_config = {
	31	.name = "ti_tscadc",
	32	.reg_bits = 32,
	33	.reg_stride = 4,
	34	.val_bits = 32,
	35	};
	36
a318b7d0	37	void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val)
abeccee4	38	{
317b2099 SAS	39	unsigned long flags;
317b2099 SAS	40
a318b7d0 AD	41	spin_lock_irqsave(&tscadc->reg_lock, flags);
	42	tscadc->reg_se_cache \|= val;
	43	if (tscadc->adc_waiting)
	44	wake_up(&tscadc->reg_se_wait);
	45	else if (!tscadc->adc_in_use)
0d3a7cce	46	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
7ca6740c	47
a318b7d0	48	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
abeccee4	49	}
7e170c6e SAS	50	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
7e170c6e SAS	51
a318b7d0	52	static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc)
7ca6740c SAS	53	{
	54	DEFINE_WAIT(wait);
	55	u32 reg;
	56
0d3a7cce	57	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
7ca6740c	58	if (reg & SEQ_STATUS) {
a318b7d0 AD	59	tscadc->adc_waiting = true;
a318b7d0 AD	60	prepare_to_wait(&tscadc->reg_se_wait, &wait,
7ca6740c	61	TASK_UNINTERRUPTIBLE);
a318b7d0	62	spin_unlock_irq(&tscadc->reg_lock);
7ca6740c SAS	63
	64	schedule();
	65
a318b7d0 AD	66	spin_lock_irq(&tscadc->reg_lock);
a318b7d0 AD	67	finish_wait(&tscadc->reg_se_wait, &wait);
7ca6740c	68
b10848e6 V	69	/*
	70	* Sequencer should either be idle or
	71	* busy applying the charge step.
	72	*/
0d3a7cce	73	regmap_read(tscadc->regmap, REG_ADCFSM, &reg);
b10848e6	74	WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP));
a318b7d0	75	tscadc->adc_waiting = false;
7ca6740c	76	}
a318b7d0	77	tscadc->adc_in_use = true;
7ca6740c SAS	78	}
7ca6740c SAS	79
a318b7d0	80	void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val)
7ca6740c	81	{
a318b7d0 AD	82	spin_lock_irq(&tscadc->reg_lock);
a318b7d0 AD	83	am335x_tscadc_need_adc(tscadc);
7ca6740c	84
0d3a7cce	85	regmap_write(tscadc->regmap, REG_SE, val);
a318b7d0	86	spin_unlock_irq(&tscadc->reg_lock);
7ca6740c SAS	87	}
	88	EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
	89
a318b7d0	90	void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc)
7e170c6e SAS	91	{
	92	unsigned long flags;
	93
a318b7d0 AD	94	spin_lock_irqsave(&tscadc->reg_lock, flags);
a318b7d0 AD	95	tscadc->adc_in_use = false;
0d3a7cce	96	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
a318b7d0	97	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
7e170c6e	98	}
7ca6740c	99	EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
abeccee4	100
a318b7d0	101	void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val)
abeccee4	102	{
317b2099 SAS	103	unsigned long flags;
317b2099 SAS	104
a318b7d0 AD	105	spin_lock_irqsave(&tscadc->reg_lock, flags);
a318b7d0 AD	106	tscadc->reg_se_cache &= ~val;
0d3a7cce	107	regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache);
a318b7d0	108	spin_unlock_irqrestore(&tscadc->reg_lock, flags);
abeccee4 PR	109	}
	110	EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
	111
a318b7d0	112	static void tscadc_idle_config(struct ti_tscadc_dev *tscadc)
01636eb9 PR	113	{
	114	unsigned int idleconfig;
	115
	116	idleconfig = STEPCONFIG_YNN \| STEPCONFIG_INM_ADCREFM \|
	117	STEPCONFIG_INP_ADCREFM \| STEPCONFIG_YPN;
	118
0d3a7cce	119	regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig);
01636eb9 PR	120	}
01636eb9 PR	121
612b95cd	122	static int ti_tscadc_probe(struct platform_device *pdev)
01636eb9 PR	123	{
	124	struct ti_tscadc_dev *tscadc;
	125	struct resource *res;
	126	struct clk *clk;
e368866e	127	struct device_node *node;
2b99bafa	128	struct mfd_cell *cell;
18926ede SAS	129	struct property *prop;
	130	const __be32 *cur;
	131	u32 val;
01636eb9	132	int err, ctrl;
e90f8754	133	int clock_rate;
a6543a1c	134	int tsc_wires = 0, adc_channels = 0, total_channels;
18926ede	135	int readouts = 0;
01636eb9	136
9e5775f3 SAS	137	if (!pdev->dev.of_node) {
9e5775f3 SAS	138	dev_err(&pdev->dev, "Could not find valid DT data.\n");
01636eb9 PR	139	return -EINVAL;
	140	}
	141
9e5775f3 SAS	142	node = of_get_child_by_name(pdev->dev.of_node, "tsc");
9e5775f3 SAS	143	of_property_read_u32(node, "ti,wires", &tsc_wires);
18926ede	144	of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
a6543a1c	145
9e5775f3	146	node = of_get_child_by_name(pdev->dev.of_node, "adc");
18926ede SAS	147	of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
	148	adc_channels++;
	149	if (val > 7) {
	150	dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
	151	val);
	152	return -EINVAL;
	153	}
	154	}
5e53a69b	155	total_channels = tsc_wires + adc_channels;
5e53a69b PR	156	if (total_channels > 8) {
	157	dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
	158	return -EINVAL;
	159	}
24d5c82f PA	160	if (total_channels == 0) {
	161	dev_err(&pdev->dev, "Need atleast one channel.\n");
	162	return -EINVAL;
	163	}
2b99bafa	164
18926ede SAS	165	if (readouts * 2 + 2 + adc_channels > 16) {
	166	dev_err(&pdev->dev, "Too many step configurations requested\n");
	167	return -EINVAL;
	168	}
	169
01636eb9	170	/* Allocate memory for device */
dea1c703	171	tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL);
a2e87fee	172	if (!tscadc)
01636eb9	173	return -ENOMEM;
a2e87fee	174
01636eb9	175	tscadc->dev = &pdev->dev;
3c39c9c6 PR	176
	177	err = platform_get_irq(pdev, 0);
	178	if (err < 0) {
	179	dev_err(&pdev->dev, "no irq ID is specified.\n");
	180	goto ret;
	181	} else
	182	tscadc->irq = err;
01636eb9	183
924ff918	184	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c9329d86	185	tscadc->tscadc_phys_base = res->start;
924ff918 JH	186	tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
	187	if (IS_ERR(tscadc->tscadc_base))
	188	return PTR_ERR(tscadc->tscadc_base);
01636eb9	189
0d3a7cce	190	tscadc->regmap = devm_regmap_init_mmio(&pdev->dev,
01636eb9	191	tscadc->tscadc_base, &tscadc_regmap_config);
0d3a7cce	192	if (IS_ERR(tscadc->regmap)) {
01636eb9	193	dev_err(&pdev->dev, "regmap init failed\n");
0d3a7cce	194	err = PTR_ERR(tscadc->regmap);
3c39c9c6	195	goto ret;
01636eb9 PR	196	}
01636eb9 PR	197
abeccee4	198	spin_lock_init(&tscadc->reg_lock);
7ca6740c SAS	199	init_waitqueue_head(&tscadc->reg_se_wait);
7ca6740c SAS	200
01636eb9 PR	201	pm_runtime_enable(&pdev->dev);
	202	pm_runtime_get_sync(&pdev->dev);
	203
	204	/*
	205	* The TSC_ADC_Subsystem has 2 clock domains
	206	* OCP_CLK and ADC_CLK.
	207	* The ADC clock is expected to run at target of 3MHz,
	208	* and expected to capture 12-bit data at a rate of 200 KSPS.
	209	* The TSC_ADC_SS controller design assumes the OCP clock is
	210	* at least 6x faster than the ADC clock.
	211	*/
c2b1509c	212	clk = devm_clk_get(&pdev->dev, "adc_tsc_fck");
01636eb9 PR	213	if (IS_ERR(clk)) {
	214	dev_err(&pdev->dev, "failed to get TSC fck\n");
	215	err = PTR_ERR(clk);
	216	goto err_disable_clk;
	217	}
	218	clock_rate = clk_get_rate(clk);
e90f8754	219	tscadc->clk_div = clock_rate / ADC_CLK;
efe3126a	220
01636eb9	221	/* TSCADC_CLKDIV needs to be configured to the value minus 1 */
e90f8754	222	tscadc->clk_div--;
0d3a7cce	223	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
01636eb9 PR	224
01636eb9 PR	225	/* Set the control register bits */
f0933a60	226	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
0d3a7cce	227	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9 PR	228
01636eb9 PR	229	/* Set register bits for Idle Config Mode */
f0933a60 JL	230	if (tsc_wires > 0) {
	231	tscadc->tsc_wires = tsc_wires;
	232	if (tsc_wires == 5)
	233	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	234	else
	235	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
b5f8b763	236	tscadc_idle_config(tscadc);
f0933a60	237	}
01636eb9 PR	238
01636eb9 PR	239	/* Enable the TSC module enable bit */
01636eb9	240	ctrl \|= CNTRLREG_TSCSSENB;
0d3a7cce	241	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9	242
24d5c82f PA	243	tscadc->used_cells = 0;
	244	tscadc->tsc_cell = -1;
	245	tscadc->adc_cell = -1;
	246
2b99bafa	247	/* TSC Cell */
24d5c82f PA	248	if (tsc_wires > 0) {
	249	tscadc->tsc_cell = tscadc->used_cells;
	250	cell = &tscadc->cells[tscadc->used_cells++];
5f184e63	251	cell->name = "TI-am335x-tsc";
24d5c82f PA	252	cell->of_compatible = "ti,am3359-tsc";
	253	cell->platform_data = &tscadc;
	254	cell->pdata_size = sizeof(tscadc);
	255	}
2b99bafa	256
5e53a69b	257	/* ADC Cell */
24d5c82f PA	258	if (adc_channels > 0) {
	259	tscadc->adc_cell = tscadc->used_cells;
	260	cell = &tscadc->cells[tscadc->used_cells++];
9f99928f	261	cell->name = "TI-am335x-adc";
24d5c82f PA	262	cell->of_compatible = "ti,am3359-adc";
	263	cell->platform_data = &tscadc;
	264	cell->pdata_size = sizeof(tscadc);
	265	}
5e53a69b	266
b40ee006 V	267	err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO,
	268	tscadc->cells, tscadc->used_cells, NULL,
	269	0, NULL);
01636eb9 PR	270	if (err < 0)
	271	goto err_disable_clk;
	272
01636eb9	273	platform_set_drvdata(pdev, tscadc);
01636eb9 PR	274	return 0;
	275
	276	err_disable_clk:
	277	pm_runtime_put_sync(&pdev->dev);
	278	pm_runtime_disable(&pdev->dev);
3c39c9c6	279	ret:
01636eb9 PR	280	return err;
	281	}
	282
612b95cd	283	static int ti_tscadc_remove(struct platform_device *pdev)
01636eb9 PR	284	{
	285	struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
	286
0d3a7cce	287	regmap_write(tscadc->regmap, REG_SE, 0x00);
01636eb9 PR	288
	289	pm_runtime_put_sync(&pdev->dev);
	290	pm_runtime_disable(&pdev->dev);
	291
	292	mfd_remove_devices(tscadc->dev);
	293
	294	return 0;
	295	}
	296
c974ac77 V	297	static int __maybe_unused ti_tscadc_can_wakeup(struct device dev, void data)
	298	{
	299	return device_may_wakeup(dev);
	300	}
	301
dae936a0	302	static int __maybe_unused tscadc_suspend(struct device *dev)
01636eb9	303	{
a318b7d0	304	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
01636eb9	305
0d3a7cce	306	regmap_write(tscadc->regmap, REG_SE, 0x00);
c974ac77 V	307	if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) {
	308	u32 ctrl;
	309
	310	regmap_read(tscadc->regmap, REG_CTRL, &ctrl);
	311	ctrl &= ~(CNTRLREG_POWERDOWN);
	312	ctrl \|= CNTRLREG_TSCSSENB;
	313	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
	314	}
01636eb9 PR	315	pm_runtime_put_sync(dev);
	316
	317	return 0;
	318	}
	319
dae936a0	320	static int __maybe_unused tscadc_resume(struct device *dev)
01636eb9	321	{
a318b7d0	322	struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev);
f0933a60	323	u32 ctrl;
01636eb9 PR	324
	325	pm_runtime_get_sync(dev);
	326
	327	/* context restore */
b5f8b763	328	ctrl = CNTRLREG_STEPCONFIGWRT \| CNTRLREG_STEPID;
0d3a7cce	329	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
b5f8b763	330
a318b7d0 AD	331	if (tscadc->tsc_cell != -1) {
a318b7d0 AD	332	if (tscadc->tsc_wires == 5)
f0933a60 JL	333	ctrl \|= CNTRLREG_5WIRE \| CNTRLREG_TSCENB;
	334	else
	335	ctrl \|= CNTRLREG_4WIRE \| CNTRLREG_TSCENB;
a318b7d0	336	tscadc_idle_config(tscadc);
f0933a60 JL	337	}
f0933a60 JL	338	ctrl \|= CNTRLREG_TSCSSENB;
0d3a7cce	339	regmap_write(tscadc->regmap, REG_CTRL, ctrl);
01636eb9	340
0d3a7cce	341	regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div);
e90f8754	342
01636eb9 PR	343	return 0;
	344	}
	345
dae936a0	346	static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume);
01636eb9	347
a6543a1c PR	348	static const struct of_device_id ti_tscadc_dt_ids[] = {
	349	{ .compatible = "ti,am3359-tscadc", },
	350	{ }
	351	};
	352	MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
	353
01636eb9 PR	354	static struct platform_driver ti_tscadc_driver = {
01636eb9 PR	355	.driver = {
a6543a1c	356	.name = "ti_am3359-tscadc",
dae936a0	357	.pm = &tscadc_pm_ops,
131221bc	358	.of_match_table = ti_tscadc_dt_ids,
01636eb9 PR	359	},
01636eb9 PR	360	.probe = ti_tscadc_probe,
612b95cd	361	.remove = ti_tscadc_remove,
01636eb9 PR	362
	363	};
	364
	365	module_platform_driver(ti_tscadc_driver);
	366
	367	MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
	368	MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
	369	MODULE_LICENSE("GPL");