Commit | Line | Data |
---|---|---|
3bda759f | 1 | // SPDX-License-Identifier: GPL-2.0-only |
01636eb9 PR |
2 | /* |
3 | * TI Touch Screen / ADC MFD driver | |
4 | * | |
4f4ed454 | 5 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
01636eb9 PR |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
01636eb9 PR |
9 | #include <linux/slab.h> |
10 | #include <linux/err.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/regmap.h> | |
14 | #include <linux/mfd/core.h> | |
15 | #include <linux/pm_runtime.h> | |
a6543a1c PR |
16 | #include <linux/of.h> |
17 | #include <linux/of_device.h> | |
7ca6740c | 18 | #include <linux/sched.h> |
01636eb9 PR |
19 | |
20 | #include <linux/mfd/ti_am335x_tscadc.h> | |
21 | ||
01636eb9 PR |
22 | static const struct regmap_config tscadc_regmap_config = { |
23 | .name = "ti_tscadc", | |
24 | .reg_bits = 32, | |
25 | .reg_stride = 4, | |
26 | .val_bits = 32, | |
27 | }; | |
28 | ||
a318b7d0 | 29 | void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tscadc, u32 val) |
abeccee4 | 30 | { |
317b2099 SAS |
31 | unsigned long flags; |
32 | ||
a318b7d0 AD |
33 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
34 | tscadc->reg_se_cache |= val; | |
35 | if (tscadc->adc_waiting) | |
36 | wake_up(&tscadc->reg_se_wait); | |
37 | else if (!tscadc->adc_in_use) | |
0d3a7cce | 38 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
7ca6740c | 39 | |
a318b7d0 | 40 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
abeccee4 | 41 | } |
7e170c6e SAS |
42 | EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache); |
43 | ||
a318b7d0 | 44 | static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tscadc) |
7ca6740c SAS |
45 | { |
46 | DEFINE_WAIT(wait); | |
47 | u32 reg; | |
48 | ||
0d3a7cce | 49 | regmap_read(tscadc->regmap, REG_ADCFSM, ®); |
7ca6740c | 50 | if (reg & SEQ_STATUS) { |
a318b7d0 AD |
51 | tscadc->adc_waiting = true; |
52 | prepare_to_wait(&tscadc->reg_se_wait, &wait, | |
7ca6740c | 53 | TASK_UNINTERRUPTIBLE); |
a318b7d0 | 54 | spin_unlock_irq(&tscadc->reg_lock); |
7ca6740c SAS |
55 | |
56 | schedule(); | |
57 | ||
a318b7d0 AD |
58 | spin_lock_irq(&tscadc->reg_lock); |
59 | finish_wait(&tscadc->reg_se_wait, &wait); | |
7ca6740c | 60 | |
b10848e6 V |
61 | /* |
62 | * Sequencer should either be idle or | |
63 | * busy applying the charge step. | |
64 | */ | |
0d3a7cce | 65 | regmap_read(tscadc->regmap, REG_ADCFSM, ®); |
b10848e6 | 66 | WARN_ON((reg & SEQ_STATUS) && !(reg & CHARGE_STEP)); |
a318b7d0 | 67 | tscadc->adc_waiting = false; |
7ca6740c | 68 | } |
a318b7d0 | 69 | tscadc->adc_in_use = true; |
7ca6740c SAS |
70 | } |
71 | ||
a318b7d0 | 72 | void am335x_tsc_se_set_once(struct ti_tscadc_dev *tscadc, u32 val) |
7ca6740c | 73 | { |
a318b7d0 AD |
74 | spin_lock_irq(&tscadc->reg_lock); |
75 | am335x_tscadc_need_adc(tscadc); | |
7ca6740c | 76 | |
0d3a7cce | 77 | regmap_write(tscadc->regmap, REG_SE, val); |
a318b7d0 | 78 | spin_unlock_irq(&tscadc->reg_lock); |
7ca6740c SAS |
79 | } |
80 | EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once); | |
81 | ||
a318b7d0 | 82 | void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tscadc) |
7e170c6e SAS |
83 | { |
84 | unsigned long flags; | |
85 | ||
a318b7d0 AD |
86 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
87 | tscadc->adc_in_use = false; | |
0d3a7cce | 88 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
a318b7d0 | 89 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
7e170c6e | 90 | } |
7ca6740c | 91 | EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done); |
abeccee4 | 92 | |
a318b7d0 | 93 | void am335x_tsc_se_clr(struct ti_tscadc_dev *tscadc, u32 val) |
abeccee4 | 94 | { |
317b2099 SAS |
95 | unsigned long flags; |
96 | ||
a318b7d0 AD |
97 | spin_lock_irqsave(&tscadc->reg_lock, flags); |
98 | tscadc->reg_se_cache &= ~val; | |
0d3a7cce | 99 | regmap_write(tscadc->regmap, REG_SE, tscadc->reg_se_cache); |
a318b7d0 | 100 | spin_unlock_irqrestore(&tscadc->reg_lock, flags); |
abeccee4 PR |
101 | } |
102 | EXPORT_SYMBOL_GPL(am335x_tsc_se_clr); | |
103 | ||
a318b7d0 | 104 | static void tscadc_idle_config(struct ti_tscadc_dev *tscadc) |
01636eb9 PR |
105 | { |
106 | unsigned int idleconfig; | |
107 | ||
bf0f394c MR |
108 | idleconfig = STEPCONFIG_INM_ADCREFM | STEPCONFIG_INP_ADCREFM; |
109 | if (ti_adc_with_touchscreen(tscadc)) | |
110 | idleconfig |= STEPCONFIG_YNN | STEPCONFIG_YPN; | |
01636eb9 | 111 | |
0d3a7cce | 112 | regmap_write(tscadc->regmap, REG_IDLECONFIG, idleconfig); |
01636eb9 PR |
113 | } |
114 | ||
612b95cd | 115 | static int ti_tscadc_probe(struct platform_device *pdev) |
01636eb9 | 116 | { |
36e48f07 MR |
117 | struct ti_tscadc_dev *tscadc; |
118 | struct resource *res; | |
119 | struct clk *clk; | |
120 | struct device_node *node; | |
121 | struct mfd_cell *cell; | |
122 | struct property *prop; | |
123 | const __be32 *cur; | |
0a123303 | 124 | bool use_tsc = false, use_mag = false; |
36e48f07 | 125 | u32 val; |
b813f320 | 126 | int err; |
430b98fc | 127 | int tscmag_wires = 0, adc_channels = 0, cell_idx = 0, total_channels; |
0a123303 | 128 | int readouts = 0, mag_tracks = 0; |
01636eb9 | 129 | |
61479479 MR |
130 | /* Allocate memory for device */ |
131 | tscadc = devm_kzalloc(&pdev->dev, sizeof(*tscadc), GFP_KERNEL); | |
132 | if (!tscadc) | |
133 | return -ENOMEM; | |
134 | ||
135 | tscadc->dev = &pdev->dev; | |
136 | ||
9e5775f3 SAS |
137 | if (!pdev->dev.of_node) { |
138 | dev_err(&pdev->dev, "Could not find valid DT data.\n"); | |
01636eb9 PR |
139 | return -EINVAL; |
140 | } | |
141 | ||
f7834843 MR |
142 | tscadc->data = of_device_get_match_data(&pdev->dev); |
143 | ||
bf0f394c MR |
144 | if (ti_adc_with_touchscreen(tscadc)) { |
145 | node = of_get_child_by_name(pdev->dev.of_node, "tsc"); | |
146 | of_property_read_u32(node, "ti,wires", &tscmag_wires); | |
90fc6ff4 MR |
147 | err = of_property_read_u32(node, "ti,coordinate-readouts", |
148 | &readouts); | |
149 | if (err < 0) | |
150 | of_property_read_u32(node, "ti,coordiante-readouts", | |
151 | &readouts); | |
152 | ||
bf0f394c | 153 | of_node_put(node); |
90fc6ff4 | 154 | |
bf0f394c MR |
155 | if (tscmag_wires) |
156 | use_tsc = true; | |
0a123303 MR |
157 | } else { |
158 | /* | |
159 | * When adding support for the magnetic stripe reader, here is | |
160 | * the place to look for the number of tracks used from device | |
161 | * tree. Let's default to 0 for now. | |
162 | */ | |
163 | mag_tracks = 0; | |
164 | tscmag_wires = mag_tracks * 2; | |
165 | if (tscmag_wires) | |
166 | use_mag = true; | |
bf0f394c | 167 | } |
a6543a1c | 168 | |
9e5775f3 | 169 | node = of_get_child_by_name(pdev->dev.of_node, "adc"); |
18926ede SAS |
170 | of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) { |
171 | adc_channels++; | |
172 | if (val > 7) { | |
173 | dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n", | |
243e3cb9 | 174 | val); |
29f95e8b | 175 | of_node_put(node); |
18926ede SAS |
176 | return -EINVAL; |
177 | } | |
178 | } | |
29f95e8b MR |
179 | |
180 | of_node_put(node); | |
181 | ||
430b98fc | 182 | total_channels = tscmag_wires + adc_channels; |
5e53a69b PR |
183 | if (total_channels > 8) { |
184 | dev_err(&pdev->dev, "Number of i/p channels more than 8\n"); | |
185 | return -EINVAL; | |
186 | } | |
243e3cb9 | 187 | |
24d5c82f | 188 | if (total_channels == 0) { |
ad70c03f | 189 | dev_err(&pdev->dev, "Need at least one channel.\n"); |
24d5c82f PA |
190 | return -EINVAL; |
191 | } | |
2b99bafa | 192 | |
2a4e333a | 193 | if (use_tsc && (readouts * 2 + 2 + adc_channels > 16)) { |
18926ede SAS |
194 | dev_err(&pdev->dev, "Too many step configurations requested\n"); |
195 | return -EINVAL; | |
196 | } | |
197 | ||
3c39c9c6 | 198 | err = platform_get_irq(pdev, 0); |
bc239d8d | 199 | if (err < 0) |
287ee127 | 200 | return err; |
bc239d8d | 201 | else |
3c39c9c6 | 202 | tscadc->irq = err; |
01636eb9 | 203 | |
924ff918 JH |
204 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
205 | tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res); | |
206 | if (IS_ERR(tscadc->tscadc_base)) | |
207 | return PTR_ERR(tscadc->tscadc_base); | |
01636eb9 | 208 | |
de98a43e | 209 | tscadc->tscadc_phys_base = res->start; |
0d3a7cce | 210 | tscadc->regmap = devm_regmap_init_mmio(&pdev->dev, |
243e3cb9 MR |
211 | tscadc->tscadc_base, |
212 | &tscadc_regmap_config); | |
0d3a7cce | 213 | if (IS_ERR(tscadc->regmap)) { |
01636eb9 | 214 | dev_err(&pdev->dev, "regmap init failed\n"); |
287ee127 | 215 | return PTR_ERR(tscadc->regmap); |
01636eb9 PR |
216 | } |
217 | ||
abeccee4 | 218 | spin_lock_init(&tscadc->reg_lock); |
7ca6740c SAS |
219 | init_waitqueue_head(&tscadc->reg_se_wait); |
220 | ||
01636eb9 PR |
221 | pm_runtime_enable(&pdev->dev); |
222 | pm_runtime_get_sync(&pdev->dev); | |
223 | ||
224 | /* | |
c4359f75 MR |
225 | * The TSC_ADC_Subsystem has 2 clock domains: OCP_CLK and ADC_CLK. |
226 | * ADCs produce a 12-bit sample every 15 ADC_CLK cycles. | |
227 | * am33xx ADCs expect to capture 200ksps. | |
0a123303 MR |
228 | * am47xx ADCs expect to capture 867ksps. |
229 | * We need ADC clocks respectively running at 3MHz and 13MHz. | |
230 | * These frequencies are valid since TSC_ADC_SS controller design | |
c4359f75 | 231 | * assumes the OCP clock is at least 6x faster than the ADC clock. |
01636eb9 | 232 | */ |
235a96e9 | 233 | clk = devm_clk_get(&pdev->dev, NULL); |
01636eb9 | 234 | if (IS_ERR(clk)) { |
e40b5971 | 235 | dev_err(&pdev->dev, "failed to get fck\n"); |
01636eb9 PR |
236 | err = PTR_ERR(clk); |
237 | goto err_disable_clk; | |
238 | } | |
efe3126a | 239 | |
f7834843 | 240 | tscadc->clk_div = (clk_get_rate(clk) / tscadc->data->target_clk_rate) - 1; |
0d3a7cce | 241 | regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div); |
01636eb9 | 242 | |
b813f320 MR |
243 | /* |
244 | * Set the control register bits. tscadc->ctrl stores the configuration | |
245 | * of the CTRL register but not the subsystem enable bit which must be | |
246 | * added manually when timely. | |
247 | */ | |
bf0f394c MR |
248 | tscadc->ctrl = CNTRLREG_STEPID; |
249 | if (ti_adc_with_touchscreen(tscadc)) { | |
250 | tscadc->ctrl |= CNTRLREG_TSC_STEPCONFIGWRT; | |
251 | if (use_tsc) { | |
252 | tscadc->ctrl |= CNTRLREG_TSC_ENB; | |
253 | if (tscmag_wires == 5) | |
254 | tscadc->ctrl |= CNTRLREG_TSC_5WIRE; | |
255 | else | |
256 | tscadc->ctrl |= CNTRLREG_TSC_4WIRE; | |
257 | } | |
0a123303 MR |
258 | } else { |
259 | tscadc->ctrl |= CNTRLREG_MAG_PREAMP_PWRDOWN | | |
260 | CNTRLREG_MAG_PREAMP_BYPASS; | |
f0933a60 | 261 | } |
b813f320 | 262 | regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl); |
01636eb9 | 263 | |
25b15d04 MR |
264 | tscadc_idle_config(tscadc); |
265 | ||
01636eb9 | 266 | /* Enable the TSC module enable bit */ |
c3e36b5d | 267 | regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl | CNTRLREG_SSENB); |
01636eb9 | 268 | |
0a123303 MR |
269 | /* TSC or MAG Cell */ |
270 | if (use_tsc || use_mag) { | |
7c605802 | 271 | cell = &tscadc->cells[cell_idx++]; |
f7834843 MR |
272 | cell->name = tscadc->data->secondary_feature_name; |
273 | cell->of_compatible = tscadc->data->secondary_feature_compatible; | |
24d5c82f PA |
274 | cell->platform_data = &tscadc; |
275 | cell->pdata_size = sizeof(tscadc); | |
276 | } | |
2b99bafa | 277 | |
5e53a69b | 278 | /* ADC Cell */ |
24d5c82f | 279 | if (adc_channels > 0) { |
7c605802 | 280 | cell = &tscadc->cells[cell_idx++]; |
f7834843 MR |
281 | cell->name = tscadc->data->adc_feature_name; |
282 | cell->of_compatible = tscadc->data->adc_feature_compatible; | |
24d5c82f PA |
283 | cell->platform_data = &tscadc; |
284 | cell->pdata_size = sizeof(tscadc); | |
285 | } | |
5e53a69b | 286 | |
b40ee006 | 287 | err = mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, |
7c605802 | 288 | tscadc->cells, cell_idx, NULL, 0, NULL); |
01636eb9 PR |
289 | if (err < 0) |
290 | goto err_disable_clk; | |
291 | ||
01636eb9 | 292 | platform_set_drvdata(pdev, tscadc); |
01636eb9 PR |
293 | return 0; |
294 | ||
295 | err_disable_clk: | |
296 | pm_runtime_put_sync(&pdev->dev); | |
297 | pm_runtime_disable(&pdev->dev); | |
287ee127 | 298 | |
01636eb9 PR |
299 | return err; |
300 | } | |
301 | ||
612b95cd | 302 | static int ti_tscadc_remove(struct platform_device *pdev) |
01636eb9 | 303 | { |
36e48f07 | 304 | struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev); |
01636eb9 | 305 | |
0d3a7cce | 306 | regmap_write(tscadc->regmap, REG_SE, 0x00); |
01636eb9 PR |
307 | |
308 | pm_runtime_put_sync(&pdev->dev); | |
309 | pm_runtime_disable(&pdev->dev); | |
310 | ||
311 | mfd_remove_devices(tscadc->dev); | |
312 | ||
313 | return 0; | |
314 | } | |
315 | ||
c974ac77 V |
316 | static int __maybe_unused ti_tscadc_can_wakeup(struct device *dev, void *data) |
317 | { | |
318 | return device_may_wakeup(dev); | |
319 | } | |
320 | ||
dae936a0 | 321 | static int __maybe_unused tscadc_suspend(struct device *dev) |
01636eb9 | 322 | { |
36e48f07 | 323 | struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev); |
01636eb9 | 324 | |
0d3a7cce | 325 | regmap_write(tscadc->regmap, REG_SE, 0x00); |
c974ac77 V |
326 | if (device_for_each_child(dev, NULL, ti_tscadc_can_wakeup)) { |
327 | u32 ctrl; | |
328 | ||
329 | regmap_read(tscadc->regmap, REG_CTRL, &ctrl); | |
330 | ctrl &= ~(CNTRLREG_POWERDOWN); | |
c3e36b5d | 331 | ctrl |= CNTRLREG_SSENB; |
c974ac77 V |
332 | regmap_write(tscadc->regmap, REG_CTRL, ctrl); |
333 | } | |
01636eb9 PR |
334 | pm_runtime_put_sync(dev); |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
dae936a0 | 339 | static int __maybe_unused tscadc_resume(struct device *dev) |
01636eb9 | 340 | { |
36e48f07 | 341 | struct ti_tscadc_dev *tscadc = dev_get_drvdata(dev); |
01636eb9 PR |
342 | |
343 | pm_runtime_get_sync(dev); | |
344 | ||
3dafbe93 | 345 | regmap_write(tscadc->regmap, REG_CLKDIV, tscadc->clk_div); |
b813f320 | 346 | regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl); |
25b15d04 | 347 | tscadc_idle_config(tscadc); |
c3e36b5d | 348 | regmap_write(tscadc->regmap, REG_CTRL, tscadc->ctrl | CNTRLREG_SSENB); |
01636eb9 PR |
349 | |
350 | return 0; | |
351 | } | |
352 | ||
dae936a0 | 353 | static SIMPLE_DEV_PM_OPS(tscadc_pm_ops, tscadc_suspend, tscadc_resume); |
01636eb9 | 354 | |
f7834843 MR |
355 | static const struct ti_tscadc_data tscdata = { |
356 | .adc_feature_name = "TI-am335x-adc", | |
357 | .adc_feature_compatible = "ti,am3359-adc", | |
358 | .secondary_feature_name = "TI-am335x-tsc", | |
359 | .secondary_feature_compatible = "ti,am3359-tsc", | |
2f89c261 | 360 | .target_clk_rate = TSC_ADC_CLK, |
f7834843 MR |
361 | }; |
362 | ||
0a123303 MR |
363 | static const struct ti_tscadc_data magdata = { |
364 | .adc_feature_name = "TI-am43xx-adc", | |
365 | .adc_feature_compatible = "ti,am4372-adc", | |
366 | .secondary_feature_name = "TI-am43xx-mag", | |
367 | .secondary_feature_compatible = "ti,am4372-mag", | |
368 | .target_clk_rate = MAG_ADC_CLK, | |
369 | }; | |
370 | ||
a6543a1c | 371 | static const struct of_device_id ti_tscadc_dt_ids[] = { |
f7834843 | 372 | { .compatible = "ti,am3359-tscadc", .data = &tscdata }, |
0a123303 | 373 | { .compatible = "ti,am4372-magadc", .data = &magdata }, |
a6543a1c PR |
374 | { } |
375 | }; | |
376 | MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids); | |
377 | ||
01636eb9 PR |
378 | static struct platform_driver ti_tscadc_driver = { |
379 | .driver = { | |
a6543a1c | 380 | .name = "ti_am3359-tscadc", |
dae936a0 | 381 | .pm = &tscadc_pm_ops, |
131221bc | 382 | .of_match_table = ti_tscadc_dt_ids, |
01636eb9 PR |
383 | }, |
384 | .probe = ti_tscadc_probe, | |
612b95cd | 385 | .remove = ti_tscadc_remove, |
01636eb9 PR |
386 | |
387 | }; | |
388 | ||
389 | module_platform_driver(ti_tscadc_driver); | |
390 | ||
0a123303 | 391 | MODULE_DESCRIPTION("TI touchscreen/magnetic stripe reader/ADC MFD controller driver"); |
01636eb9 PR |
392 | MODULE_AUTHOR("Rachna Patil <rachna@ti.com>"); |
393 | MODULE_LICENSE("GPL"); |