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d6315949 DB |
1 | /* |
2 | * Toshiba TC6393XB SoC support | |
3 | * | |
4 | * Copyright(c) 2005-2006 Chris Humbert | |
5 | * Copyright(c) 2005 Dirk Opfer | |
6 | * Copyright(c) 2005 Ian Molton <spyro@f2s.com> | |
7 | * Copyright(c) 2007 Dmitry Baryshkov | |
8 | * | |
9 | * Based on code written by Sharp/Lineo for 2.4 kernels | |
10 | * Based on locomo.c | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/fb.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/mfd/tc6393xb.h> | |
25 | #include <linux/gpio.h> | |
26 | ||
27 | #define SCR_REVID 0x08 /* b Revision ID */ | |
28 | #define SCR_ISR 0x50 /* b Interrupt Status */ | |
29 | #define SCR_IMR 0x52 /* b Interrupt Mask */ | |
30 | #define SCR_IRR 0x54 /* b Interrupt Routing */ | |
31 | #define SCR_GPER 0x60 /* w GP Enable */ | |
32 | #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ | |
33 | #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ | |
34 | #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ | |
35 | #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ | |
36 | #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ | |
37 | #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ | |
38 | #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ | |
39 | #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ | |
40 | #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ | |
41 | #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ | |
42 | #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ | |
43 | #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ | |
44 | #define SCR_CCR 0x98 /* w Clock Control */ | |
45 | #define SCR_PLL2CR 0x9a /* w PLL2 Control */ | |
46 | #define SCR_PLL1CR 0x9c /* l PLL1 Control */ | |
47 | #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ | |
48 | #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ | |
49 | #define SCR_FER 0xe0 /* b Function Enable */ | |
50 | #define SCR_MCR 0xe4 /* w Mode Control */ | |
51 | #define SCR_CONFIG 0xfc /* b Configuration Control */ | |
52 | #define SCR_DEBUG 0xff /* b Debug */ | |
53 | ||
54 | #define SCR_CCR_CK32K BIT(0) | |
55 | #define SCR_CCR_USBCK BIT(1) | |
56 | #define SCR_CCR_UNK1 BIT(4) | |
57 | #define SCR_CCR_MCLK_MASK (7 << 8) | |
58 | #define SCR_CCR_MCLK_OFF (0 << 8) | |
59 | #define SCR_CCR_MCLK_12 (1 << 8) | |
60 | #define SCR_CCR_MCLK_24 (2 << 8) | |
61 | #define SCR_CCR_MCLK_48 (3 << 8) | |
62 | #define SCR_CCR_HCLK_MASK (3 << 12) | |
63 | #define SCR_CCR_HCLK_24 (0 << 12) | |
64 | #define SCR_CCR_HCLK_48 (1 << 12) | |
65 | ||
66 | #define SCR_FER_USBEN BIT(0) /* USB host enable */ | |
67 | #define SCR_FER_LCDCVEN BIT(1) /* polysilicon TFT enable */ | |
68 | #define SCR_FER_SLCDEN BIT(2) /* SLCD enable */ | |
69 | ||
70 | #define SCR_MCR_RDY_MASK (3 << 0) | |
71 | #define SCR_MCR_RDY_OPENDRAIN (0 << 0) | |
72 | #define SCR_MCR_RDY_TRISTATE (1 << 0) | |
73 | #define SCR_MCR_RDY_PUSHPULL (2 << 0) | |
74 | #define SCR_MCR_RDY_UNK BIT(2) | |
75 | #define SCR_MCR_RDY_EN BIT(3) | |
76 | #define SCR_MCR_INT_MASK (3 << 4) | |
77 | #define SCR_MCR_INT_OPENDRAIN (0 << 4) | |
78 | #define SCR_MCR_INT_TRISTATE (1 << 4) | |
79 | #define SCR_MCR_INT_PUSHPULL (2 << 4) | |
80 | #define SCR_MCR_INT_UNK BIT(6) | |
81 | #define SCR_MCR_INT_EN BIT(7) | |
82 | /* bits 8 - 16 are unknown */ | |
83 | ||
84 | #define TC_GPIO_BIT(i) (1 << (i & 0x7)) | |
85 | ||
86 | /*--------------------------------------------------------------------------*/ | |
87 | ||
88 | struct tc6393xb { | |
89 | void __iomem *scr; | |
90 | ||
91 | struct gpio_chip gpio; | |
92 | ||
93 | struct clk *clk; /* 3,6 Mhz */ | |
94 | ||
95 | spinlock_t lock; /* protects RMW cycles */ | |
96 | ||
97 | struct { | |
98 | u8 fer; | |
99 | u16 ccr; | |
100 | u8 gpi_bcr[3]; | |
101 | u8 gpo_dsr[3]; | |
102 | u8 gpo_doecr[3]; | |
103 | } suspend_state; | |
104 | ||
105 | struct resource rscr; | |
106 | struct resource *iomem; | |
107 | int irq; | |
108 | int irq_base; | |
109 | }; | |
110 | ||
111 | /*--------------------------------------------------------------------------*/ | |
112 | ||
113 | static int tc6393xb_gpio_get(struct gpio_chip *chip, | |
114 | unsigned offset) | |
115 | { | |
116 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
117 | ||
118 | /* XXX: does dsr also represent inputs? */ | |
119 | return ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)) | |
120 | & TC_GPIO_BIT(offset); | |
121 | } | |
122 | ||
123 | static void __tc6393xb_gpio_set(struct gpio_chip *chip, | |
124 | unsigned offset, int value) | |
125 | { | |
126 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
127 | u8 dsr; | |
128 | ||
129 | dsr = ioread8(tc6393xb->scr + SCR_GPO_DSR(offset / 8)); | |
130 | if (value) | |
131 | dsr |= TC_GPIO_BIT(offset); | |
132 | else | |
133 | dsr &= ~TC_GPIO_BIT(offset); | |
134 | ||
135 | iowrite8(dsr, tc6393xb->scr + SCR_GPO_DSR(offset / 8)); | |
136 | } | |
137 | ||
138 | static void tc6393xb_gpio_set(struct gpio_chip *chip, | |
139 | unsigned offset, int value) | |
140 | { | |
141 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
142 | unsigned long flags; | |
143 | ||
144 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
145 | ||
146 | __tc6393xb_gpio_set(chip, offset, value); | |
147 | ||
148 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
149 | } | |
150 | ||
151 | static int tc6393xb_gpio_direction_input(struct gpio_chip *chip, | |
152 | unsigned offset) | |
153 | { | |
154 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
155 | unsigned long flags; | |
156 | u8 doecr; | |
157 | ||
158 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
159 | ||
160 | doecr = ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); | |
161 | doecr &= ~TC_GPIO_BIT(offset); | |
162 | iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); | |
163 | ||
164 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
169 | static int tc6393xb_gpio_direction_output(struct gpio_chip *chip, | |
170 | unsigned offset, int value) | |
171 | { | |
172 | struct tc6393xb *tc6393xb = container_of(chip, struct tc6393xb, gpio); | |
173 | unsigned long flags; | |
174 | u8 doecr; | |
175 | ||
176 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
177 | ||
178 | __tc6393xb_gpio_set(chip, offset, value); | |
179 | ||
180 | doecr = ioread8(tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); | |
181 | doecr |= TC_GPIO_BIT(offset); | |
182 | iowrite8(doecr, tc6393xb->scr + SCR_GPO_DOECR(offset / 8)); | |
183 | ||
184 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
189 | static int tc6393xb_register_gpio(struct tc6393xb *tc6393xb, int gpio_base) | |
190 | { | |
191 | tc6393xb->gpio.label = "tc6393xb"; | |
192 | tc6393xb->gpio.base = gpio_base; | |
193 | tc6393xb->gpio.ngpio = 16; | |
194 | tc6393xb->gpio.set = tc6393xb_gpio_set; | |
195 | tc6393xb->gpio.get = tc6393xb_gpio_get; | |
196 | tc6393xb->gpio.direction_input = tc6393xb_gpio_direction_input; | |
197 | tc6393xb->gpio.direction_output = tc6393xb_gpio_direction_output; | |
198 | ||
199 | return gpiochip_add(&tc6393xb->gpio); | |
200 | } | |
201 | ||
202 | /*--------------------------------------------------------------------------*/ | |
203 | ||
204 | static void | |
205 | tc6393xb_irq(unsigned int irq, struct irq_desc *desc) | |
206 | { | |
207 | struct tc6393xb *tc6393xb = get_irq_data(irq); | |
208 | unsigned int isr; | |
209 | unsigned int i, irq_base; | |
210 | ||
211 | irq_base = tc6393xb->irq_base; | |
212 | ||
213 | while ((isr = ioread8(tc6393xb->scr + SCR_ISR) & | |
214 | ~ioread8(tc6393xb->scr + SCR_IMR))) | |
215 | for (i = 0; i < TC6393XB_NR_IRQS; i++) { | |
216 | if (isr & (1 << i)) | |
217 | generic_handle_irq(irq_base + i); | |
218 | } | |
219 | } | |
220 | ||
221 | static void tc6393xb_irq_ack(unsigned int irq) | |
222 | { | |
223 | } | |
224 | ||
225 | static void tc6393xb_irq_mask(unsigned int irq) | |
226 | { | |
227 | struct tc6393xb *tc6393xb = get_irq_chip_data(irq); | |
228 | unsigned long flags; | |
229 | u8 imr; | |
230 | ||
231 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
232 | imr = ioread8(tc6393xb->scr + SCR_IMR); | |
233 | imr |= 1 << (irq - tc6393xb->irq_base); | |
234 | iowrite8(imr, tc6393xb->scr + SCR_IMR); | |
235 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
236 | } | |
237 | ||
238 | static void tc6393xb_irq_unmask(unsigned int irq) | |
239 | { | |
240 | struct tc6393xb *tc6393xb = get_irq_chip_data(irq); | |
241 | unsigned long flags; | |
242 | u8 imr; | |
243 | ||
244 | spin_lock_irqsave(&tc6393xb->lock, flags); | |
245 | imr = ioread8(tc6393xb->scr + SCR_IMR); | |
246 | imr &= ~(1 << (irq - tc6393xb->irq_base)); | |
247 | iowrite8(imr, tc6393xb->scr + SCR_IMR); | |
248 | spin_unlock_irqrestore(&tc6393xb->lock, flags); | |
249 | } | |
250 | ||
251 | static struct irq_chip tc6393xb_chip = { | |
252 | .name = "tc6393xb", | |
253 | .ack = tc6393xb_irq_ack, | |
254 | .mask = tc6393xb_irq_mask, | |
255 | .unmask = tc6393xb_irq_unmask, | |
256 | }; | |
257 | ||
258 | static void tc6393xb_attach_irq(struct platform_device *dev) | |
259 | { | |
260 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
261 | unsigned int irq, irq_base; | |
262 | ||
263 | irq_base = tc6393xb->irq_base; | |
264 | ||
265 | for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { | |
266 | set_irq_chip(irq, &tc6393xb_chip); | |
267 | set_irq_chip_data(irq, tc6393xb); | |
268 | set_irq_handler(irq, handle_edge_irq); | |
269 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
270 | } | |
271 | ||
272 | set_irq_type(tc6393xb->irq, IRQT_FALLING); | |
273 | set_irq_data(tc6393xb->irq, tc6393xb); | |
274 | set_irq_chained_handler(tc6393xb->irq, tc6393xb_irq); | |
275 | } | |
276 | ||
277 | static void tc6393xb_detach_irq(struct platform_device *dev) | |
278 | { | |
279 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
280 | unsigned int irq, irq_base; | |
281 | ||
282 | set_irq_chained_handler(tc6393xb->irq, NULL); | |
283 | set_irq_data(tc6393xb->irq, NULL); | |
284 | ||
285 | irq_base = tc6393xb->irq_base; | |
286 | ||
287 | for (irq = irq_base; irq < irq_base + TC6393XB_NR_IRQS; irq++) { | |
288 | set_irq_flags(irq, 0); | |
289 | set_irq_chip(irq, NULL); | |
290 | set_irq_chip_data(irq, NULL); | |
291 | } | |
292 | } | |
293 | ||
294 | /*--------------------------------------------------------------------------*/ | |
295 | ||
296 | static int tc6393xb_hw_init(struct platform_device *dev) | |
297 | { | |
298 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
299 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
300 | int i; | |
301 | ||
302 | iowrite8(tc6393xb->suspend_state.fer, tc6393xb->scr + SCR_FER); | |
303 | iowrite16(tcpd->scr_pll2cr, tc6393xb->scr + SCR_PLL2CR); | |
304 | iowrite16(tc6393xb->suspend_state.ccr, tc6393xb->scr + SCR_CCR); | |
305 | iowrite16(SCR_MCR_RDY_OPENDRAIN | SCR_MCR_RDY_UNK | SCR_MCR_RDY_EN | | |
306 | SCR_MCR_INT_OPENDRAIN | SCR_MCR_INT_UNK | SCR_MCR_INT_EN | | |
307 | BIT(15), tc6393xb->scr + SCR_MCR); | |
308 | iowrite16(tcpd->scr_gper, tc6393xb->scr + SCR_GPER); | |
309 | iowrite8(0, tc6393xb->scr + SCR_IRR); | |
310 | iowrite8(0xbf, tc6393xb->scr + SCR_IMR); | |
311 | ||
312 | for (i = 0; i < 3; i++) { | |
313 | iowrite8(tc6393xb->suspend_state.gpo_dsr[i], | |
314 | tc6393xb->scr + SCR_GPO_DSR(i)); | |
315 | iowrite8(tc6393xb->suspend_state.gpo_doecr[i], | |
316 | tc6393xb->scr + SCR_GPO_DOECR(i)); | |
317 | iowrite8(tc6393xb->suspend_state.gpi_bcr[i], | |
318 | tc6393xb->scr + SCR_GPI_BCR(i)); | |
319 | } | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | static int __devinit tc6393xb_probe(struct platform_device *dev) | |
325 | { | |
326 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
327 | struct tc6393xb *tc6393xb; | |
328 | struct resource *iomem; | |
329 | struct resource *rscr; | |
330 | int retval, temp; | |
331 | int i; | |
332 | ||
333 | iomem = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
334 | if (!iomem) | |
335 | return -EINVAL; | |
336 | ||
337 | tc6393xb = kzalloc(sizeof *tc6393xb, GFP_KERNEL); | |
338 | if (!tc6393xb) { | |
339 | retval = -ENOMEM; | |
340 | goto err_kzalloc; | |
341 | } | |
342 | ||
343 | spin_lock_init(&tc6393xb->lock); | |
344 | ||
345 | platform_set_drvdata(dev, tc6393xb); | |
346 | tc6393xb->iomem = iomem; | |
347 | tc6393xb->irq = platform_get_irq(dev, 0); | |
348 | tc6393xb->irq_base = tcpd->irq_base; | |
349 | ||
350 | tc6393xb->clk = clk_get(&dev->dev, "GPIO27_CLK" /* "CK3P6MI" */); | |
351 | if (IS_ERR(tc6393xb->clk)) { | |
352 | retval = PTR_ERR(tc6393xb->clk); | |
353 | goto err_clk_get; | |
354 | } | |
355 | ||
356 | rscr = &tc6393xb->rscr; | |
357 | rscr->name = "tc6393xb-core"; | |
358 | rscr->start = iomem->start; | |
359 | rscr->end = iomem->start + 0xff; | |
360 | rscr->flags = IORESOURCE_MEM; | |
361 | ||
362 | retval = request_resource(iomem, rscr); | |
363 | if (retval) | |
364 | goto err_request_scr; | |
365 | ||
366 | tc6393xb->scr = ioremap(rscr->start, rscr->end - rscr->start + 1); | |
367 | if (!tc6393xb->scr) { | |
368 | retval = -ENOMEM; | |
369 | goto err_ioremap; | |
370 | } | |
371 | ||
372 | retval = clk_enable(tc6393xb->clk); | |
373 | if (retval) | |
374 | goto err_clk_enable; | |
375 | ||
376 | retval = tcpd->enable(dev); | |
377 | if (retval) | |
378 | goto err_enable; | |
379 | ||
380 | tc6393xb->suspend_state.fer = 0; | |
381 | for (i = 0; i < 3; i++) { | |
382 | tc6393xb->suspend_state.gpo_dsr[i] = | |
383 | (tcpd->scr_gpo_dsr >> (8 * i)) & 0xff; | |
384 | tc6393xb->suspend_state.gpo_doecr[i] = | |
385 | (tcpd->scr_gpo_doecr >> (8 * i)) & 0xff; | |
386 | } | |
387 | /* | |
388 | * It may be necessary to change this back to | |
389 | * platform-dependant code | |
390 | */ | |
391 | tc6393xb->suspend_state.ccr = SCR_CCR_UNK1 | | |
392 | SCR_CCR_HCLK_48; | |
393 | ||
394 | retval = tc6393xb_hw_init(dev); | |
395 | if (retval) | |
396 | goto err_hw_init; | |
397 | ||
398 | printk(KERN_INFO "Toshiba tc6393xb revision %d at 0x%08lx, irq %d\n", | |
399 | ioread8(tc6393xb->scr + SCR_REVID), | |
400 | (unsigned long) iomem->start, tc6393xb->irq); | |
401 | ||
402 | tc6393xb->gpio.base = -1; | |
403 | ||
404 | if (tcpd->gpio_base >= 0) { | |
405 | retval = tc6393xb_register_gpio(tc6393xb, tcpd->gpio_base); | |
406 | if (retval) | |
407 | goto err_gpio_add; | |
408 | } | |
409 | ||
410 | if (tc6393xb->irq) | |
411 | tc6393xb_attach_irq(dev); | |
412 | ||
413 | return 0; | |
414 | ||
415 | if (tc6393xb->irq) | |
416 | tc6393xb_detach_irq(dev); | |
417 | ||
418 | err_gpio_add: | |
419 | if (tc6393xb->gpio.base != -1) | |
420 | temp = gpiochip_remove(&tc6393xb->gpio); | |
421 | err_hw_init: | |
422 | tcpd->disable(dev); | |
423 | err_clk_enable: | |
424 | clk_disable(tc6393xb->clk); | |
425 | err_enable: | |
426 | iounmap(tc6393xb->scr); | |
427 | err_ioremap: | |
428 | release_resource(&tc6393xb->rscr); | |
429 | err_request_scr: | |
430 | clk_put(tc6393xb->clk); | |
431 | err_clk_get: | |
432 | kfree(tc6393xb); | |
433 | err_kzalloc: | |
434 | return retval; | |
435 | } | |
436 | ||
437 | static int __devexit tc6393xb_remove(struct platform_device *dev) | |
438 | { | |
439 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
440 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
441 | int ret; | |
442 | ||
443 | if (tc6393xb->irq) | |
444 | tc6393xb_detach_irq(dev); | |
445 | ||
446 | if (tc6393xb->gpio.base != -1) { | |
447 | ret = gpiochip_remove(&tc6393xb->gpio); | |
448 | if (ret) { | |
449 | dev_err(&dev->dev, "Can't remove gpio chip: %d\n", ret); | |
450 | return ret; | |
451 | } | |
452 | } | |
453 | ||
454 | ret = tcpd->disable(dev); | |
455 | ||
456 | clk_disable(tc6393xb->clk); | |
457 | ||
458 | iounmap(tc6393xb->scr); | |
459 | ||
460 | release_resource(&tc6393xb->rscr); | |
461 | ||
462 | platform_set_drvdata(dev, NULL); | |
463 | ||
464 | clk_put(tc6393xb->clk); | |
465 | ||
466 | kfree(tc6393xb); | |
467 | ||
468 | return ret; | |
469 | } | |
470 | ||
471 | #ifdef CONFIG_PM | |
472 | static int tc6393xb_suspend(struct platform_device *dev, pm_message_t state) | |
473 | { | |
474 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
475 | struct tc6393xb *tc6393xb = platform_get_drvdata(dev); | |
476 | int i; | |
477 | ||
478 | ||
479 | tc6393xb->suspend_state.ccr = ioread16(tc6393xb->scr + SCR_CCR); | |
480 | tc6393xb->suspend_state.fer = ioread8(tc6393xb->scr + SCR_FER); | |
481 | ||
482 | for (i = 0; i < 3; i++) { | |
483 | tc6393xb->suspend_state.gpo_dsr[i] = | |
484 | ioread8(tc6393xb->scr + SCR_GPO_DSR(i)); | |
485 | tc6393xb->suspend_state.gpo_doecr[i] = | |
486 | ioread8(tc6393xb->scr + SCR_GPO_DOECR(i)); | |
487 | tc6393xb->suspend_state.gpi_bcr[i] = | |
488 | ioread8(tc6393xb->scr + SCR_GPI_BCR(i)); | |
489 | } | |
490 | ||
491 | return tcpd->suspend(dev); | |
492 | } | |
493 | ||
494 | static int tc6393xb_resume(struct platform_device *dev) | |
495 | { | |
496 | struct tc6393xb_platform_data *tcpd = dev->dev.platform_data; | |
497 | int ret = tcpd->resume(dev); | |
498 | ||
499 | if (ret) | |
500 | return ret; | |
501 | ||
502 | return tc6393xb_hw_init(dev); | |
503 | } | |
504 | #else | |
505 | #define tc6393xb_suspend NULL | |
506 | #define tc6393xb_resume NULL | |
507 | #endif | |
508 | ||
509 | static struct platform_driver tc6393xb_driver = { | |
510 | .probe = tc6393xb_probe, | |
511 | .remove = __devexit_p(tc6393xb_remove), | |
512 | .suspend = tc6393xb_suspend, | |
513 | .resume = tc6393xb_resume, | |
514 | ||
515 | .driver = { | |
516 | .name = "tc6393xb", | |
517 | .owner = THIS_MODULE, | |
518 | }, | |
519 | }; | |
520 | ||
521 | static int __init tc6393xb_init(void) | |
522 | { | |
523 | return platform_driver_register(&tc6393xb_driver); | |
524 | } | |
525 | ||
526 | static void __exit tc6393xb_exit(void) | |
527 | { | |
528 | platform_driver_unregister(&tc6393xb_driver); | |
529 | } | |
530 | ||
531 | subsys_initcall(tc6393xb_init); | |
532 | module_exit(tc6393xb_exit); | |
533 | ||
534 | MODULE_LICENSE("GPL"); | |
535 | MODULE_AUTHOR("Ian Molton, Dmitry Baryshkov and Dirk Opfer"); | |
536 | MODULE_DESCRIPTION("tc6393xb Toshiba Mobile IO Controller"); | |
537 | MODULE_ALIAS("platform:tc6393xb"); |