[linux-2.6-block.git] / drivers / mfd / t7l66xb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 * Toshiba T7L66XB core mfd support
 *
 * Copyright (c) 2005, 2007, 2008 Ian Molton
 * Copyright (c) 2008 Dmitry Baryshkov
 *
 * T7L66 features:
 *
 * Supported in this driver:
 * SD/MMC
 * SM/NAND flash controller
 *
 * As yet not supported
 * GPIO interface (on NAND pins)
 * Serial interface
 * TFT 'interface converter'
 * PCMCIA interface logic
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
#include <linux/mfd/t7l66xb.h>

enum {
	T7L66XB_CELL_NAND,
	T7L66XB_CELL_MMC,
};

static const struct resource t7l66xb_mmc_resources[] = {
	DEFINE_RES_MEM(0x800, 0x200),
	DEFINE_RES_IRQ(IRQ_T7L66XB_MMC)
};

#define SCR_REVID	0x08		/* b Revision ID	*/
#define SCR_IMR		0x42		/* b Interrupt Mask	*/
#define SCR_DEV_CTL	0xe0		/* b Device control	*/
#define SCR_ISR		0xe1		/* b Interrupt Status	*/
#define SCR_GPO_OC	0xf0		/* b GPO output control	*/
#define SCR_GPO_OS	0xf1		/* b GPO output enable	*/
#define SCR_GPI_S	0xf2		/* w GPI status		*/
#define SCR_APDC	0xf8		/* b Active pullup down ctrl */

#define SCR_DEV_CTL_USB		BIT(0)	/* USB enable		*/
#define SCR_DEV_CTL_MMC		BIT(1)	/* MMC enable		*/

/*--------------------------------------------------------------------------*/

struct t7l66xb {
	void __iomem		*scr;
	/* Lock to protect registers requiring read/modify/write ops. */
	raw_spinlock_t		lock;

	struct resource		rscr;
	struct clk		*clk48m;
	struct clk		*clk32k;
	int			irq;
	int			irq_base;
};

/*--------------------------------------------------------------------------*/

static int t7l66xb_mmc_enable(struct platform_device *mmc)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
	unsigned long flags;
	u8 dev_ctl;
	int ret;

	ret = clk_prepare_enable(t7l66xb->clk32k);
	if (ret)
		return ret;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);

	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	dev_ctl |= SCR_DEV_CTL_MMC;
	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);

	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);

	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
		t7l66xb_mmc_resources[0].start & 0xfffe);

	return 0;
}

static int t7l66xb_mmc_disable(struct platform_device *mmc)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
	unsigned long flags;
	u8 dev_ctl;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);

	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	dev_ctl &= ~SCR_DEV_CTL_MMC;
	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);

	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);

	clk_disable_unprepare(t7l66xb->clk32k);

	return 0;
}

static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);

	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
}

static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
{
	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);

	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
}

/*--------------------------------------------------------------------------*/

static struct tmio_mmc_data t7166xb_mmc_data = {
	.hclk = 24000000,
	.set_pwr = t7l66xb_mmc_pwr,
	.set_clk_div = t7l66xb_mmc_clk_div,
};

static const struct resource t7l66xb_nand_resources[] = {
	{
		.start	= 0xc00,
		.end	= 0xc07,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= 0x0100,
		.end	= 0x01ff,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start	= IRQ_T7L66XB_NAND,
		.end	= IRQ_T7L66XB_NAND,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct mfd_cell t7l66xb_cells[] = {
	[T7L66XB_CELL_MMC] = {
		.name = "tmio-mmc",
		.enable = t7l66xb_mmc_enable,
		.disable = t7l66xb_mmc_disable,
		.platform_data = &t7166xb_mmc_data,
		.pdata_size    = sizeof(t7166xb_mmc_data),
		.num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
		.resources = t7l66xb_mmc_resources,
	},
	[T7L66XB_CELL_NAND] = {
		.name = "tmio-nand",
		.num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
		.resources = t7l66xb_nand_resources,
	},
};

/*--------------------------------------------------------------------------*/

/* Handle the T7L66XB interrupt mux */
static void t7l66xb_irq(struct irq_desc *desc)
{
	struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
	unsigned int isr;
	unsigned int i, irq_base;

	irq_base = t7l66xb->irq_base;

	while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
				~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
		for (i = 0; i < T7L66XB_NR_IRQS; i++)
			if (isr & (1 << i))
				generic_handle_irq(irq_base + i);
}

static void t7l66xb_irq_mask(struct irq_data *data)
{
	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
	unsigned long			flags;
	u8 imr;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
	imr |= 1 << (data->irq - t7l66xb->irq_base);
	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}

static void t7l66xb_irq_unmask(struct irq_data *data)
{
	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
	unsigned long flags;
	u8 imr;

	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
	imr &= ~(1 << (data->irq - t7l66xb->irq_base));
	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
}

static struct irq_chip t7l66xb_chip = {
	.name		= "t7l66xb",
	.irq_ack	= t7l66xb_irq_mask,
	.irq_mask	= t7l66xb_irq_mask,
	.irq_unmask	= t7l66xb_irq_unmask,
};

/*--------------------------------------------------------------------------*/

/* Install the IRQ handler */
static void t7l66xb_attach_irq(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	irq_base = t7l66xb->irq_base;

	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
		irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
		irq_set_chip_data(irq, t7l66xb);
	}

	irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
	irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
}

static void t7l66xb_detach_irq(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	unsigned int irq, irq_base;

	irq_base = t7l66xb->irq_base;

	irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);

	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
		irq_set_chip(irq, NULL);
		irq_set_chip_data(irq, NULL);
	}
}

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_PM
static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);

	if (pdata && pdata->suspend)
		pdata->suspend(dev);
	clk_disable_unprepare(t7l66xb->clk48m);

	return 0;
}

static int t7l66xb_resume(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	int ret;

	ret = clk_prepare_enable(t7l66xb->clk48m);
	if (ret)
		return ret;

	if (pdata && pdata->resume)
		pdata->resume(dev);

	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
		t7l66xb_mmc_resources[0].start & 0xfffe);

	return 0;
}
#else
#define t7l66xb_suspend NULL
#define t7l66xb_resume	NULL
#endif

/*--------------------------------------------------------------------------*/

static int t7l66xb_probe(struct platform_device *dev)
{
	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
	struct t7l66xb *t7l66xb;
	struct resource *iomem, *rscr;
	int ret;

	if (!pdata)
		return -EINVAL;

	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!iomem)
		return -EINVAL;

	t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
	if (!t7l66xb)
		return -ENOMEM;

	raw_spin_lock_init(&t7l66xb->lock);

	platform_set_drvdata(dev, t7l66xb);

	ret = platform_get_irq(dev, 0);
	if (ret >= 0)
		t7l66xb->irq = ret;
	else
		goto err_noirq;

	t7l66xb->irq_base = pdata->irq_base;

	t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
	if (IS_ERR(t7l66xb->clk32k)) {
		ret = PTR_ERR(t7l66xb->clk32k);
		goto err_clk32k_get;
	}

	t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
	if (IS_ERR(t7l66xb->clk48m)) {
		ret = PTR_ERR(t7l66xb->clk48m);
		goto err_clk48m_get;
	}

	rscr = &t7l66xb->rscr;
	rscr->name = "t7l66xb-core";
	rscr->start = iomem->start;
	rscr->end = iomem->start + 0xff;
	rscr->flags = IORESOURCE_MEM;

	ret = request_resource(iomem, rscr);
	if (ret)
		goto err_request_scr;

	t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
	if (!t7l66xb->scr) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	ret = clk_prepare_enable(t7l66xb->clk48m);
	if (ret)
		goto err_clk_enable;

	if (pdata->enable)
		pdata->enable(dev);

	/* Mask all interrupts */
	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);

	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
		dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
		(unsigned long)iomem->start, t7l66xb->irq);

	t7l66xb_attach_irq(dev);

	t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
	t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);

	ret = mfd_add_devices(&dev->dev, dev->id,
			      t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
			      iomem, t7l66xb->irq_base, NULL);

	if (!ret)
		return 0;

	t7l66xb_detach_irq(dev);
	clk_disable_unprepare(t7l66xb->clk48m);
err_clk_enable:
	iounmap(t7l66xb->scr);
err_ioremap:
	release_resource(&t7l66xb->rscr);
err_request_scr:
	clk_put(t7l66xb->clk48m);
err_clk48m_get:
	clk_put(t7l66xb->clk32k);
err_clk32k_get:
err_noirq:
	kfree(t7l66xb);
	return ret;
}

static int t7l66xb_remove(struct platform_device *dev)
{
	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);

	clk_disable_unprepare(t7l66xb->clk48m);
	clk_put(t7l66xb->clk48m);
	clk_disable_unprepare(t7l66xb->clk32k);
	clk_put(t7l66xb->clk32k);
	t7l66xb_detach_irq(dev);
	iounmap(t7l66xb->scr);
	release_resource(&t7l66xb->rscr);
	mfd_remove_devices(&dev->dev);
	kfree(t7l66xb);

	return 0;
}

static struct platform_driver t7l66xb_platform_driver = {
	.driver = {
		.name	= "t7l66xb",
	},
	.suspend	= t7l66xb_suspend,
	.resume		= t7l66xb_resume,
	.probe		= t7l66xb_probe,
	.remove		= t7l66xb_remove,
};

/*--------------------------------------------------------------------------*/

module_platform_driver(t7l66xb_platform_driver);

MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Ian Molton");
MODULE_ALIAS("platform:t7l66xb");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1f192015 IM	2	/*
	3	*
	4	* Toshiba T7L66XB core mfd support
	5	*
	6	* Copyright (c) 2005, 2007, 2008 Ian Molton
	7	* Copyright (c) 2008 Dmitry Baryshkov
	8	*
1f192015 IM	9	* T7L66 features:
	10	*
	11	* Supported in this driver:
	12	* SD/MMC
	13	* SM/NAND flash controller
	14	*
	15	* As yet not supported
	16	* GPIO interface (on NAND pins)
	17	* Serial interface
	18	* TFT 'interface converter'
	19	* PCMCIA interface logic
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
7acb706c	24	#include <linux/err.h>
1f192015	25	#include <linux/io.h>
5a0e3ad6	26	#include <linux/slab.h>
1f192015	27	#include <linux/irq.h>
7acb706c	28	#include <linux/clk.h>
1f192015 IM	29	#include <linux/platform_device.h>
	30	#include <linux/mfd/core.h>
	31	#include <linux/mfd/tmio.h>
	32	#include <linux/mfd/t7l66xb.h>
	33
	34	enum {
	35	T7L66XB_CELL_NAND,
	36	T7L66XB_CELL_MMC,
	37	};
	38
64e8867b	39	static const struct resource t7l66xb_mmc_resources[] = {
81a22c33 ZL	40	DEFINE_RES_MEM(0x800, 0x200),
81a22c33 ZL	41	DEFINE_RES_IRQ(IRQ_T7L66XB_MMC)
64e8867b IM	42	};
64e8867b IM	43
1f192015 IM	44	#define SCR_REVID 0x08 /* b Revision ID */
	45	#define SCR_IMR 0x42 /* b Interrupt Mask */
	46	#define SCR_DEV_CTL 0xe0 /* b Device control */
	47	#define SCR_ISR 0xe1 /* b Interrupt Status */
	48	#define SCR_GPO_OC 0xf0 /* b GPO output control */
	49	#define SCR_GPO_OS 0xf1 /* b GPO output enable */
	50	#define SCR_GPI_S 0xf2 /* w GPI status */
	51	#define SCR_APDC 0xf8 /* b Active pullup down ctrl */
	52
	53	#define SCR_DEV_CTL_USB BIT(0) /* USB enable */
	54	#define SCR_DEV_CTL_MMC BIT(1) /* MMC enable */
	55
	56	/--------------------------------------------------------------------------/
	57
	58	struct t7l66xb {
	59	void __iomem *scr;
	60	/* Lock to protect registers requiring read/modify/write ops. */
9fe8c2df	61	raw_spinlock_t lock;
1f192015 IM	62
1f192015 IM	63	struct resource rscr;
7acb706c IM	64	struct clk *clk48m;
7acb706c IM	65	struct clk *clk32k;
1f192015 IM	66	int irq;
	67	int irq_base;
	68	};
	69
	70	/--------------------------------------------------------------------------/
	71
	72	static int t7l66xb_mmc_enable(struct platform_device *mmc)
	73	{
ed835136	74	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
1f192015 IM	75	unsigned long flags;
1f192015 IM	76	u8 dev_ctl;
b62d8dbe	77	int ret;
1f192015	78
b62d8dbe AY	79	ret = clk_prepare_enable(t7l66xb->clk32k);
	80	if (ret)
	81	return ret;
1f192015	82
9fe8c2df	83	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015 IM	84
	85	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	86	dev_ctl \|= SCR_DEV_CTL_MMC;
	87	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
	88
9fe8c2df	89	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015	90
64e8867b IM	91	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
	92	t7l66xb_mmc_resources[0].start & 0xfffe);
	93
1f192015 IM	94	return 0;
	95	}
	96
	97	static int t7l66xb_mmc_disable(struct platform_device *mmc)
	98	{
ed835136	99	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
1f192015 IM	100	unsigned long flags;
	101	u8 dev_ctl;
	102
9fe8c2df	103	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015 IM	104
	105	dev_ctl = tmio_ioread8(t7l66xb->scr + SCR_DEV_CTL);
	106	dev_ctl &= ~SCR_DEV_CTL_MMC;
	107	tmio_iowrite8(dev_ctl, t7l66xb->scr + SCR_DEV_CTL);
	108
9fe8c2df	109	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015	110
71d679b8	111	clk_disable_unprepare(t7l66xb->clk32k);
1f192015 IM	112
	113	return 0;
	114	}
	115
64e8867b IM	116	static void t7l66xb_mmc_pwr(struct platform_device *mmc, int state)
64e8867b IM	117	{
ed835136	118	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
64e8867b IM	119
	120	tmio_core_mmc_pwr(t7l66xb->scr + 0x200, 0, state);
	121	}
	122
	123	static void t7l66xb_mmc_clk_div(struct platform_device *mmc, int state)
	124	{
ed835136	125	struct t7l66xb *t7l66xb = dev_get_drvdata(mmc->dev.parent);
64e8867b IM	126
	127	tmio_core_mmc_clk_div(t7l66xb->scr + 0x200, 0, state);
	128	}
	129
1f192015 IM	130	/--------------------------------------------------------------------------/
1f192015 IM	131
4d3792e0	132	static struct tmio_mmc_data t7166xb_mmc_data = {
f0e46cc4	133	.hclk = 24000000,
64e8867b IM	134	.set_pwr = t7l66xb_mmc_pwr,
64e8867b IM	135	.set_clk_div = t7l66xb_mmc_clk_div,
1f192015 IM	136	};
1f192015 IM	137
3446d4bb	138	static const struct resource t7l66xb_nand_resources[] = {
1f192015 IM	139	{
	140	.start = 0xc00,
	141	.end = 0xc07,
	142	.flags = IORESOURCE_MEM,
	143	},
	144	{
	145	.start = 0x0100,
	146	.end = 0x01ff,
	147	.flags = IORESOURCE_MEM,
	148	},
	149	{
	150	.start = IRQ_T7L66XB_NAND,
	151	.end = IRQ_T7L66XB_NAND,
	152	.flags = IORESOURCE_IRQ,
	153	},
	154	};
	155
	156	static struct mfd_cell t7l66xb_cells[] = {
	157	[T7L66XB_CELL_MMC] = {
	158	.name = "tmio-mmc",
	159	.enable = t7l66xb_mmc_enable,
	160	.disable = t7l66xb_mmc_disable,
ec71974f SO	161	.platform_data = &t7166xb_mmc_data,
ec71974f SO	162	.pdata_size = sizeof(t7166xb_mmc_data),
1f192015 IM	163	.num_resources = ARRAY_SIZE(t7l66xb_mmc_resources),
	164	.resources = t7l66xb_mmc_resources,
	165	},
	166	[T7L66XB_CELL_NAND] = {
	167	.name = "tmio-nand",
	168	.num_resources = ARRAY_SIZE(t7l66xb_nand_resources),
	169	.resources = t7l66xb_nand_resources,
	170	},
	171	};
	172
	173	/--------------------------------------------------------------------------/
	174
	175	/* Handle the T7L66XB interrupt mux */
bd0b9ac4	176	static void t7l66xb_irq(struct irq_desc *desc)
1f192015	177	{
1e84aa44	178	struct t7l66xb *t7l66xb = irq_desc_get_handler_data(desc);
1f192015 IM	179	unsigned int isr;
	180	unsigned int i, irq_base;
	181
	182	irq_base = t7l66xb->irq_base;
	183
	184	while ((isr = tmio_ioread8(t7l66xb->scr + SCR_ISR) &
	185	~tmio_ioread8(t7l66xb->scr + SCR_IMR)))
	186	for (i = 0; i < T7L66XB_NR_IRQS; i++)
	187	if (isr & (1 << i))
	188	generic_handle_irq(irq_base + i);
	189	}
	190
a4e7fead	191	static void t7l66xb_irq_mask(struct irq_data *data)
1f192015	192	{
a4e7fead	193	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
1f192015 IM	194	unsigned long flags;
	195	u8 imr;
	196
9fe8c2df	197	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015	198	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
a4e7fead	199	imr \|= 1 << (data->irq - t7l66xb->irq_base);
1f192015	200	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
9fe8c2df	201	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015 IM	202	}
1f192015 IM	203
a4e7fead	204	static void t7l66xb_irq_unmask(struct irq_data *data)
1f192015	205	{
a4e7fead	206	struct t7l66xb *t7l66xb = irq_data_get_irq_chip_data(data);
1f192015 IM	207	unsigned long flags;
	208	u8 imr;
	209
9fe8c2df	210	raw_spin_lock_irqsave(&t7l66xb->lock, flags);
1f192015	211	imr = tmio_ioread8(t7l66xb->scr + SCR_IMR);
a4e7fead	212	imr &= ~(1 << (data->irq - t7l66xb->irq_base));
1f192015	213	tmio_iowrite8(imr, t7l66xb->scr + SCR_IMR);
9fe8c2df	214	raw_spin_unlock_irqrestore(&t7l66xb->lock, flags);
1f192015 IM	215	}
	216
	217	static struct irq_chip t7l66xb_chip = {
a4e7fead MB	218	.name = "t7l66xb",
	219	.irq_ack = t7l66xb_irq_mask,
	220	.irq_mask = t7l66xb_irq_mask,
	221	.irq_unmask = t7l66xb_irq_unmask,
1f192015 IM	222	};
	223
	224	/--------------------------------------------------------------------------/
	225
	226	/* Install the IRQ handler */
	227	static void t7l66xb_attach_irq(struct platform_device *dev)
	228	{
	229	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	230	unsigned int irq, irq_base;
	231
	232	irq_base = t7l66xb->irq_base;
	233
	234	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
d6f7ce9f	235	irq_set_chip_and_handler(irq, &t7l66xb_chip, handle_level_irq);
d5bb1221	236	irq_set_chip_data(irq, t7l66xb);
1f192015 IM	237	}
1f192015 IM	238
d5bb1221	239	irq_set_irq_type(t7l66xb->irq, IRQ_TYPE_EDGE_FALLING);
de7c9e0d	240	irq_set_chained_handler_and_data(t7l66xb->irq, t7l66xb_irq, t7l66xb);
1f192015 IM	241	}
	242
	243	static void t7l66xb_detach_irq(struct platform_device *dev)
	244	{
	245	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
	246	unsigned int irq, irq_base;
	247
	248	irq_base = t7l66xb->irq_base;
	249
de7c9e0d	250	irq_set_chained_handler_and_data(t7l66xb->irq, NULL, NULL);
1f192015 IM	251
1f192015 IM	252	for (irq = irq_base; irq < irq_base + T7L66XB_NR_IRQS; irq++) {
d5bb1221 TG	253	irq_set_chip(irq, NULL);
d5bb1221 TG	254	irq_set_chip_data(irq, NULL);
1f192015 IM	255	}
	256	}
	257
	258	/--------------------------------------------------------------------------/
	259
	260	#ifdef CONFIG_PM
	261	static int t7l66xb_suspend(struct platform_device *dev, pm_message_t state)
	262	{
7acb706c	263	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
334a41ce	264	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	265
	266	if (pdata && pdata->suspend)
	267	pdata->suspend(dev);
71d679b8	268	clk_disable_unprepare(t7l66xb->clk48m);
1f192015 IM	269
	270	return 0;
	271	}
	272
	273	static int t7l66xb_resume(struct platform_device *dev)
	274	{
7acb706c	275	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
334a41ce	276	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
b62d8dbe AY	277	int ret;
	278
	279	ret = clk_prepare_enable(t7l66xb->clk48m);
	280	if (ret)
	281	return ret;
1f192015 IM	282
	283	if (pdata && pdata->resume)
	284	pdata->resume(dev);
	285
64e8867b IM	286	tmio_core_mmc_enable(t7l66xb->scr + 0x200, 0,
	287	t7l66xb_mmc_resources[0].start & 0xfffe);
	288
1f192015 IM	289	return 0;
	290	}
	291	#else
	292	#define t7l66xb_suspend NULL
	293	#define t7l66xb_resume NULL
	294	#endif
	295
	296	/--------------------------------------------------------------------------/
	297
	298	static int t7l66xb_probe(struct platform_device *dev)
	299	{
334a41ce	300	struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
1f192015 IM	301	struct t7l66xb *t7l66xb;
	302	struct resource iomem, rscr;
	303	int ret;
	304
78b7d84c	305	if (!pdata)
9ad285d6 SO	306	return -EINVAL;
9ad285d6 SO	307
1f192015 IM	308	iomem = platform_get_resource(dev, IORESOURCE_MEM, 0);
	309	if (!iomem)
	310	return -EINVAL;
	311
	312	t7l66xb = kzalloc(sizeof *t7l66xb, GFP_KERNEL);
	313	if (!t7l66xb)
	314	return -ENOMEM;
	315
9fe8c2df	316	raw_spin_lock_init(&t7l66xb->lock);
1f192015 IM	317
	318	platform_set_drvdata(dev, t7l66xb);
	319
	320	ret = platform_get_irq(dev, 0);
	321	if (ret >= 0)
	322	t7l66xb->irq = ret;
	323	else
	324	goto err_noirq;
	325
	326	t7l66xb->irq_base = pdata->irq_base;
	327
7acb706c IM	328	t7l66xb->clk32k = clk_get(&dev->dev, "CLK_CK32K");
	329	if (IS_ERR(t7l66xb->clk32k)) {
	330	ret = PTR_ERR(t7l66xb->clk32k);
	331	goto err_clk32k_get;
	332	}
	333
	334	t7l66xb->clk48m = clk_get(&dev->dev, "CLK_CK48M");
	335	if (IS_ERR(t7l66xb->clk48m)) {
	336	ret = PTR_ERR(t7l66xb->clk48m);
7acb706c IM	337	goto err_clk48m_get;
	338	}
	339
1f192015 IM	340	rscr = &t7l66xb->rscr;
	341	rscr->name = "t7l66xb-core";
	342	rscr->start = iomem->start;
	343	rscr->end = iomem->start + 0xff;
	344	rscr->flags = IORESOURCE_MEM;
	345
	346	ret = request_resource(iomem, rscr);
	347	if (ret)
	348	goto err_request_scr;
	349
c02e6a5f	350	t7l66xb->scr = ioremap(rscr->start, resource_size(rscr));
1f192015 IM	351	if (!t7l66xb->scr) {
	352	ret = -ENOMEM;
	353	goto err_ioremap;
	354	}
	355
b62d8dbe AY	356	ret = clk_prepare_enable(t7l66xb->clk48m);
	357	if (ret)
	358	goto err_clk_enable;
7acb706c	359
78b7d84c	360	if (pdata->enable)
1f192015 IM	361	pdata->enable(dev);
	362
	363	/* Mask all interrupts */
	364	tmio_iowrite8(0xbf, t7l66xb->scr + SCR_IMR);
	365
	366	printk(KERN_INFO "%s rev %d @ 0x%08lx, irq %d\n",
	367	dev->name, tmio_ioread8(t7l66xb->scr + SCR_REVID),
	368	(unsigned long)iomem->start, t7l66xb->irq);
	369
	370	t7l66xb_attach_irq(dev);
	371
7dc00a0d SO	372	t7l66xb_cells[T7L66XB_CELL_NAND].platform_data = pdata->nand_data;
7dc00a0d SO	373	t7l66xb_cells[T7L66XB_CELL_NAND].pdata_size = sizeof(*pdata->nand_data);
8a4fbe01	374
56bf2bda SO	375	ret = mfd_add_devices(&dev->dev, dev->id,
56bf2bda SO	376	t7l66xb_cells, ARRAY_SIZE(t7l66xb_cells),
0848c94f	377	iomem, t7l66xb->irq_base, NULL);
1f192015 IM	378
	379	if (!ret)
	380	return 0;
	381
	382	t7l66xb_detach_irq(dev);
b62d8dbe AY	383	clk_disable_unprepare(t7l66xb->clk48m);
b62d8dbe AY	384	err_clk_enable:
1f192015 IM	385	iounmap(t7l66xb->scr);
	386	err_ioremap:
	387	release_resource(&t7l66xb->rscr);
1f192015	388	err_request_scr:
7acb706c IM	389	clk_put(t7l66xb->clk48m);
	390	err_clk48m_get:
	391	clk_put(t7l66xb->clk32k);
	392	err_clk32k_get:
	393	err_noirq:
0e820ab6	394	kfree(t7l66xb);
1f192015 IM	395	return ret;
	396	}
	397
	398	static int t7l66xb_remove(struct platform_device *dev)
	399	{
1f192015	400	struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
1f192015	401
71d679b8	402	clk_disable_unprepare(t7l66xb->clk48m);
7acb706c	403	clk_put(t7l66xb->clk48m);
71d679b8	404	clk_disable_unprepare(t7l66xb->clk32k);
d2d272a9	405	clk_put(t7l66xb->clk32k);
1f192015 IM	406	t7l66xb_detach_irq(dev);
	407	iounmap(t7l66xb->scr);
	408	release_resource(&t7l66xb->rscr);
56bf2bda	409	mfd_remove_devices(&dev->dev);
1f192015 IM	410	kfree(t7l66xb);
1f192015 IM	411
128ac294	412	return 0;
1f192015 IM	413	}
	414
	415	static struct platform_driver t7l66xb_platform_driver = {
	416	.driver = {
	417	.name = "t7l66xb",
1f192015 IM	418	},
	419	.suspend = t7l66xb_suspend,
	420	.resume = t7l66xb_resume,
	421	.probe = t7l66xb_probe,
	422	.remove = t7l66xb_remove,
	423	};
	424
	425	/--------------------------------------------------------------------------/
	426
65349d60	427	module_platform_driver(t7l66xb_platform_driver);
1f192015 IM	428
	429	MODULE_DESCRIPTION("Toshiba T7L66XB core driver");
	430	MODULE_LICENSE("GPL v2");
	431	MODULE_AUTHOR("Ian Molton");
	432	MODULE_ALIAS("platform:t7l66xb");