Commit | Line | Data |
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35bdd290 | 1 | /* |
cf090914 PG |
2 | * STA2x11 mfd for GPIO, SCTL and APBREG |
3 | * | |
35bdd290 | 4 | * Copyright (c) 2009-2011 Wind River Systems, Inc. |
b73df698 | 5 | * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi) |
35bdd290 AR |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
14 | * See the GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
cf090914 PG |
23 | #include <linux/init.h> |
24 | #include <linux/export.h> | |
35bdd290 AR |
25 | #include <linux/spinlock.h> |
26 | #include <linux/errno.h> | |
27 | #include <linux/device.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/list.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/pci.h> | |
35bdd290 AR |
33 | #include <linux/seq_file.h> |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/mfd/core.h> | |
36 | #include <linux/mfd/sta2x11-mfd.h> | |
d94e2553 | 37 | #include <linux/regmap.h> |
35bdd290 AR |
38 | |
39 | #include <asm/sta2x11.h> | |
40 | ||
d94e2553 DC |
41 | static inline int __reg_within_range(unsigned int r, |
42 | unsigned int start, | |
43 | unsigned int end) | |
44 | { | |
45 | return ((r >= start) && (r <= end)); | |
46 | } | |
47 | ||
35bdd290 AR |
48 | /* This describes STA2X11 MFD chip for us, we may have several */ |
49 | struct sta2x11_mfd { | |
50 | struct sta2x11_instance *instance; | |
d94e2553 | 51 | struct regmap *regmap[sta2x11_n_mfd_plat_devs]; |
e885ba29 | 52 | spinlock_t lock[sta2x11_n_mfd_plat_devs]; |
35bdd290 | 53 | struct list_head list; |
1950c716 | 54 | void __iomem *regs[sta2x11_n_mfd_plat_devs]; |
35bdd290 AR |
55 | }; |
56 | ||
57 | static LIST_HEAD(sta2x11_mfd_list); | |
58 | ||
59 | /* Three functions to act on the list */ | |
60 | static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev) | |
61 | { | |
62 | struct sta2x11_instance *instance; | |
63 | struct sta2x11_mfd *mfd; | |
64 | ||
65 | if (!pdev && !list_empty(&sta2x11_mfd_list)) { | |
81d30eda JP |
66 | pr_warn("%s: Unspecified device, using first instance\n", |
67 | __func__); | |
35bdd290 AR |
68 | return list_entry(sta2x11_mfd_list.next, |
69 | struct sta2x11_mfd, list); | |
70 | } | |
71 | ||
72 | instance = sta2x11_get_instance(pdev); | |
73 | if (!instance) | |
74 | return NULL; | |
75 | list_for_each_entry(mfd, &sta2x11_mfd_list, list) { | |
76 | if (mfd->instance == instance) | |
77 | return mfd; | |
78 | } | |
79 | return NULL; | |
80 | } | |
81 | ||
f791be49 | 82 | static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags) |
35bdd290 | 83 | { |
e885ba29 | 84 | int i; |
35bdd290 AR |
85 | struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev); |
86 | struct sta2x11_instance *instance; | |
87 | ||
88 | if (mfd) | |
89 | return -EBUSY; | |
90 | instance = sta2x11_get_instance(pdev); | |
91 | if (!instance) | |
92 | return -EINVAL; | |
93 | mfd = kzalloc(sizeof(*mfd), flags); | |
94 | if (!mfd) | |
95 | return -ENOMEM; | |
96 | INIT_LIST_HEAD(&mfd->list); | |
e885ba29 DC |
97 | for (i = 0; i < ARRAY_SIZE(mfd->lock); i++) |
98 | spin_lock_init(&mfd->lock[i]); | |
35bdd290 AR |
99 | mfd->instance = instance; |
100 | list_add(&mfd->list, &sta2x11_mfd_list); | |
101 | return 0; | |
102 | } | |
103 | ||
1950c716 DC |
104 | /* This function is exported and is not expected to fail */ |
105 | u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val, | |
106 | enum sta2x11_mfd_plat_dev index) | |
35bdd290 AR |
107 | { |
108 | struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev); | |
109 | u32 r; | |
110 | unsigned long flags; | |
709edecd | 111 | void __iomem *regs; |
35bdd290 AR |
112 | |
113 | if (!mfd) { | |
114 | dev_warn(&pdev->dev, ": can't access sctl regs\n"); | |
115 | return 0; | |
116 | } | |
709edecd WY |
117 | |
118 | regs = mfd->regs[index]; | |
1950c716 | 119 | if (!regs) { |
35bdd290 AR |
120 | dev_warn(&pdev->dev, ": system ctl not initialized\n"); |
121 | return 0; | |
122 | } | |
e885ba29 | 123 | spin_lock_irqsave(&mfd->lock[index], flags); |
1950c716 | 124 | r = readl(regs + reg); |
35bdd290 AR |
125 | r &= ~mask; |
126 | r |= val; | |
127 | if (mask) | |
1950c716 | 128 | writel(r, regs + reg); |
e885ba29 | 129 | spin_unlock_irqrestore(&mfd->lock[index], flags); |
35bdd290 AR |
130 | return r; |
131 | } | |
1950c716 | 132 | EXPORT_SYMBOL(__sta2x11_mfd_mask); |
35bdd290 | 133 | |
29f5b5a3 DC |
134 | int sta2x11_mfd_get_regs_data(struct platform_device *dev, |
135 | enum sta2x11_mfd_plat_dev index, | |
136 | void __iomem **regs, | |
137 | spinlock_t **lock) | |
35bdd290 | 138 | { |
334a41ce | 139 | struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev); |
29f5b5a3 | 140 | struct sta2x11_mfd *mfd; |
35bdd290 | 141 | |
29f5b5a3 DC |
142 | if (!pdev) |
143 | return -ENODEV; | |
144 | mfd = sta2x11_mfd_find(pdev); | |
145 | if (!mfd) | |
146 | return -ENODEV; | |
147 | if (index >= sta2x11_n_mfd_plat_devs) | |
148 | return -ENODEV; | |
149 | *regs = mfd->regs[index]; | |
150 | *lock = &mfd->lock[index]; | |
151 | pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs); | |
152 | return *regs ? 0 : -ENODEV; | |
35bdd290 | 153 | } |
29f5b5a3 | 154 | EXPORT_SYMBOL(sta2x11_mfd_get_regs_data); |
35bdd290 | 155 | |
d94e2553 DC |
156 | /* |
157 | * Special sta2x11-mfd regmap lock/unlock functions | |
158 | */ | |
35bdd290 | 159 | |
d94e2553 DC |
160 | static void sta2x11_regmap_lock(void *__lock) |
161 | { | |
162 | spinlock_t *lock = __lock; | |
163 | spin_lock(lock); | |
164 | } | |
35bdd290 | 165 | |
d94e2553 DC |
166 | static void sta2x11_regmap_unlock(void *__lock) |
167 | { | |
168 | spinlock_t *lock = __lock; | |
169 | spin_unlock(lock); | |
170 | } | |
35bdd290 | 171 | |
dba6c1ae DC |
172 | /* OTP (one time programmable registers do not require locking */ |
173 | static void sta2x11_regmap_nolock(void *__lock) | |
174 | { | |
175 | } | |
176 | ||
d94e2553 | 177 | static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = { |
b18adafc DC |
178 | [sta2x11_sctl] = STA2X11_MFD_SCTL_NAME, |
179 | [sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME, | |
180 | [sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME, | |
dba6c1ae | 181 | [sta2x11_scr] = STA2X11_MFD_SCR_NAME, |
35bdd290 | 182 | }; |
35bdd290 | 183 | |
d94e2553 DC |
184 | static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg) |
185 | { | |
186 | return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA); | |
187 | } | |
188 | ||
189 | static struct regmap_config sta2x11_sctl_regmap_config = { | |
190 | .reg_bits = 32, | |
191 | .reg_stride = 4, | |
192 | .val_bits = 32, | |
193 | .lock = sta2x11_regmap_lock, | |
194 | .unlock = sta2x11_regmap_unlock, | |
195 | .max_register = SCTL_SCRSTSTA, | |
196 | .writeable_reg = sta2x11_sctl_writeable_reg, | |
35bdd290 AR |
197 | }; |
198 | ||
dba6c1ae DC |
199 | static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg) |
200 | { | |
201 | return (reg == STA2X11_SECR_CR) || | |
202 | __reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1); | |
203 | } | |
35bdd290 | 204 | |
dba6c1ae | 205 | static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg) |
35bdd290 | 206 | { |
dba6c1ae DC |
207 | return false; |
208 | } | |
35bdd290 | 209 | |
dba6c1ae DC |
210 | static struct regmap_config sta2x11_scr_regmap_config = { |
211 | .reg_bits = 32, | |
212 | .reg_stride = 4, | |
213 | .val_bits = 32, | |
214 | .lock = sta2x11_regmap_nolock, | |
215 | .unlock = sta2x11_regmap_nolock, | |
216 | .max_register = STA2X11_SECR_FVR1, | |
217 | .readable_reg = sta2x11_scr_readable_reg, | |
218 | .writeable_reg = sta2x11_scr_writeable_reg, | |
219 | }; | |
35bdd290 | 220 | |
d94e2553 DC |
221 | static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg) |
222 | { | |
223 | /* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */ | |
224 | if (reg >= APBREG_BSR_SARAC) | |
225 | reg -= APBREG_BSR_SARAC; | |
226 | switch (reg) { | |
227 | case APBREG_BSR: | |
228 | case APBREG_PAER: | |
229 | case APBREG_PWAC: | |
230 | case APBREG_PRAC: | |
231 | case APBREG_PCG: | |
232 | case APBREG_PUR: | |
233 | case APBREG_EMU_PCG: | |
234 | return true; | |
235 | default: | |
236 | return false; | |
237 | } | |
238 | } | |
35bdd290 | 239 | |
d94e2553 DC |
240 | static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg) |
241 | { | |
242 | if (reg >= APBREG_BSR_SARAC) | |
243 | reg -= APBREG_BSR_SARAC; | |
244 | if (!sta2x11_apbreg_readable_reg(dev, reg)) | |
245 | return false; | |
246 | return reg != APBREG_PAER; | |
247 | } | |
35bdd290 | 248 | |
d94e2553 DC |
249 | static struct regmap_config sta2x11_apbreg_regmap_config = { |
250 | .reg_bits = 32, | |
251 | .reg_stride = 4, | |
252 | .val_bits = 32, | |
253 | .lock = sta2x11_regmap_lock, | |
254 | .unlock = sta2x11_regmap_unlock, | |
255 | .max_register = APBREG_EMU_PCG_SARAC, | |
256 | .readable_reg = sta2x11_apbreg_readable_reg, | |
257 | .writeable_reg = sta2x11_apbreg_writeable_reg, | |
1950c716 | 258 | }; |
35bdd290 | 259 | |
d94e2553 DC |
260 | static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev, |
261 | unsigned int reg) | |
262 | { | |
263 | return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG || | |
264 | __reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) || | |
265 | __reg_within_range(reg, MASTER_LOCK_REG, | |
266 | SYSTEM_CONFIG_STATUS_REG) || | |
267 | reg == MSP_CLK_CTRL_REG || | |
268 | __reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG); | |
269 | } | |
35bdd290 | 270 | |
d94e2553 DC |
271 | static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev, |
272 | unsigned int reg) | |
273 | { | |
274 | if (!sta2x11_apb_soc_regs_readable_reg(dev, reg)) | |
275 | return false; | |
276 | switch (reg) { | |
277 | case PCIE_COMMON_CLOCK_CONFIG_0_4_0: | |
278 | case SYSTEM_CONFIG_STATUS_REG: | |
279 | case COMPENSATION_REG1: | |
280 | case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG: | |
281 | case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4: | |
282 | return false; | |
283 | default: | |
284 | return true; | |
35bdd290 | 285 | } |
35bdd290 AR |
286 | } |
287 | ||
d94e2553 DC |
288 | static struct regmap_config sta2x11_apb_soc_regs_regmap_config = { |
289 | .reg_bits = 32, | |
290 | .reg_stride = 4, | |
291 | .val_bits = 32, | |
292 | .lock = sta2x11_regmap_lock, | |
293 | .unlock = sta2x11_regmap_unlock, | |
294 | .max_register = TEST_CTL_REG, | |
295 | .readable_reg = sta2x11_apb_soc_regs_readable_reg, | |
296 | .writeable_reg = sta2x11_apb_soc_regs_writeable_reg, | |
1950c716 | 297 | }; |
35bdd290 | 298 | |
d94e2553 DC |
299 | static struct regmap_config * |
300 | sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = { | |
301 | [sta2x11_sctl] = &sta2x11_sctl_regmap_config, | |
302 | [sta2x11_apbreg] = &sta2x11_apbreg_regmap_config, | |
303 | [sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config, | |
dba6c1ae | 304 | [sta2x11_scr] = &sta2x11_scr_regmap_config, |
1950c716 | 305 | }; |
35bdd290 | 306 | |
dba6c1ae | 307 | /* Probe for the four platform devices */ |
1950c716 DC |
308 | |
309 | static int sta2x11_mfd_platform_probe(struct platform_device *dev, | |
310 | enum sta2x11_mfd_plat_dev index) | |
35bdd290 AR |
311 | { |
312 | struct pci_dev **pdev; | |
313 | struct sta2x11_mfd *mfd; | |
314 | struct resource *res; | |
1950c716 | 315 | const char *name = sta2x11_mfd_names[index]; |
d94e2553 | 316 | struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index]; |
35bdd290 | 317 | |
334a41ce | 318 | pdev = dev_get_platdata(&dev->dev); |
35bdd290 AR |
319 | mfd = sta2x11_mfd_find(*pdev); |
320 | if (!mfd) | |
321 | return -ENODEV; | |
d94e2553 DC |
322 | if (!regmap_config) |
323 | return -ENODEV; | |
35bdd290 AR |
324 | |
325 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
326 | if (!res) | |
327 | return -ENOMEM; | |
328 | ||
1950c716 | 329 | if (!request_mem_region(res->start, resource_size(res), name)) |
35bdd290 AR |
330 | return -EBUSY; |
331 | ||
1950c716 DC |
332 | mfd->regs[index] = ioremap(res->start, resource_size(res)); |
333 | if (!mfd->regs[index]) { | |
35bdd290 AR |
334 | release_mem_region(res->start, resource_size(res)); |
335 | return -ENOMEM; | |
336 | } | |
d94e2553 DC |
337 | regmap_config->lock_arg = &mfd->lock; |
338 | /* | |
339 | No caching, registers could be reached both via regmap and via | |
340 | void __iomem * | |
341 | */ | |
342 | regmap_config->cache_type = REGCACHE_NONE; | |
343 | mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index], | |
344 | regmap_config); | |
ec9e4ba6 | 345 | WARN_ON(IS_ERR(mfd->regmap[index])); |
35bdd290 | 346 | |
35bdd290 AR |
347 | return 0; |
348 | } | |
349 | ||
1950c716 DC |
350 | static int sta2x11_sctl_probe(struct platform_device *dev) |
351 | { | |
352 | return sta2x11_mfd_platform_probe(dev, sta2x11_sctl); | |
353 | } | |
354 | ||
355 | static int sta2x11_apbreg_probe(struct platform_device *dev) | |
356 | { | |
357 | return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg); | |
358 | } | |
359 | ||
360 | static int sta2x11_apb_soc_regs_probe(struct platform_device *dev) | |
361 | { | |
362 | return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs); | |
363 | } | |
364 | ||
dba6c1ae DC |
365 | static int sta2x11_scr_probe(struct platform_device *dev) |
366 | { | |
367 | return sta2x11_mfd_platform_probe(dev, sta2x11_scr); | |
368 | } | |
369 | ||
1950c716 | 370 | /* The three platform drivers */ |
35bdd290 AR |
371 | static struct platform_driver sta2x11_sctl_platform_driver = { |
372 | .driver = { | |
b18adafc | 373 | .name = STA2X11_MFD_SCTL_NAME, |
35bdd290 AR |
374 | }, |
375 | .probe = sta2x11_sctl_probe, | |
376 | }; | |
377 | ||
35bdd290 AR |
378 | static struct platform_driver sta2x11_platform_driver = { |
379 | .driver = { | |
b18adafc | 380 | .name = STA2X11_MFD_APBREG_NAME, |
35bdd290 AR |
381 | }, |
382 | .probe = sta2x11_apbreg_probe, | |
383 | }; | |
384 | ||
1950c716 DC |
385 | static struct platform_driver sta2x11_apb_soc_regs_platform_driver = { |
386 | .driver = { | |
b18adafc | 387 | .name = STA2X11_MFD_APB_SOC_REGS_NAME, |
1950c716 DC |
388 | }, |
389 | .probe = sta2x11_apb_soc_regs_probe, | |
390 | }; | |
391 | ||
dba6c1ae DC |
392 | static struct platform_driver sta2x11_scr_platform_driver = { |
393 | .driver = { | |
394 | .name = STA2X11_MFD_SCR_NAME, | |
dba6c1ae DC |
395 | }, |
396 | .probe = sta2x11_scr_probe, | |
397 | }; | |
398 | ||
d91d76d8 TR |
399 | static struct platform_driver * const drivers[] = { |
400 | &sta2x11_platform_driver, | |
401 | &sta2x11_sctl_platform_driver, | |
402 | &sta2x11_apb_soc_regs_platform_driver, | |
403 | &sta2x11_scr_platform_driver, | |
404 | }; | |
405 | ||
406 | static int __init sta2x11_drivers_init(void) | |
dba6c1ae | 407 | { |
d91d76d8 | 408 | return platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
dba6c1ae DC |
409 | } |
410 | ||
35bdd290 | 411 | /* |
1950c716 | 412 | * What follows are the PCI devices that host the above pdevs. |
35bdd290 AR |
413 | * Each logic block is 4kB and they are all consecutive: we use this info. |
414 | */ | |
415 | ||
1950c716 DC |
416 | /* Mfd 0 device */ |
417 | ||
418 | /* Mfd 0, Bar 0 */ | |
419 | enum mfd0_bar0_cells { | |
35bdd290 AR |
420 | STA2X11_GPIO_0 = 0, |
421 | STA2X11_GPIO_1, | |
422 | STA2X11_GPIO_2, | |
423 | STA2X11_GPIO_3, | |
424 | STA2X11_SCTL, | |
425 | STA2X11_SCR, | |
426 | STA2X11_TIME, | |
427 | }; | |
1950c716 DC |
428 | /* Mfd 0 , Bar 1 */ |
429 | enum mfd0_bar1_cells { | |
35bdd290 AR |
430 | STA2X11_APBREG = 0, |
431 | }; | |
432 | #define CELL_4K(_name, _cell) { \ | |
433 | .name = _name, \ | |
434 | .start = _cell * 4096, .end = _cell * 4096 + 4095, \ | |
435 | .flags = IORESOURCE_MEM, \ | |
436 | } | |
437 | ||
a73e5df1 | 438 | static const struct resource gpio_resources[] = { |
35bdd290 | 439 | { |
b18adafc DC |
440 | /* 4 consecutive cells, 1 driver */ |
441 | .name = STA2X11_MFD_GPIO_NAME, | |
35bdd290 AR |
442 | .start = 0, |
443 | .end = (4 * 4096) - 1, | |
444 | .flags = IORESOURCE_MEM, | |
445 | } | |
446 | }; | |
a73e5df1 | 447 | static const struct resource sctl_resources[] = { |
b18adafc | 448 | CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL), |
35bdd290 | 449 | }; |
a73e5df1 | 450 | static const struct resource scr_resources[] = { |
b18adafc | 451 | CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR), |
35bdd290 | 452 | }; |
a73e5df1 | 453 | static const struct resource time_resources[] = { |
b18adafc | 454 | CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME), |
35bdd290 AR |
455 | }; |
456 | ||
a73e5df1 | 457 | static const struct resource apbreg_resources[] = { |
b18adafc | 458 | CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG), |
35bdd290 AR |
459 | }; |
460 | ||
461 | #define DEV(_name, _r) \ | |
462 | { .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, } | |
463 | ||
2dfea380 | 464 | static struct mfd_cell sta2x11_mfd0_bar0[] = { |
b18adafc DC |
465 | /* offset 0: we add pdata later */ |
466 | DEV(STA2X11_MFD_GPIO_NAME, gpio_resources), | |
467 | DEV(STA2X11_MFD_SCTL_NAME, sctl_resources), | |
468 | DEV(STA2X11_MFD_SCR_NAME, scr_resources), | |
469 | DEV(STA2X11_MFD_TIME_NAME, time_resources), | |
35bdd290 AR |
470 | }; |
471 | ||
2dfea380 | 472 | static struct mfd_cell sta2x11_mfd0_bar1[] = { |
b18adafc | 473 | DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources), |
35bdd290 AR |
474 | }; |
475 | ||
1950c716 DC |
476 | /* Mfd 1 devices */ |
477 | ||
478 | /* Mfd 1, Bar 0 */ | |
479 | enum mfd1_bar0_cells { | |
480 | STA2X11_VIC = 0, | |
481 | }; | |
482 | ||
483 | /* Mfd 1, Bar 1 */ | |
484 | enum mfd1_bar1_cells { | |
485 | STA2X11_APB_SOC_REGS = 0, | |
486 | }; | |
487 | ||
612b95cd | 488 | static const struct resource vic_resources[] = { |
b18adafc | 489 | CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC), |
1950c716 DC |
490 | }; |
491 | ||
612b95cd | 492 | static const struct resource apb_soc_regs_resources[] = { |
b18adafc | 493 | CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS), |
1950c716 DC |
494 | }; |
495 | ||
612b95cd | 496 | static struct mfd_cell sta2x11_mfd1_bar0[] = { |
b18adafc | 497 | DEV(STA2X11_MFD_VIC_NAME, vic_resources), |
1950c716 DC |
498 | }; |
499 | ||
612b95cd | 500 | static struct mfd_cell sta2x11_mfd1_bar1[] = { |
b18adafc | 501 | DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources), |
1950c716 DC |
502 | }; |
503 | ||
504 | ||
35bdd290 AR |
505 | static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state) |
506 | { | |
507 | pci_save_state(pdev); | |
508 | pci_disable_device(pdev); | |
509 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
510 | ||
511 | return 0; | |
512 | } | |
513 | ||
514 | static int sta2x11_mfd_resume(struct pci_dev *pdev) | |
515 | { | |
516 | int err; | |
517 | ||
4d1d9980 | 518 | pci_set_power_state(pdev, PCI_D0); |
35bdd290 AR |
519 | err = pci_enable_device(pdev); |
520 | if (err) | |
521 | return err; | |
522 | pci_restore_state(pdev); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
1950c716 DC |
527 | struct sta2x11_mfd_bar_setup_data { |
528 | struct mfd_cell *cells; | |
529 | int ncells; | |
530 | }; | |
531 | ||
532 | struct sta2x11_mfd_setup_data { | |
533 | struct sta2x11_mfd_bar_setup_data bars[2]; | |
534 | }; | |
535 | ||
536 | #define STA2X11_MFD0 0 | |
537 | #define STA2X11_MFD1 1 | |
538 | ||
539 | static struct sta2x11_mfd_setup_data mfd_setup_data[] = { | |
540 | /* Mfd 0: gpio, sctl, scr, timers / apbregs */ | |
541 | [STA2X11_MFD0] = { | |
542 | .bars = { | |
543 | [0] = { | |
544 | .cells = sta2x11_mfd0_bar0, | |
545 | .ncells = ARRAY_SIZE(sta2x11_mfd0_bar0), | |
546 | }, | |
547 | [1] = { | |
548 | .cells = sta2x11_mfd0_bar1, | |
549 | .ncells = ARRAY_SIZE(sta2x11_mfd0_bar1), | |
550 | }, | |
551 | }, | |
552 | }, | |
553 | /* Mfd 1: vic / apb-soc-regs */ | |
554 | [STA2X11_MFD1] = { | |
555 | .bars = { | |
556 | [0] = { | |
557 | .cells = sta2x11_mfd1_bar0, | |
558 | .ncells = ARRAY_SIZE(sta2x11_mfd1_bar0), | |
559 | }, | |
560 | [1] = { | |
561 | .cells = sta2x11_mfd1_bar1, | |
562 | .ncells = ARRAY_SIZE(sta2x11_mfd1_bar1), | |
563 | }, | |
564 | }, | |
565 | }, | |
566 | }; | |
567 | ||
2dfea380 LT |
568 | static void sta2x11_mfd_setup(struct pci_dev *pdev, |
569 | struct sta2x11_mfd_setup_data *sd) | |
1950c716 DC |
570 | { |
571 | int i, j; | |
572 | for (i = 0; i < ARRAY_SIZE(sd->bars); i++) | |
573 | for (j = 0; j < sd->bars[i].ncells; j++) { | |
574 | sd->bars[i].cells[j].pdata_size = sizeof(pdev); | |
575 | sd->bars[i].cells[j].platform_data = &pdev; | |
576 | } | |
577 | } | |
578 | ||
f791be49 | 579 | static int sta2x11_mfd_probe(struct pci_dev *pdev, |
2dfea380 | 580 | const struct pci_device_id *pci_id) |
35bdd290 AR |
581 | { |
582 | int err, i; | |
1950c716 | 583 | struct sta2x11_mfd_setup_data *setup_data; |
35bdd290 AR |
584 | |
585 | dev_info(&pdev->dev, "%s\n", __func__); | |
586 | ||
587 | err = pci_enable_device(pdev); | |
588 | if (err) { | |
589 | dev_err(&pdev->dev, "Can't enable device.\n"); | |
590 | return err; | |
591 | } | |
592 | ||
593 | err = pci_enable_msi(pdev); | |
594 | if (err) | |
595 | dev_info(&pdev->dev, "Enable msi failed\n"); | |
596 | ||
1950c716 DC |
597 | setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ? |
598 | &mfd_setup_data[STA2X11_MFD0] : | |
599 | &mfd_setup_data[STA2X11_MFD1]; | |
35bdd290 AR |
600 | |
601 | /* platform data is the pci device for all of them */ | |
1950c716 | 602 | sta2x11_mfd_setup(pdev, setup_data); |
35bdd290 AR |
603 | |
604 | /* Record this pdev before mfd_add_devices: their probe looks for it */ | |
8ec86a30 DC |
605 | if (!sta2x11_mfd_find(pdev)) |
606 | sta2x11_mfd_add(pdev, GFP_ATOMIC); | |
35bdd290 | 607 | |
1950c716 DC |
608 | /* Just 2 bars for all mfd's at present */ |
609 | for (i = 0; i < 2; i++) { | |
610 | err = mfd_add_devices(&pdev->dev, -1, | |
611 | setup_data->bars[i].cells, | |
612 | setup_data->bars[i].ncells, | |
613 | &pdev->resource[i], | |
614 | 0, NULL); | |
615 | if (err) { | |
616 | dev_err(&pdev->dev, | |
617 | "mfd_add_devices[%d] failed: %d\n", i, err); | |
618 | goto err_disable; | |
619 | } | |
35bdd290 AR |
620 | } |
621 | ||
622 | return 0; | |
623 | ||
624 | err_disable: | |
625 | mfd_remove_devices(&pdev->dev); | |
626 | pci_disable_device(pdev); | |
627 | pci_disable_msi(pdev); | |
628 | return err; | |
629 | } | |
630 | ||
36fcd06c | 631 | static const struct pci_device_id sta2x11_mfd_tbl[] = { |
35bdd290 | 632 | {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)}, |
1950c716 | 633 | {PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)}, |
35bdd290 AR |
634 | {0,}, |
635 | }; | |
636 | ||
637 | static struct pci_driver sta2x11_mfd_driver = { | |
638 | .name = "sta2x11-mfd", | |
639 | .id_table = sta2x11_mfd_tbl, | |
640 | .probe = sta2x11_mfd_probe, | |
641 | .suspend = sta2x11_mfd_suspend, | |
642 | .resume = sta2x11_mfd_resume, | |
643 | }; | |
644 | ||
645 | static int __init sta2x11_mfd_init(void) | |
646 | { | |
647 | pr_info("%s\n", __func__); | |
648 | return pci_register_driver(&sta2x11_mfd_driver); | |
649 | } | |
650 | ||
651 | /* | |
652 | * All of this must be ready before "normal" devices like MMCI appear. | |
653 | * But MFD (the pci device) can't be too early. The following choice | |
654 | * prepares platform drivers very early and probe the PCI device later, | |
655 | * but before other PCI devices. | |
656 | */ | |
d91d76d8 | 657 | subsys_initcall(sta2x11_drivers_init); |
35bdd290 | 658 | rootfs_initcall(sta2x11_mfd_init); |