[linux-2.6-block.git] / drivers / mfd / sta2x11-mfd.c

/*
 * Copyright (c) 2009-2011 Wind River Systems, Inc.
 * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/sta2x11-mfd.h>
#include <linux/regmap.h>

#include <asm/sta2x11.h>

static inline int __reg_within_range(unsigned int r,
				     unsigned int start,
				     unsigned int end)
{
	return ((r >= start) && (r <= end));
}

/* This describes STA2X11 MFD chip for us, we may have several */
struct sta2x11_mfd {
	struct sta2x11_instance *instance;
	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
	spinlock_t lock[sta2x11_n_mfd_plat_devs];
	struct list_head list;
	void __iomem *regs[sta2x11_n_mfd_plat_devs];
};

static LIST_HEAD(sta2x11_mfd_list);

/* Three functions to act on the list */
static struct sta2x11_mfd *sta2x11_mfd_find(struct pci_dev *pdev)
{
	struct sta2x11_instance *instance;
	struct sta2x11_mfd *mfd;

	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
		pr_warning("%s: Unspecified device, "
			    "using first instance\n", __func__);
		return list_entry(sta2x11_mfd_list.next,
				  struct sta2x11_mfd, list);
	}

	instance = sta2x11_get_instance(pdev);
	if (!instance)
		return NULL;
	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
		if (mfd->instance == instance)
			return mfd;
	}
	return NULL;
}

static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
{
	int i;
	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	struct sta2x11_instance *instance;

	if (mfd)
		return -EBUSY;
	instance = sta2x11_get_instance(pdev);
	if (!instance)
		return -EINVAL;
	mfd = kzalloc(sizeof(*mfd), flags);
	if (!mfd)
		return -ENOMEM;
	INIT_LIST_HEAD(&mfd->list);
	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
		spin_lock_init(&mfd->lock[i]);
	mfd->instance = instance;
	list_add(&mfd->list, &sta2x11_mfd_list);
	return 0;
}

/* This function is exported and is not expected to fail */
u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
		       enum sta2x11_mfd_plat_dev index)
{
	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	u32 r;
	unsigned long flags;
	void __iomem *regs;

	if (!mfd) {
		dev_warn(&pdev->dev, ": can't access sctl regs\n");
		return 0;
	}

	regs = mfd->regs[index];
	if (!regs) {
		dev_warn(&pdev->dev, ": system ctl not initialized\n");
		return 0;
	}
	spin_lock_irqsave(&mfd->lock[index], flags);
	r = readl(regs + reg);
	r &= ~mask;
	r |= val;
	if (mask)
		writel(r, regs + reg);
	spin_unlock_irqrestore(&mfd->lock[index], flags);
	return r;
}
EXPORT_SYMBOL(__sta2x11_mfd_mask);

int sta2x11_mfd_get_regs_data(struct platform_device *dev,
			      enum sta2x11_mfd_plat_dev index,
			      void __iomem **regs,
			      spinlock_t **lock)
{
	struct pci_dev *pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
	struct sta2x11_mfd *mfd;

	if (!pdev)
		return -ENODEV;
	mfd = sta2x11_mfd_find(pdev);
	if (!mfd)
		return -ENODEV;
	if (index >= sta2x11_n_mfd_plat_devs)
		return -ENODEV;
	*regs = mfd->regs[index];
	*lock = &mfd->lock[index];
	pr_debug("%s %d *regs = %p\n", __func__, __LINE__, *regs);
	return *regs ? 0 : -ENODEV;
}
EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);

/*
 * Special sta2x11-mfd regmap lock/unlock functions
 */

static void sta2x11_regmap_lock(void *__lock)
{
	spinlock_t *lock = __lock;
	spin_lock(lock);
}

static void sta2x11_regmap_unlock(void *__lock)
{
	spinlock_t *lock = __lock;
	spin_unlock(lock);
}

/* OTP (one time programmable registers do not require locking */
static void sta2x11_regmap_nolock(void *__lock)
{
}

static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
};

static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
{
	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
}

static struct regmap_config sta2x11_sctl_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = SCTL_SCRSTSTA,
	.writeable_reg = sta2x11_sctl_writeable_reg,
};

static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
{
	return (reg == STA2X11_SECR_CR) ||
		__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
}

static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
{
	return false;
}

static struct regmap_config sta2x11_scr_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_nolock,
	.unlock = sta2x11_regmap_nolock,
	.max_register = STA2X11_SECR_FVR1,
	.readable_reg = sta2x11_scr_readable_reg,
	.writeable_reg = sta2x11_scr_writeable_reg,
};

static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
{
	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
	if (reg >= APBREG_BSR_SARAC)
		reg -= APBREG_BSR_SARAC;
	switch (reg) {
	case APBREG_BSR:
	case APBREG_PAER:
	case APBREG_PWAC:
	case APBREG_PRAC:
	case APBREG_PCG:
	case APBREG_PUR:
	case APBREG_EMU_PCG:
		return true;
	default:
		return false;
	}
}

static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
{
	if (reg >= APBREG_BSR_SARAC)
		reg -= APBREG_BSR_SARAC;
	if (!sta2x11_apbreg_readable_reg(dev, reg))
		return false;
	return reg != APBREG_PAER;
}

static struct regmap_config sta2x11_apbreg_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = APBREG_EMU_PCG_SARAC,
	.readable_reg = sta2x11_apbreg_readable_reg,
	.writeable_reg = sta2x11_apbreg_writeable_reg,
};

static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
					      unsigned int reg)
{
	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG ||
		__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) ||
		__reg_within_range(reg, MASTER_LOCK_REG,
				   SYSTEM_CONFIG_STATUS_REG) ||
		reg == MSP_CLK_CTRL_REG ||
		__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
}

static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
					       unsigned int reg)
{
	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
		return false;
	switch (reg) {
	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
	case SYSTEM_CONFIG_STATUS_REG:
	case COMPENSATION_REG1:
	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
		return false;
	default:
		return true;
	}
}

static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.lock = sta2x11_regmap_lock,
	.unlock = sta2x11_regmap_unlock,
	.max_register = TEST_CTL_REG,
	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
};

static struct regmap_config *
sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
	[sta2x11_scr] = &sta2x11_scr_regmap_config,
};

/* Probe for the four platform devices */

static int sta2x11_mfd_platform_probe(struct platform_device *dev,
				      enum sta2x11_mfd_plat_dev index)
{
	struct pci_dev **pdev;
	struct sta2x11_mfd *mfd;
	struct resource *res;
	const char *name = sta2x11_mfd_names[index];
	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];

	pdev = dev_get_platdata(&dev->dev);
	mfd = sta2x11_mfd_find(*pdev);
	if (!mfd)
		return -ENODEV;
	if (!regmap_config)
		return -ENODEV;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENOMEM;

	if (!request_mem_region(res->start, resource_size(res), name))
		return -EBUSY;

	mfd->regs[index] = ioremap(res->start, resource_size(res));
	if (!mfd->regs[index]) {
		release_mem_region(res->start, resource_size(res));
		return -ENOMEM;
	}
	regmap_config->lock_arg = &mfd->lock;
	/*
	   No caching, registers could be reached both via regmap and via
	   void __iomem *
	*/
	regmap_config->cache_type = REGCACHE_NONE;
	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
						   regmap_config);
	WARN_ON(IS_ERR(mfd->regmap[index]));

	return 0;
}

static int sta2x11_sctl_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
}

static int sta2x11_apbreg_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
}

static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
}

static int sta2x11_scr_probe(struct platform_device *dev)
{
	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
}

/* The three platform drivers */
static struct platform_driver sta2x11_sctl_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_SCTL_NAME,
	},
	.probe		= sta2x11_sctl_probe,
};

static int __init sta2x11_sctl_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_sctl_platform_driver);
}

static struct platform_driver sta2x11_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_APBREG_NAME,
	},
	.probe		= sta2x11_apbreg_probe,
};

static int __init sta2x11_apbreg_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_platform_driver);
}

static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
	.driver = {
		.name	= STA2X11_MFD_APB_SOC_REGS_NAME,
	},
	.probe		= sta2x11_apb_soc_regs_probe,
};

static int __init sta2x11_apb_soc_regs_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_apb_soc_regs_platform_driver);
}

static struct platform_driver sta2x11_scr_platform_driver = {
	.driver = {
		.name = STA2X11_MFD_SCR_NAME,
	},
	.probe = sta2x11_scr_probe,
};

static int __init sta2x11_scr_init(void)
{
	pr_info("%s\n", __func__);
	return platform_driver_register(&sta2x11_scr_platform_driver);
}


/*
 * What follows are the PCI devices that host the above pdevs.
 * Each logic block is 4kB and they are all consecutive: we use this info.
 */

/* Mfd 0 device */

/* Mfd 0, Bar 0 */
enum mfd0_bar0_cells {
	STA2X11_GPIO_0 = 0,
	STA2X11_GPIO_1,
	STA2X11_GPIO_2,
	STA2X11_GPIO_3,
	STA2X11_SCTL,
	STA2X11_SCR,
	STA2X11_TIME,
};
/* Mfd 0 , Bar 1 */
enum mfd0_bar1_cells {
	STA2X11_APBREG = 0,
};
#define CELL_4K(_name, _cell) { \
		.name = _name, \
		.start = _cell * 4096, .end = _cell * 4096 + 4095, \
		.flags = IORESOURCE_MEM, \
		}

static const struct resource gpio_resources[] = {
	{
		/* 4 consecutive cells, 1 driver */
		.name = STA2X11_MFD_GPIO_NAME,
		.start = 0,
		.end = (4 * 4096) - 1,
		.flags = IORESOURCE_MEM,
	}
};
static const struct resource sctl_resources[] = {
	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
};
static const struct resource scr_resources[] = {
	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
};
static const struct resource time_resources[] = {
	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
};

static const struct resource apbreg_resources[] = {
	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
};

#define DEV(_name, _r) \
	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }

static struct mfd_cell sta2x11_mfd0_bar0[] = {
	/* offset 0: we add pdata later */
	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
	DEV(STA2X11_MFD_SCR_NAME,  scr_resources),
	DEV(STA2X11_MFD_TIME_NAME, time_resources),
};

static struct mfd_cell sta2x11_mfd0_bar1[] = {
	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
};

/* Mfd 1 devices */

/* Mfd 1, Bar 0 */
enum mfd1_bar0_cells {
	STA2X11_VIC = 0,
};

/* Mfd 1, Bar 1 */
enum mfd1_bar1_cells {
	STA2X11_APB_SOC_REGS = 0,
};

static const struct resource vic_resources[] = {
	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
};

static const struct resource apb_soc_regs_resources[] = {
	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
};

static struct mfd_cell sta2x11_mfd1_bar0[] = {
	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
};

static struct mfd_cell sta2x11_mfd1_bar1[] = {
	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
};


static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));

	return 0;
}

static int sta2x11_mfd_resume(struct pci_dev *pdev)
{
	int err;

	pci_set_power_state(pdev, PCI_D0);
	err = pci_enable_device(pdev);
	if (err)
		return err;
	pci_restore_state(pdev);

	return 0;
}

struct sta2x11_mfd_bar_setup_data {
	struct mfd_cell *cells;
	int ncells;
};

struct sta2x11_mfd_setup_data {
	struct sta2x11_mfd_bar_setup_data bars[2];
};

#define STA2X11_MFD0 0
#define STA2X11_MFD1 1

static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
	[STA2X11_MFD0] = {
		.bars = {
			[0] = {
				.cells = sta2x11_mfd0_bar0,
				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
			},
			[1] = {
				.cells = sta2x11_mfd0_bar1,
				.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
			},
		},
	},
	/* Mfd 1: vic / apb-soc-regs */
	[STA2X11_MFD1] = {
		.bars = {
			[0] = {
				.cells = sta2x11_mfd1_bar0,
				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
			},
			[1] = {
				.cells = sta2x11_mfd1_bar1,
				.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
			},
		},
	},
};

static void sta2x11_mfd_setup(struct pci_dev *pdev,
			      struct sta2x11_mfd_setup_data *sd)
{
	int i, j;
	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
		for (j = 0; j < sd->bars[i].ncells; j++) {
			sd->bars[i].cells[j].pdata_size = sizeof(pdev);
			sd->bars[i].cells[j].platform_data = &pdev;
		}
}

static int sta2x11_mfd_probe(struct pci_dev *pdev,
			     const struct pci_device_id *pci_id)
{
	int err, i;
	struct sta2x11_mfd_setup_data *setup_data;

	dev_info(&pdev->dev, "%s\n", __func__);

	err = pci_enable_device(pdev);
	if (err) {
		dev_err(&pdev->dev, "Can't enable device.\n");
		return err;
	}

	err = pci_enable_msi(pdev);
	if (err)
		dev_info(&pdev->dev, "Enable msi failed\n");

	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
		&mfd_setup_data[STA2X11_MFD0] :
		&mfd_setup_data[STA2X11_MFD1];

	/* platform data is the pci device for all of them */
	sta2x11_mfd_setup(pdev, setup_data);

	/* Record this pdev before mfd_add_devices: their probe looks for it */
	if (!sta2x11_mfd_find(pdev))
		sta2x11_mfd_add(pdev, GFP_ATOMIC);

	/* Just 2 bars for all mfd's at present */
	for (i = 0; i < 2; i++) {
		err = mfd_add_devices(&pdev->dev, -1,
				      setup_data->bars[i].cells,
				      setup_data->bars[i].ncells,
				      &pdev->resource[i],
				      0, NULL);
		if (err) {
			dev_err(&pdev->dev,
				"mfd_add_devices[%d] failed: %d\n", i, err);
			goto err_disable;
		}
	}

	return 0;

err_disable:
	mfd_remove_devices(&pdev->dev);
	pci_disable_device(pdev);
	pci_disable_msi(pdev);
	return err;
}

static const struct pci_device_id sta2x11_mfd_tbl[] = {
	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
	{0,},
};

static struct pci_driver sta2x11_mfd_driver = {
	.name =		"sta2x11-mfd",
	.id_table =	sta2x11_mfd_tbl,
	.probe =	sta2x11_mfd_probe,
	.suspend =	sta2x11_mfd_suspend,
	.resume =	sta2x11_mfd_resume,
};

static int __init sta2x11_mfd_init(void)
{
	pr_info("%s\n", __func__);
	return pci_register_driver(&sta2x11_mfd_driver);
}

/*
 * All of this must be ready before "normal" devices like MMCI appear.
 * But MFD (the pci device) can't be too early. The following choice
 * prepares platform drivers very early and probe the PCI device later,
 * but before other PCI devices.
 */
subsys_initcall(sta2x11_apbreg_init);
subsys_initcall(sta2x11_sctl_init);
subsys_initcall(sta2x11_apb_soc_regs_init);
subsys_initcall(sta2x11_scr_init);
rootfs_initcall(sta2x11_mfd_init);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Wind River");
MODULE_DESCRIPTION("STA2x11 mfd for GPIO, SCTL and APBREG");
MODULE_DEVICE_TABLE(pci, sta2x11_mfd_tbl);
Commit	Line	Data
35bdd290 AR	1	/*
35bdd290 AR	2	* Copyright (c) 2009-2011 Wind River Systems, Inc.
b73df698	3	* Copyright (c) 2011 ST Microelectronics (Alessandro Rubini, Davide Ciminaghi)
35bdd290 AR	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	12	* See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
	21	#include <linux/module.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/errno.h>
	24	#include <linux/device.h>
	25	#include <linux/slab.h>
	26	#include <linux/list.h>
	27	#include <linux/io.h>
	28	#include <linux/ioport.h>
	29	#include <linux/pci.h>
35bdd290 AR	30	#include <linux/seq_file.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/mfd/core.h>
	33	#include <linux/mfd/sta2x11-mfd.h>
d94e2553	34	#include <linux/regmap.h>
35bdd290 AR	35
	36	#include <asm/sta2x11.h>
	37
d94e2553 DC	38	static inline int __reg_within_range(unsigned int r,
	39	unsigned int start,
	40	unsigned int end)
	41	{
	42	return ((r >= start) && (r <= end));
	43	}
	44
35bdd290 AR	45	/* This describes STA2X11 MFD chip for us, we may have several */
	46	struct sta2x11_mfd {
	47	struct sta2x11_instance *instance;
d94e2553	48	struct regmap *regmap[sta2x11_n_mfd_plat_devs];
e885ba29	49	spinlock_t lock[sta2x11_n_mfd_plat_devs];
35bdd290	50	struct list_head list;
1950c716	51	void __iomem *regs[sta2x11_n_mfd_plat_devs];
35bdd290 AR	52	};
	53
	54	static LIST_HEAD(sta2x11_mfd_list);
	55
	56	/* Three functions to act on the list */
	57	static struct sta2x11_mfd sta2x11_mfd_find(struct pci_dev pdev)
	58	{
	59	struct sta2x11_instance *instance;
	60	struct sta2x11_mfd *mfd;
	61
	62	if (!pdev && !list_empty(&sta2x11_mfd_list)) {
	63	pr_warning("%s: Unspecified device, "
	64	"using first instance\n", __func__);
	65	return list_entry(sta2x11_mfd_list.next,
	66	struct sta2x11_mfd, list);
	67	}
	68
	69	instance = sta2x11_get_instance(pdev);
	70	if (!instance)
	71	return NULL;
	72	list_for_each_entry(mfd, &sta2x11_mfd_list, list) {
	73	if (mfd->instance == instance)
	74	return mfd;
	75	}
	76	return NULL;
	77	}
	78
f791be49	79	static int sta2x11_mfd_add(struct pci_dev *pdev, gfp_t flags)
35bdd290	80	{
e885ba29	81	int i;
35bdd290 AR	82	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	83	struct sta2x11_instance *instance;
	84
	85	if (mfd)
	86	return -EBUSY;
	87	instance = sta2x11_get_instance(pdev);
	88	if (!instance)
	89	return -EINVAL;
	90	mfd = kzalloc(sizeof(*mfd), flags);
	91	if (!mfd)
	92	return -ENOMEM;
	93	INIT_LIST_HEAD(&mfd->list);
e885ba29 DC	94	for (i = 0; i < ARRAY_SIZE(mfd->lock); i++)
e885ba29 DC	95	spin_lock_init(&mfd->lock[i]);
35bdd290 AR	96	mfd->instance = instance;
	97	list_add(&mfd->list, &sta2x11_mfd_list);
	98	return 0;
	99	}
	100
1950c716 DC	101	/* This function is exported and is not expected to fail */
	102	u32 __sta2x11_mfd_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val,
	103	enum sta2x11_mfd_plat_dev index)
35bdd290 AR	104	{
	105	struct sta2x11_mfd *mfd = sta2x11_mfd_find(pdev);
	106	u32 r;
	107	unsigned long flags;
709edecd	108	void __iomem *regs;
35bdd290 AR	109
	110	if (!mfd) {
	111	dev_warn(&pdev->dev, ": can't access sctl regs\n");
	112	return 0;
	113	}
709edecd WY	114
709edecd WY	115	regs = mfd->regs[index];
1950c716	116	if (!regs) {
35bdd290 AR	117	dev_warn(&pdev->dev, ": system ctl not initialized\n");
	118	return 0;
	119	}
e885ba29	120	spin_lock_irqsave(&mfd->lock[index], flags);
1950c716	121	r = readl(regs + reg);
35bdd290 AR	122	r &= ~mask;
	123	r \|= val;
	124	if (mask)
1950c716	125	writel(r, regs + reg);
e885ba29	126	spin_unlock_irqrestore(&mfd->lock[index], flags);
35bdd290 AR	127	return r;
35bdd290 AR	128	}
1950c716	129	EXPORT_SYMBOL(__sta2x11_mfd_mask);
35bdd290	130
29f5b5a3 DC	131	int sta2x11_mfd_get_regs_data(struct platform_device *dev,
	132	enum sta2x11_mfd_plat_dev index,
	133	void __iomem **regs,
	134	spinlock_t **lock)
35bdd290	135	{
334a41ce	136	struct pci_dev pdev = (struct pci_dev **)dev_get_platdata(&dev->dev);
29f5b5a3	137	struct sta2x11_mfd *mfd;
35bdd290	138
29f5b5a3 DC	139	if (!pdev)
	140	return -ENODEV;
	141	mfd = sta2x11_mfd_find(pdev);
	142	if (!mfd)
	143	return -ENODEV;
	144	if (index >= sta2x11_n_mfd_plat_devs)
	145	return -ENODEV;
	146	*regs = mfd->regs[index];
	147	*lock = &mfd->lock[index];
	148	pr_debug("%s %d regs = %p\n", __func__, __LINE__, regs);
	149	return *regs ? 0 : -ENODEV;
35bdd290	150	}
29f5b5a3	151	EXPORT_SYMBOL(sta2x11_mfd_get_regs_data);
35bdd290	152
d94e2553 DC	153	/*
	154	* Special sta2x11-mfd regmap lock/unlock functions
	155	*/
35bdd290	156
d94e2553 DC	157	static void sta2x11_regmap_lock(void *__lock)
	158	{
	159	spinlock_t *lock = __lock;
	160	spin_lock(lock);
	161	}
35bdd290	162
d94e2553 DC	163	static void sta2x11_regmap_unlock(void *__lock)
	164	{
	165	spinlock_t *lock = __lock;
	166	spin_unlock(lock);
	167	}
35bdd290	168
dba6c1ae DC	169	/* OTP (one time programmable registers do not require locking */
	170	static void sta2x11_regmap_nolock(void *__lock)
	171	{
	172	}
	173
d94e2553	174	static const char *sta2x11_mfd_names[sta2x11_n_mfd_plat_devs] = {
b18adafc DC	175	[sta2x11_sctl] = STA2X11_MFD_SCTL_NAME,
	176	[sta2x11_apbreg] = STA2X11_MFD_APBREG_NAME,
	177	[sta2x11_apb_soc_regs] = STA2X11_MFD_APB_SOC_REGS_NAME,
dba6c1ae	178	[sta2x11_scr] = STA2X11_MFD_SCR_NAME,
35bdd290	179	};
35bdd290	180
d94e2553 DC	181	static bool sta2x11_sctl_writeable_reg(struct device *dev, unsigned int reg)
	182	{
	183	return !__reg_within_range(reg, SCTL_SCPCIECSBRST, SCTL_SCRSTSTA);
	184	}
	185
	186	static struct regmap_config sta2x11_sctl_regmap_config = {
	187	.reg_bits = 32,
	188	.reg_stride = 4,
	189	.val_bits = 32,
	190	.lock = sta2x11_regmap_lock,
	191	.unlock = sta2x11_regmap_unlock,
	192	.max_register = SCTL_SCRSTSTA,
	193	.writeable_reg = sta2x11_sctl_writeable_reg,
35bdd290 AR	194	};
35bdd290 AR	195
dba6c1ae DC	196	static bool sta2x11_scr_readable_reg(struct device *dev, unsigned int reg)
	197	{
	198	return (reg == STA2X11_SECR_CR) \|\|
	199	__reg_within_range(reg, STA2X11_SECR_FVR0, STA2X11_SECR_FVR1);
	200	}
35bdd290	201
dba6c1ae	202	static bool sta2x11_scr_writeable_reg(struct device *dev, unsigned int reg)
35bdd290	203	{
dba6c1ae DC	204	return false;
dba6c1ae DC	205	}
35bdd290	206
dba6c1ae DC	207	static struct regmap_config sta2x11_scr_regmap_config = {
	208	.reg_bits = 32,
	209	.reg_stride = 4,
	210	.val_bits = 32,
	211	.lock = sta2x11_regmap_nolock,
	212	.unlock = sta2x11_regmap_nolock,
	213	.max_register = STA2X11_SECR_FVR1,
	214	.readable_reg = sta2x11_scr_readable_reg,
	215	.writeable_reg = sta2x11_scr_writeable_reg,
	216	};
35bdd290	217
d94e2553 DC	218	static bool sta2x11_apbreg_readable_reg(struct device *dev, unsigned int reg)
	219	{
	220	/* Two blocks (CAN and MLB, SARAC) 0x100 bytes apart */
	221	if (reg >= APBREG_BSR_SARAC)
	222	reg -= APBREG_BSR_SARAC;
	223	switch (reg) {
	224	case APBREG_BSR:
	225	case APBREG_PAER:
	226	case APBREG_PWAC:
	227	case APBREG_PRAC:
	228	case APBREG_PCG:
	229	case APBREG_PUR:
	230	case APBREG_EMU_PCG:
	231	return true;
	232	default:
	233	return false;
	234	}
	235	}
35bdd290	236
d94e2553 DC	237	static bool sta2x11_apbreg_writeable_reg(struct device *dev, unsigned int reg)
	238	{
	239	if (reg >= APBREG_BSR_SARAC)
	240	reg -= APBREG_BSR_SARAC;
	241	if (!sta2x11_apbreg_readable_reg(dev, reg))
	242	return false;
	243	return reg != APBREG_PAER;
	244	}
35bdd290	245
d94e2553 DC	246	static struct regmap_config sta2x11_apbreg_regmap_config = {
	247	.reg_bits = 32,
	248	.reg_stride = 4,
	249	.val_bits = 32,
	250	.lock = sta2x11_regmap_lock,
	251	.unlock = sta2x11_regmap_unlock,
	252	.max_register = APBREG_EMU_PCG_SARAC,
	253	.readable_reg = sta2x11_apbreg_readable_reg,
	254	.writeable_reg = sta2x11_apbreg_writeable_reg,
1950c716	255	};
35bdd290	256
d94e2553 DC	257	static bool sta2x11_apb_soc_regs_readable_reg(struct device *dev,
	258	unsigned int reg)
	259	{
	260	return reg <= PCIE_SoC_INT_ROUTER_STATUS3_REG \|\|
	261	__reg_within_range(reg, DMA_IP_CTRL_REG, SPARE3_RESERVED) \|\|
	262	__reg_within_range(reg, MASTER_LOCK_REG,
	263	SYSTEM_CONFIG_STATUS_REG) \|\|
	264	reg == MSP_CLK_CTRL_REG \|\|
	265	__reg_within_range(reg, COMPENSATION_REG1, TEST_CTL_REG);
	266	}
35bdd290	267
d94e2553 DC	268	static bool sta2x11_apb_soc_regs_writeable_reg(struct device *dev,
	269	unsigned int reg)
	270	{
	271	if (!sta2x11_apb_soc_regs_readable_reg(dev, reg))
	272	return false;
	273	switch (reg) {
	274	case PCIE_COMMON_CLOCK_CONFIG_0_4_0:
	275	case SYSTEM_CONFIG_STATUS_REG:
	276	case COMPENSATION_REG1:
	277	case PCIE_SoC_INT_ROUTER_STATUS0_REG...PCIE_SoC_INT_ROUTER_STATUS3_REG:
	278	case PCIE_PM_STATUS_0_PORT_0_4...PCIE_PM_STATUS_7_0_EP4:
	279	return false;
	280	default:
	281	return true;
35bdd290	282	}
35bdd290 AR	283	}
35bdd290 AR	284
d94e2553 DC	285	static struct regmap_config sta2x11_apb_soc_regs_regmap_config = {
	286	.reg_bits = 32,
	287	.reg_stride = 4,
	288	.val_bits = 32,
	289	.lock = sta2x11_regmap_lock,
	290	.unlock = sta2x11_regmap_unlock,
	291	.max_register = TEST_CTL_REG,
	292	.readable_reg = sta2x11_apb_soc_regs_readable_reg,
	293	.writeable_reg = sta2x11_apb_soc_regs_writeable_reg,
1950c716	294	};
35bdd290	295
d94e2553 DC	296	static struct regmap_config *
	297	sta2x11_mfd_regmap_configs[sta2x11_n_mfd_plat_devs] = {
	298	[sta2x11_sctl] = &sta2x11_sctl_regmap_config,
	299	[sta2x11_apbreg] = &sta2x11_apbreg_regmap_config,
	300	[sta2x11_apb_soc_regs] = &sta2x11_apb_soc_regs_regmap_config,
dba6c1ae	301	[sta2x11_scr] = &sta2x11_scr_regmap_config,
1950c716	302	};
35bdd290	303
dba6c1ae	304	/* Probe for the four platform devices */
1950c716 DC	305
	306	static int sta2x11_mfd_platform_probe(struct platform_device *dev,
	307	enum sta2x11_mfd_plat_dev index)
35bdd290 AR	308	{
	309	struct pci_dev **pdev;
	310	struct sta2x11_mfd *mfd;
	311	struct resource *res;
1950c716	312	const char *name = sta2x11_mfd_names[index];
d94e2553	313	struct regmap_config *regmap_config = sta2x11_mfd_regmap_configs[index];
35bdd290	314
334a41ce	315	pdev = dev_get_platdata(&dev->dev);
35bdd290 AR	316	mfd = sta2x11_mfd_find(*pdev);
	317	if (!mfd)
	318	return -ENODEV;
d94e2553 DC	319	if (!regmap_config)
d94e2553 DC	320	return -ENODEV;
35bdd290 AR	321
	322	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	323	if (!res)
	324	return -ENOMEM;
	325
1950c716	326	if (!request_mem_region(res->start, resource_size(res), name))
35bdd290 AR	327	return -EBUSY;
35bdd290 AR	328
1950c716 DC	329	mfd->regs[index] = ioremap(res->start, resource_size(res));
1950c716 DC	330	if (!mfd->regs[index]) {
35bdd290 AR	331	release_mem_region(res->start, resource_size(res));
	332	return -ENOMEM;
	333	}
d94e2553 DC	334	regmap_config->lock_arg = &mfd->lock;
	335	/*
	336	No caching, registers could be reached both via regmap and via
	337	void __iomem *
	338	*/
	339	regmap_config->cache_type = REGCACHE_NONE;
	340	mfd->regmap[index] = devm_regmap_init_mmio(&dev->dev, mfd->regs[index],
	341	regmap_config);
ec9e4ba6	342	WARN_ON(IS_ERR(mfd->regmap[index]));
35bdd290	343
35bdd290 AR	344	return 0;
	345	}
	346
1950c716 DC	347	static int sta2x11_sctl_probe(struct platform_device *dev)
	348	{
	349	return sta2x11_mfd_platform_probe(dev, sta2x11_sctl);
	350	}
	351
	352	static int sta2x11_apbreg_probe(struct platform_device *dev)
	353	{
	354	return sta2x11_mfd_platform_probe(dev, sta2x11_apbreg);
	355	}
	356
	357	static int sta2x11_apb_soc_regs_probe(struct platform_device *dev)
	358	{
	359	return sta2x11_mfd_platform_probe(dev, sta2x11_apb_soc_regs);
	360	}
	361
dba6c1ae DC	362	static int sta2x11_scr_probe(struct platform_device *dev)
	363	{
	364	return sta2x11_mfd_platform_probe(dev, sta2x11_scr);
	365	}
	366
1950c716	367	/* The three platform drivers */
35bdd290 AR	368	static struct platform_driver sta2x11_sctl_platform_driver = {
35bdd290 AR	369	.driver = {
b18adafc	370	.name = STA2X11_MFD_SCTL_NAME,
35bdd290 AR	371	},
	372	.probe = sta2x11_sctl_probe,
	373	};
	374
	375	static int __init sta2x11_sctl_init(void)
	376	{
	377	pr_info("%s\n", __func__);
	378	return platform_driver_register(&sta2x11_sctl_platform_driver);
	379	}
	380
	381	static struct platform_driver sta2x11_platform_driver = {
	382	.driver = {
b18adafc	383	.name = STA2X11_MFD_APBREG_NAME,
35bdd290 AR	384	},
	385	.probe = sta2x11_apbreg_probe,
	386	};
	387
	388	static int __init sta2x11_apbreg_init(void)
	389	{
	390	pr_info("%s\n", __func__);
	391	return platform_driver_register(&sta2x11_platform_driver);
	392	}
	393
1950c716 DC	394	static struct platform_driver sta2x11_apb_soc_regs_platform_driver = {
1950c716 DC	395	.driver = {
b18adafc	396	.name = STA2X11_MFD_APB_SOC_REGS_NAME,
1950c716 DC	397	},
	398	.probe = sta2x11_apb_soc_regs_probe,
	399	};
	400
	401	static int __init sta2x11_apb_soc_regs_init(void)
	402	{
	403	pr_info("%s\n", __func__);
	404	return platform_driver_register(&sta2x11_apb_soc_regs_platform_driver);
	405	}
	406
dba6c1ae DC	407	static struct platform_driver sta2x11_scr_platform_driver = {
	408	.driver = {
	409	.name = STA2X11_MFD_SCR_NAME,
dba6c1ae DC	410	},
	411	.probe = sta2x11_scr_probe,
	412	};
	413
	414	static int __init sta2x11_scr_init(void)
	415	{
	416	pr_info("%s\n", __func__);
	417	return platform_driver_register(&sta2x11_scr_platform_driver);
	418	}
	419
	420
35bdd290	421	/*
1950c716	422	* What follows are the PCI devices that host the above pdevs.
35bdd290 AR	423	* Each logic block is 4kB and they are all consecutive: we use this info.
	424	*/
	425
1950c716 DC	426	/* Mfd 0 device */
	427
	428	/* Mfd 0, Bar 0 */
	429	enum mfd0_bar0_cells {
35bdd290 AR	430	STA2X11_GPIO_0 = 0,
	431	STA2X11_GPIO_1,
	432	STA2X11_GPIO_2,
	433	STA2X11_GPIO_3,
	434	STA2X11_SCTL,
	435	STA2X11_SCR,
	436	STA2X11_TIME,
	437	};
1950c716 DC	438	/* Mfd 0 , Bar 1 */
1950c716 DC	439	enum mfd0_bar1_cells {
35bdd290 AR	440	STA2X11_APBREG = 0,
	441	};
	442	#define CELL_4K(_name, _cell) { \
	443	.name = _name, \
	444	.start = _cell * 4096, .end = _cell * 4096 + 4095, \
	445	.flags = IORESOURCE_MEM, \
	446	}
	447
a73e5df1	448	static const struct resource gpio_resources[] = {
35bdd290	449	{
b18adafc DC	450	/* 4 consecutive cells, 1 driver */
b18adafc DC	451	.name = STA2X11_MFD_GPIO_NAME,
35bdd290 AR	452	.start = 0,
	453	.end = (4 * 4096) - 1,
	454	.flags = IORESOURCE_MEM,
	455	}
	456	};
a73e5df1	457	static const struct resource sctl_resources[] = {
b18adafc	458	CELL_4K(STA2X11_MFD_SCTL_NAME, STA2X11_SCTL),
35bdd290	459	};
a73e5df1	460	static const struct resource scr_resources[] = {
b18adafc	461	CELL_4K(STA2X11_MFD_SCR_NAME, STA2X11_SCR),
35bdd290	462	};
a73e5df1	463	static const struct resource time_resources[] = {
b18adafc	464	CELL_4K(STA2X11_MFD_TIME_NAME, STA2X11_TIME),
35bdd290 AR	465	};
35bdd290 AR	466
a73e5df1	467	static const struct resource apbreg_resources[] = {
b18adafc	468	CELL_4K(STA2X11_MFD_APBREG_NAME, STA2X11_APBREG),
35bdd290 AR	469	};
	470
	471	#define DEV(_name, _r) \
	472	{ .name = _name, .num_resources = ARRAY_SIZE(_r), .resources = _r, }
	473
2dfea380	474	static struct mfd_cell sta2x11_mfd0_bar0[] = {
b18adafc DC	475	/* offset 0: we add pdata later */
	476	DEV(STA2X11_MFD_GPIO_NAME, gpio_resources),
	477	DEV(STA2X11_MFD_SCTL_NAME, sctl_resources),
	478	DEV(STA2X11_MFD_SCR_NAME, scr_resources),
	479	DEV(STA2X11_MFD_TIME_NAME, time_resources),
35bdd290 AR	480	};
35bdd290 AR	481
2dfea380	482	static struct mfd_cell sta2x11_mfd0_bar1[] = {
b18adafc	483	DEV(STA2X11_MFD_APBREG_NAME, apbreg_resources),
35bdd290 AR	484	};
35bdd290 AR	485
1950c716 DC	486	/* Mfd 1 devices */
	487
	488	/* Mfd 1, Bar 0 */
	489	enum mfd1_bar0_cells {
	490	STA2X11_VIC = 0,
	491	};
	492
	493	/* Mfd 1, Bar 1 */
	494	enum mfd1_bar1_cells {
	495	STA2X11_APB_SOC_REGS = 0,
	496	};
	497
612b95cd	498	static const struct resource vic_resources[] = {
b18adafc	499	CELL_4K(STA2X11_MFD_VIC_NAME, STA2X11_VIC),
1950c716 DC	500	};
1950c716 DC	501
612b95cd	502	static const struct resource apb_soc_regs_resources[] = {
b18adafc	503	CELL_4K(STA2X11_MFD_APB_SOC_REGS_NAME, STA2X11_APB_SOC_REGS),
1950c716 DC	504	};
1950c716 DC	505
612b95cd	506	static struct mfd_cell sta2x11_mfd1_bar0[] = {
b18adafc	507	DEV(STA2X11_MFD_VIC_NAME, vic_resources),
1950c716 DC	508	};
1950c716 DC	509
612b95cd	510	static struct mfd_cell sta2x11_mfd1_bar1[] = {
b18adafc	511	DEV(STA2X11_MFD_APB_SOC_REGS_NAME, apb_soc_regs_resources),
1950c716 DC	512	};
	513
	514
35bdd290 AR	515	static int sta2x11_mfd_suspend(struct pci_dev *pdev, pm_message_t state)
	516	{
	517	pci_save_state(pdev);
	518	pci_disable_device(pdev);
	519	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	520
	521	return 0;
	522	}
	523
	524	static int sta2x11_mfd_resume(struct pci_dev *pdev)
	525	{
	526	int err;
	527
4d1d9980	528	pci_set_power_state(pdev, PCI_D0);
35bdd290 AR	529	err = pci_enable_device(pdev);
	530	if (err)
	531	return err;
	532	pci_restore_state(pdev);
	533
	534	return 0;
	535	}
	536
1950c716 DC	537	struct sta2x11_mfd_bar_setup_data {
	538	struct mfd_cell *cells;
	539	int ncells;
	540	};
	541
	542	struct sta2x11_mfd_setup_data {
	543	struct sta2x11_mfd_bar_setup_data bars[2];
	544	};
	545
	546	#define STA2X11_MFD0 0
	547	#define STA2X11_MFD1 1
	548
	549	static struct sta2x11_mfd_setup_data mfd_setup_data[] = {
	550	/* Mfd 0: gpio, sctl, scr, timers / apbregs */
	551	[STA2X11_MFD0] = {
	552	.bars = {
	553	[0] = {
	554	.cells = sta2x11_mfd0_bar0,
	555	.ncells = ARRAY_SIZE(sta2x11_mfd0_bar0),
	556	},
	557	[1] = {
	558	.cells = sta2x11_mfd0_bar1,
	559	.ncells = ARRAY_SIZE(sta2x11_mfd0_bar1),
	560	},
	561	},
	562	},
	563	/* Mfd 1: vic / apb-soc-regs */
	564	[STA2X11_MFD1] = {
	565	.bars = {
	566	[0] = {
	567	.cells = sta2x11_mfd1_bar0,
	568	.ncells = ARRAY_SIZE(sta2x11_mfd1_bar0),
	569	},
	570	[1] = {
	571	.cells = sta2x11_mfd1_bar1,
	572	.ncells = ARRAY_SIZE(sta2x11_mfd1_bar1),
	573	},
	574	},
	575	},
	576	};
	577
2dfea380 LT	578	static void sta2x11_mfd_setup(struct pci_dev *pdev,
2dfea380 LT	579	struct sta2x11_mfd_setup_data *sd)
1950c716 DC	580	{
	581	int i, j;
	582	for (i = 0; i < ARRAY_SIZE(sd->bars); i++)
	583	for (j = 0; j < sd->bars[i].ncells; j++) {
	584	sd->bars[i].cells[j].pdata_size = sizeof(pdev);
	585	sd->bars[i].cells[j].platform_data = &pdev;
	586	}
	587	}
	588
f791be49	589	static int sta2x11_mfd_probe(struct pci_dev *pdev,
2dfea380	590	const struct pci_device_id *pci_id)
35bdd290 AR	591	{
35bdd290 AR	592	int err, i;
1950c716	593	struct sta2x11_mfd_setup_data *setup_data;
35bdd290 AR	594
	595	dev_info(&pdev->dev, "%s\n", __func__);
	596
	597	err = pci_enable_device(pdev);
	598	if (err) {
	599	dev_err(&pdev->dev, "Can't enable device.\n");
	600	return err;
	601	}
	602
	603	err = pci_enable_msi(pdev);
	604	if (err)
	605	dev_info(&pdev->dev, "Enable msi failed\n");
	606
1950c716 DC	607	setup_data = pci_id->device == PCI_DEVICE_ID_STMICRO_GPIO ?
	608	&mfd_setup_data[STA2X11_MFD0] :
	609	&mfd_setup_data[STA2X11_MFD1];
35bdd290 AR	610
35bdd290 AR	611	/* platform data is the pci device for all of them */
1950c716	612	sta2x11_mfd_setup(pdev, setup_data);
35bdd290 AR	613
35bdd290 AR	614	/* Record this pdev before mfd_add_devices: their probe looks for it */
8ec86a30 DC	615	if (!sta2x11_mfd_find(pdev))
8ec86a30 DC	616	sta2x11_mfd_add(pdev, GFP_ATOMIC);
35bdd290	617
1950c716 DC	618	/* Just 2 bars for all mfd's at present */
	619	for (i = 0; i < 2; i++) {
	620	err = mfd_add_devices(&pdev->dev, -1,
	621	setup_data->bars[i].cells,
	622	setup_data->bars[i].ncells,
	623	&pdev->resource[i],
	624	0, NULL);
	625	if (err) {
	626	dev_err(&pdev->dev,
	627	"mfd_add_devices[%d] failed: %d\n", i, err);
	628	goto err_disable;
	629	}
35bdd290 AR	630	}
	631
	632	return 0;
	633
	634	err_disable:
	635	mfd_remove_devices(&pdev->dev);
	636	pci_disable_device(pdev);
	637	pci_disable_msi(pdev);
	638	return err;
	639	}
	640
36fcd06c	641	static const struct pci_device_id sta2x11_mfd_tbl[] = {
35bdd290	642	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_GPIO)},
1950c716	643	{PCI_DEVICE(PCI_VENDOR_ID_STMICRO, PCI_DEVICE_ID_STMICRO_VIC)},
35bdd290 AR	644	{0,},
	645	};
	646
	647	static struct pci_driver sta2x11_mfd_driver = {
	648	.name = "sta2x11-mfd",
	649	.id_table = sta2x11_mfd_tbl,
	650	.probe = sta2x11_mfd_probe,
	651	.suspend = sta2x11_mfd_suspend,
	652	.resume = sta2x11_mfd_resume,
	653	};
	654
	655	static int __init sta2x11_mfd_init(void)
	656	{
	657	pr_info("%s\n", __func__);
	658	return pci_register_driver(&sta2x11_mfd_driver);
	659	}
	660
	661	/*
	662	* All of this must be ready before "normal" devices like MMCI appear.
	663	* But MFD (the pci device) can't be too early. The following choice
	664	* prepares platform drivers very early and probe the PCI device later,
	665	* but before other PCI devices.
	666	*/
	667	subsys_initcall(sta2x11_apbreg_init);
	668	subsys_initcall(sta2x11_sctl_init);
1950c716	669	subsys_initcall(sta2x11_apb_soc_regs_init);
dba6c1ae	670	subsys_initcall(sta2x11_scr_init);
35bdd290 AR	671	rootfs_initcall(sta2x11_mfd_init);
	672
	673	MODULE_LICENSE("GPL v2");
	674	MODULE_AUTHOR("Wind River");
	675	MODULE_DESCRIPTION("STA2x11 mfd for GPIO, SCTL and APBREG");
	676	MODULE_DEVICE_TABLE(pci, sta2x11_mfd_tbl);