[linux-2.6-block.git] / drivers / mfd / sec-irq.c

/*
 * sec-irq.c
 *
 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
 *              http://www.samsung.com
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/regmap.h>

#include <linux/mfd/samsung/core.h>
#include <linux/mfd/samsung/irq.h>
#include <linux/mfd/samsung/s2mps11.h>
#include <linux/mfd/samsung/s2mps14.h>
#include <linux/mfd/samsung/s5m8763.h>
#include <linux/mfd/samsung/s5m8767.h>

static const struct regmap_irq s2mps11_irqs[] = {
	[S2MPS11_IRQ_PWRONF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONF_MASK,
	},
	[S2MPS11_IRQ_PWRONR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONR_MASK,
	},
	[S2MPS11_IRQ_JIGONBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBF_MASK,
	},
	[S2MPS11_IRQ_JIGONBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBR_MASK,
	},
	[S2MPS11_IRQ_ACOKBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBF_MASK,
	},
	[S2MPS11_IRQ_ACOKBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBR_MASK,
	},
	[S2MPS11_IRQ_PWRON1S] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRON1S_MASK,
	},
	[S2MPS11_IRQ_MRB] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_MRB_MASK,
	},
	[S2MPS11_IRQ_RTC60S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC60S_MASK,
	},
	[S2MPS11_IRQ_RTCA0] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA0_MASK,
	},
	[S2MPS11_IRQ_RTCA1] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA1_MASK,
	},
	[S2MPS11_IRQ_SMPL] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_SMPL_MASK,
	},
	[S2MPS11_IRQ_RTC1S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC1S_MASK,
	},
	[S2MPS11_IRQ_WTSR] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_WTSR_MASK,
	},
	[S2MPS11_IRQ_INT120C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT120C_MASK,
	},
	[S2MPS11_IRQ_INT140C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT140C_MASK,
	},
};

static const struct regmap_irq s2mps14_irqs[] = {
	[S2MPS14_IRQ_PWRONF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONF_MASK,
	},
	[S2MPS14_IRQ_PWRONR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRONR_MASK,
	},
	[S2MPS14_IRQ_JIGONBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBF_MASK,
	},
	[S2MPS14_IRQ_JIGONBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_JIGONBR_MASK,
	},
	[S2MPS14_IRQ_ACOKBF] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBF_MASK,
	},
	[S2MPS14_IRQ_ACOKBR] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_ACOKBR_MASK,
	},
	[S2MPS14_IRQ_PWRON1S] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_PWRON1S_MASK,
	},
	[S2MPS14_IRQ_MRB] = {
		.reg_offset = 0,
		.mask = S2MPS11_IRQ_MRB_MASK,
	},
	[S2MPS14_IRQ_RTC60S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC60S_MASK,
	},
	[S2MPS14_IRQ_RTCA1] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA1_MASK,
	},
	[S2MPS14_IRQ_RTCA0] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTCA0_MASK,
	},
	[S2MPS14_IRQ_SMPL] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_SMPL_MASK,
	},
	[S2MPS14_IRQ_RTC1S] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_RTC1S_MASK,
	},
	[S2MPS14_IRQ_WTSR] = {
		.reg_offset = 1,
		.mask = S2MPS11_IRQ_WTSR_MASK,
	},
	[S2MPS14_IRQ_INT120C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT120C_MASK,
	},
	[S2MPS14_IRQ_INT140C] = {
		.reg_offset = 2,
		.mask = S2MPS11_IRQ_INT140C_MASK,
	},
	[S2MPS14_IRQ_TSD] = {
		.reg_offset = 2,
		.mask = S2MPS14_IRQ_TSD_MASK,
	},
};

static const struct regmap_irq s5m8767_irqs[] = {
	[S5M8767_IRQ_PWRR] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_PWRR_MASK,
	},
	[S5M8767_IRQ_PWRF] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_PWRF_MASK,
	},
	[S5M8767_IRQ_PWR1S] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_PWR1S_MASK,
	},
	[S5M8767_IRQ_JIGR] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_JIGR_MASK,
	},
	[S5M8767_IRQ_JIGF] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_JIGF_MASK,
	},
	[S5M8767_IRQ_LOWBAT2] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_LOWBAT2_MASK,
	},
	[S5M8767_IRQ_LOWBAT1] = {
		.reg_offset = 0,
		.mask = S5M8767_IRQ_LOWBAT1_MASK,
	},
	[S5M8767_IRQ_MRB] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_MRB_MASK,
	},
	[S5M8767_IRQ_DVSOK2] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_DVSOK2_MASK,
	},
	[S5M8767_IRQ_DVSOK3] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_DVSOK3_MASK,
	},
	[S5M8767_IRQ_DVSOK4] = {
		.reg_offset = 1,
		.mask = S5M8767_IRQ_DVSOK4_MASK,
	},
	[S5M8767_IRQ_RTC60S] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTC60S_MASK,
	},
	[S5M8767_IRQ_RTCA1] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTCA1_MASK,
	},
	[S5M8767_IRQ_RTCA2] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTCA2_MASK,
	},
	[S5M8767_IRQ_SMPL] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_SMPL_MASK,
	},
	[S5M8767_IRQ_RTC1S] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_RTC1S_MASK,
	},
	[S5M8767_IRQ_WTSR] = {
		.reg_offset = 2,
		.mask = S5M8767_IRQ_WTSR_MASK,
	},
};

static const struct regmap_irq s5m8763_irqs[] = {
	[S5M8763_IRQ_DCINF] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_DCINF_MASK,
	},
	[S5M8763_IRQ_DCINR] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_DCINR_MASK,
	},
	[S5M8763_IRQ_JIGF] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_JIGF_MASK,
	},
	[S5M8763_IRQ_JIGR] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_JIGR_MASK,
	},
	[S5M8763_IRQ_PWRONF] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_PWRONF_MASK,
	},
	[S5M8763_IRQ_PWRONR] = {
		.reg_offset = 0,
		.mask = S5M8763_IRQ_PWRONR_MASK,
	},
	[S5M8763_IRQ_WTSREVNT] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_WTSREVNT_MASK,
	},
	[S5M8763_IRQ_SMPLEVNT] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_SMPLEVNT_MASK,
	},
	[S5M8763_IRQ_ALARM1] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_ALARM1_MASK,
	},
	[S5M8763_IRQ_ALARM0] = {
		.reg_offset = 1,
		.mask = S5M8763_IRQ_ALARM0_MASK,
	},
	[S5M8763_IRQ_ONKEY1S] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_ONKEY1S_MASK,
	},
	[S5M8763_IRQ_TOPOFFR] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_TOPOFFR_MASK,
	},
	[S5M8763_IRQ_DCINOVPR] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_DCINOVPR_MASK,
	},
	[S5M8763_IRQ_CHGRSTF] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_CHGRSTF_MASK,
	},
	[S5M8763_IRQ_DONER] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_DONER_MASK,
	},
	[S5M8763_IRQ_CHGFAULT] = {
		.reg_offset = 2,
		.mask = S5M8763_IRQ_CHGFAULT_MASK,
	},
	[S5M8763_IRQ_LOBAT1] = {
		.reg_offset = 3,
		.mask = S5M8763_IRQ_LOBAT1_MASK,
	},
	[S5M8763_IRQ_LOBAT2] = {
		.reg_offset = 3,
		.mask = S5M8763_IRQ_LOBAT2_MASK,
	},
};

static const struct regmap_irq_chip s2mps11_irq_chip = {
	.name = "s2mps11",
	.irqs = s2mps11_irqs,
	.num_irqs = ARRAY_SIZE(s2mps11_irqs),
	.num_regs = 3,
	.status_base = S2MPS11_REG_INT1,
	.mask_base = S2MPS11_REG_INT1M,
	.ack_base = S2MPS11_REG_INT1,
};

static const struct regmap_irq_chip s2mps14_irq_chip = {
	.name = "s2mps14",
	.irqs = s2mps14_irqs,
	.num_irqs = ARRAY_SIZE(s2mps14_irqs),
	.num_regs = 3,
	.status_base = S2MPS14_REG_INT1,
	.mask_base = S2MPS14_REG_INT1M,
	.ack_base = S2MPS14_REG_INT1,
};

static const struct regmap_irq_chip s5m8767_irq_chip = {
	.name = "s5m8767",
	.irqs = s5m8767_irqs,
	.num_irqs = ARRAY_SIZE(s5m8767_irqs),
	.num_regs = 3,
	.status_base = S5M8767_REG_INT1,
	.mask_base = S5M8767_REG_INT1M,
	.ack_base = S5M8767_REG_INT1,
};

static const struct regmap_irq_chip s5m8763_irq_chip = {
	.name = "s5m8763",
	.irqs = s5m8763_irqs,
	.num_irqs = ARRAY_SIZE(s5m8763_irqs),
	.num_regs = 4,
	.status_base = S5M8763_REG_IRQ1,
	.mask_base = S5M8763_REG_IRQM1,
	.ack_base = S5M8763_REG_IRQ1,
};

int sec_irq_init(struct sec_pmic_dev *sec_pmic)
{
	int ret = 0;
	int type = sec_pmic->device_type;

	if (!sec_pmic->irq) {
		dev_warn(sec_pmic->dev,
			 "No interrupt specified, no interrupts\n");
		sec_pmic->irq_base = 0;
		return 0;
	}

	switch (type) {
	case S5M8763X:
		ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
				  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				  sec_pmic->irq_base, &s5m8763_irq_chip,
				  &sec_pmic->irq_data);
		break;
	case S5M8767X:
		ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
				  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				  sec_pmic->irq_base, &s5m8767_irq_chip,
				  &sec_pmic->irq_data);
		break;
	case S2MPS11X:
		ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
				  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				  sec_pmic->irq_base, &s2mps11_irq_chip,
				  &sec_pmic->irq_data);
		break;
	case S2MPS14X:
		ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
				  IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
				  sec_pmic->irq_base, &s2mps14_irq_chip,
				  &sec_pmic->irq_data);
		break;
	default:
		dev_err(sec_pmic->dev, "Unknown device type %lu\n",
			sec_pmic->device_type);
		return -EINVAL;
	}

	if (ret != 0) {
		dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
		return ret;
	}

	return 0;
}

void sec_irq_exit(struct sec_pmic_dev *sec_pmic)
{
	regmap_del_irq_chip(sec_pmic->irq, sec_pmic->irq_data);
}
Commit	Line	Data
5ac2ffa7	1	/*
63063bfb	2	* sec-irq.c
5ac2ffa7	3	*
dc691966	4	* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
5ac2ffa7 SK	5	* http://www.samsung.com
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*
	12	*/
	13
	14	#include <linux/device.h>
	15	#include <linux/interrupt.h>
	16	#include <linux/irq.h>
6445b84a SK	17	#include <linux/regmap.h>
6445b84a SK	18
54227bcf SK	19	#include <linux/mfd/samsung/core.h>
54227bcf SK	20	#include <linux/mfd/samsung/irq.h>
6445b84a	21	#include <linux/mfd/samsung/s2mps11.h>
dc691966	22	#include <linux/mfd/samsung/s2mps14.h>
54227bcf SK	23	#include <linux/mfd/samsung/s5m8763.h>
54227bcf SK	24	#include <linux/mfd/samsung/s5m8767.h>
5ac2ffa7	25
a30fffb0	26	static const struct regmap_irq s2mps11_irqs[] = {
6445b84a	27	[S2MPS11_IRQ_PWRONF] = {
5e393a22	28	.reg_offset = 0,
6445b84a SK	29	.mask = S2MPS11_IRQ_PWRONF_MASK,
	30	},
	31	[S2MPS11_IRQ_PWRONR] = {
5e393a22	32	.reg_offset = 0,
6445b84a SK	33	.mask = S2MPS11_IRQ_PWRONR_MASK,
	34	},
	35	[S2MPS11_IRQ_JIGONBF] = {
5e393a22	36	.reg_offset = 0,
6445b84a SK	37	.mask = S2MPS11_IRQ_JIGONBF_MASK,
	38	},
	39	[S2MPS11_IRQ_JIGONBR] = {
5e393a22	40	.reg_offset = 0,
6445b84a SK	41	.mask = S2MPS11_IRQ_JIGONBR_MASK,
	42	},
	43	[S2MPS11_IRQ_ACOKBF] = {
5e393a22	44	.reg_offset = 0,
6445b84a SK	45	.mask = S2MPS11_IRQ_ACOKBF_MASK,
	46	},
	47	[S2MPS11_IRQ_ACOKBR] = {
5e393a22	48	.reg_offset = 0,
6445b84a SK	49	.mask = S2MPS11_IRQ_ACOKBR_MASK,
	50	},
	51	[S2MPS11_IRQ_PWRON1S] = {
5e393a22	52	.reg_offset = 0,
6445b84a SK	53	.mask = S2MPS11_IRQ_PWRON1S_MASK,
	54	},
	55	[S2MPS11_IRQ_MRB] = {
5e393a22	56	.reg_offset = 0,
6445b84a SK	57	.mask = S2MPS11_IRQ_MRB_MASK,
	58	},
	59	[S2MPS11_IRQ_RTC60S] = {
5e393a22	60	.reg_offset = 1,
6445b84a SK	61	.mask = S2MPS11_IRQ_RTC60S_MASK,
6445b84a SK	62	},
67762095	63	[S2MPS11_IRQ_RTCA0] = {
5e393a22	64	.reg_offset = 1,
67762095	65	.mask = S2MPS11_IRQ_RTCA0_MASK,
6445b84a	66	},
67762095	67	[S2MPS11_IRQ_RTCA1] = {
5e393a22	68	.reg_offset = 1,
67762095	69	.mask = S2MPS11_IRQ_RTCA1_MASK,
6445b84a SK	70	},
6445b84a SK	71	[S2MPS11_IRQ_SMPL] = {
5e393a22	72	.reg_offset = 1,
6445b84a SK	73	.mask = S2MPS11_IRQ_SMPL_MASK,
	74	},
	75	[S2MPS11_IRQ_RTC1S] = {
5e393a22	76	.reg_offset = 1,
6445b84a SK	77	.mask = S2MPS11_IRQ_RTC1S_MASK,
	78	},
	79	[S2MPS11_IRQ_WTSR] = {
5e393a22	80	.reg_offset = 1,
6445b84a SK	81	.mask = S2MPS11_IRQ_WTSR_MASK,
	82	},
	83	[S2MPS11_IRQ_INT120C] = {
5e393a22	84	.reg_offset = 2,
6445b84a SK	85	.mask = S2MPS11_IRQ_INT120C_MASK,
	86	},
	87	[S2MPS11_IRQ_INT140C] = {
5e393a22	88	.reg_offset = 2,
6445b84a SK	89	.mask = S2MPS11_IRQ_INT140C_MASK,
6445b84a SK	90	},
5ac2ffa7 SK	91	};
5ac2ffa7 SK	92
dc691966 KK	93	static const struct regmap_irq s2mps14_irqs[] = {
	94	[S2MPS14_IRQ_PWRONF] = {
	95	.reg_offset = 0,
	96	.mask = S2MPS11_IRQ_PWRONF_MASK,
	97	},
	98	[S2MPS14_IRQ_PWRONR] = {
	99	.reg_offset = 0,
	100	.mask = S2MPS11_IRQ_PWRONR_MASK,
	101	},
	102	[S2MPS14_IRQ_JIGONBF] = {
	103	.reg_offset = 0,
	104	.mask = S2MPS11_IRQ_JIGONBF_MASK,
	105	},
	106	[S2MPS14_IRQ_JIGONBR] = {
	107	.reg_offset = 0,
	108	.mask = S2MPS11_IRQ_JIGONBR_MASK,
	109	},
	110	[S2MPS14_IRQ_ACOKBF] = {
	111	.reg_offset = 0,
	112	.mask = S2MPS11_IRQ_ACOKBF_MASK,
	113	},
	114	[S2MPS14_IRQ_ACOKBR] = {
	115	.reg_offset = 0,
	116	.mask = S2MPS11_IRQ_ACOKBR_MASK,
	117	},
	118	[S2MPS14_IRQ_PWRON1S] = {
	119	.reg_offset = 0,
	120	.mask = S2MPS11_IRQ_PWRON1S_MASK,
	121	},
	122	[S2MPS14_IRQ_MRB] = {
	123	.reg_offset = 0,
	124	.mask = S2MPS11_IRQ_MRB_MASK,
	125	},
	126	[S2MPS14_IRQ_RTC60S] = {
	127	.reg_offset = 1,
	128	.mask = S2MPS11_IRQ_RTC60S_MASK,
	129	},
	130	[S2MPS14_IRQ_RTCA1] = {
	131	.reg_offset = 1,
	132	.mask = S2MPS11_IRQ_RTCA1_MASK,
	133	},
	134	[S2MPS14_IRQ_RTCA0] = {
	135	.reg_offset = 1,
	136	.mask = S2MPS11_IRQ_RTCA0_MASK,
	137	},
	138	[S2MPS14_IRQ_SMPL] = {
	139	.reg_offset = 1,
	140	.mask = S2MPS11_IRQ_SMPL_MASK,
	141	},
	142	[S2MPS14_IRQ_RTC1S] = {
	143	.reg_offset = 1,
	144	.mask = S2MPS11_IRQ_RTC1S_MASK,
	145	},
	146	[S2MPS14_IRQ_WTSR] = {
	147	.reg_offset = 1,
	148	.mask = S2MPS11_IRQ_WTSR_MASK,
	149	},
	150	[S2MPS14_IRQ_INT120C] = {
	151	.reg_offset = 2,
	152	.mask = S2MPS11_IRQ_INT120C_MASK,
	153	},
	154	[S2MPS14_IRQ_INT140C] = {
	155	.reg_offset = 2,
	156	.mask = S2MPS11_IRQ_INT140C_MASK,
157	},
158	[S2MPS14_IRQ_TSD] = {
159	.reg_offset = 2,
160	.mask = S2MPS14_IRQ_TSD_MASK,
161	},
162	};
6445b84a	163
a30fffb0	164	static const struct regmap_irq s5m8767_irqs[] = {
5ac2ffa7	165	[S5M8767_IRQ_PWRR] = {
5e393a22	166	.reg_offset = 0,
5ac2ffa7 SK	167	.mask = S5M8767_IRQ_PWRR_MASK,
	168	},
	169	[S5M8767_IRQ_PWRF] = {
5e393a22	170	.reg_offset = 0,
5ac2ffa7 SK	171	.mask = S5M8767_IRQ_PWRF_MASK,
	172	},
	173	[S5M8767_IRQ_PWR1S] = {
5e393a22	174	.reg_offset = 0,
5ac2ffa7 SK	175	.mask = S5M8767_IRQ_PWR1S_MASK,
	176	},
	177	[S5M8767_IRQ_JIGR] = {
5e393a22	178	.reg_offset = 0,
5ac2ffa7 SK	179	.mask = S5M8767_IRQ_JIGR_MASK,
	180	},
	181	[S5M8767_IRQ_JIGF] = {
5e393a22	182	.reg_offset = 0,
5ac2ffa7 SK	183	.mask = S5M8767_IRQ_JIGF_MASK,
	184	},
	185	[S5M8767_IRQ_LOWBAT2] = {
5e393a22	186	.reg_offset = 0,
5ac2ffa7 SK	187	.mask = S5M8767_IRQ_LOWBAT2_MASK,
	188	},
	189	[S5M8767_IRQ_LOWBAT1] = {
5e393a22	190	.reg_offset = 0,
5ac2ffa7 SK	191	.mask = S5M8767_IRQ_LOWBAT1_MASK,
	192	},
	193	[S5M8767_IRQ_MRB] = {
5e393a22	194	.reg_offset = 1,
5ac2ffa7 SK	195	.mask = S5M8767_IRQ_MRB_MASK,
	196	},
	197	[S5M8767_IRQ_DVSOK2] = {
5e393a22	198	.reg_offset = 1,
5ac2ffa7 SK	199	.mask = S5M8767_IRQ_DVSOK2_MASK,
	200	},
	201	[S5M8767_IRQ_DVSOK3] = {
5e393a22	202	.reg_offset = 1,
5ac2ffa7 SK	203	.mask = S5M8767_IRQ_DVSOK3_MASK,
	204	},
	205	[S5M8767_IRQ_DVSOK4] = {
5e393a22	206	.reg_offset = 1,
5ac2ffa7 SK	207	.mask = S5M8767_IRQ_DVSOK4_MASK,
	208	},
	209	[S5M8767_IRQ_RTC60S] = {
5e393a22	210	.reg_offset = 2,
5ac2ffa7 SK	211	.mask = S5M8767_IRQ_RTC60S_MASK,
	212	},
	213	[S5M8767_IRQ_RTCA1] = {
5e393a22	214	.reg_offset = 2,
5ac2ffa7 SK	215	.mask = S5M8767_IRQ_RTCA1_MASK,
	216	},
	217	[S5M8767_IRQ_RTCA2] = {
5e393a22	218	.reg_offset = 2,
5ac2ffa7 SK	219	.mask = S5M8767_IRQ_RTCA2_MASK,
	220	},
	221	[S5M8767_IRQ_SMPL] = {
5e393a22	222	.reg_offset = 2,
5ac2ffa7 SK	223	.mask = S5M8767_IRQ_SMPL_MASK,
	224	},
	225	[S5M8767_IRQ_RTC1S] = {
5e393a22	226	.reg_offset = 2,
5ac2ffa7 SK	227	.mask = S5M8767_IRQ_RTC1S_MASK,
	228	},
	229	[S5M8767_IRQ_WTSR] = {
5e393a22	230	.reg_offset = 2,
5ac2ffa7 SK	231	.mask = S5M8767_IRQ_WTSR_MASK,
	232	},
	233	};
	234
a30fffb0	235	static const struct regmap_irq s5m8763_irqs[] = {
5ac2ffa7	236	[S5M8763_IRQ_DCINF] = {
5e393a22	237	.reg_offset = 0,
5ac2ffa7 SK	238	.mask = S5M8763_IRQ_DCINF_MASK,
	239	},
	240	[S5M8763_IRQ_DCINR] = {
5e393a22	241	.reg_offset = 0,
5ac2ffa7 SK	242	.mask = S5M8763_IRQ_DCINR_MASK,
	243	},
	244	[S5M8763_IRQ_JIGF] = {
5e393a22	245	.reg_offset = 0,
5ac2ffa7 SK	246	.mask = S5M8763_IRQ_JIGF_MASK,
	247	},
	248	[S5M8763_IRQ_JIGR] = {
5e393a22	249	.reg_offset = 0,
5ac2ffa7 SK	250	.mask = S5M8763_IRQ_JIGR_MASK,
	251	},
	252	[S5M8763_IRQ_PWRONF] = {
5e393a22	253	.reg_offset = 0,
5ac2ffa7 SK	254	.mask = S5M8763_IRQ_PWRONF_MASK,
	255	},
	256	[S5M8763_IRQ_PWRONR] = {
5e393a22	257	.reg_offset = 0,
5ac2ffa7 SK	258	.mask = S5M8763_IRQ_PWRONR_MASK,
	259	},
	260	[S5M8763_IRQ_WTSREVNT] = {
5e393a22	261	.reg_offset = 1,
5ac2ffa7 SK	262	.mask = S5M8763_IRQ_WTSREVNT_MASK,
	263	},
	264	[S5M8763_IRQ_SMPLEVNT] = {
5e393a22	265	.reg_offset = 1,
5ac2ffa7 SK	266	.mask = S5M8763_IRQ_SMPLEVNT_MASK,
	267	},
	268	[S5M8763_IRQ_ALARM1] = {
5e393a22	269	.reg_offset = 1,
5ac2ffa7 SK	270	.mask = S5M8763_IRQ_ALARM1_MASK,
	271	},
	272	[S5M8763_IRQ_ALARM0] = {
5e393a22	273	.reg_offset = 1,
5ac2ffa7 SK	274	.mask = S5M8763_IRQ_ALARM0_MASK,
	275	},
	276	[S5M8763_IRQ_ONKEY1S] = {
5e393a22	277	.reg_offset = 2,
5ac2ffa7 SK	278	.mask = S5M8763_IRQ_ONKEY1S_MASK,
	279	},
	280	[S5M8763_IRQ_TOPOFFR] = {
5e393a22	281	.reg_offset = 2,
5ac2ffa7 SK	282	.mask = S5M8763_IRQ_TOPOFFR_MASK,
	283	},
	284	[S5M8763_IRQ_DCINOVPR] = {
5e393a22	285	.reg_offset = 2,
5ac2ffa7 SK	286	.mask = S5M8763_IRQ_DCINOVPR_MASK,
	287	},
	288	[S5M8763_IRQ_CHGRSTF] = {
5e393a22	289	.reg_offset = 2,
5ac2ffa7 SK	290	.mask = S5M8763_IRQ_CHGRSTF_MASK,
	291	},
	292	[S5M8763_IRQ_DONER] = {
5e393a22	293	.reg_offset = 2,
5ac2ffa7 SK	294	.mask = S5M8763_IRQ_DONER_MASK,
	295	},
	296	[S5M8763_IRQ_CHGFAULT] = {
5e393a22	297	.reg_offset = 2,
5ac2ffa7 SK	298	.mask = S5M8763_IRQ_CHGFAULT_MASK,
	299	},
	300	[S5M8763_IRQ_LOBAT1] = {
5e393a22	301	.reg_offset = 3,
5ac2ffa7 SK	302	.mask = S5M8763_IRQ_LOBAT1_MASK,
	303	},
	304	[S5M8763_IRQ_LOBAT2] = {
5e393a22	305	.reg_offset = 3,
5ac2ffa7 SK	306	.mask = S5M8763_IRQ_LOBAT2_MASK,
	307	},
	308	};
	309
a30fffb0	310	static const struct regmap_irq_chip s2mps11_irq_chip = {
6445b84a SK	311	.name = "s2mps11",
	312	.irqs = s2mps11_irqs,
	313	.num_irqs = ARRAY_SIZE(s2mps11_irqs),
	314	.num_regs = 3,
	315	.status_base = S2MPS11_REG_INT1,
	316	.mask_base = S2MPS11_REG_INT1M,
	317	.ack_base = S2MPS11_REG_INT1,
	318	};
5ac2ffa7	319
dc691966 KK	320	static const struct regmap_irq_chip s2mps14_irq_chip = {
	321	.name = "s2mps14",
	322	.irqs = s2mps14_irqs,
	323	.num_irqs = ARRAY_SIZE(s2mps14_irqs),
	324	.num_regs = 3,
	325	.status_base = S2MPS14_REG_INT1,
	326	.mask_base = S2MPS14_REG_INT1M,
	327	.ack_base = S2MPS14_REG_INT1,
	328	};
	329
a30fffb0	330	static const struct regmap_irq_chip s5m8767_irq_chip = {
5ac2ffa7	331	.name = "s5m8767",
6445b84a SK	332	.irqs = s5m8767_irqs,
	333	.num_irqs = ARRAY_SIZE(s5m8767_irqs),
	334	.num_regs = 3,
	335	.status_base = S5M8767_REG_INT1,
	336	.mask_base = S5M8767_REG_INT1M,
	337	.ack_base = S5M8767_REG_INT1,
5ac2ffa7 SK	338	};
5ac2ffa7 SK	339
a30fffb0	340	static const struct regmap_irq_chip s5m8763_irq_chip = {
5ac2ffa7	341	.name = "s5m8763",
6445b84a SK	342	.irqs = s5m8763_irqs,
	343	.num_irqs = ARRAY_SIZE(s5m8763_irqs),
	344	.num_regs = 4,
	345	.status_base = S5M8763_REG_IRQ1,
	346	.mask_base = S5M8763_REG_IRQM1,
	347	.ack_base = S5M8763_REG_IRQ1,
5ac2ffa7 SK	348	};
5ac2ffa7 SK	349
63063bfb	350	int sec_irq_init(struct sec_pmic_dev *sec_pmic)
5ac2ffa7	351	{
5ac2ffa7	352	int ret = 0;
63063bfb	353	int type = sec_pmic->device_type;
5ac2ffa7	354
63063bfb SK	355	if (!sec_pmic->irq) {
63063bfb SK	356	dev_warn(sec_pmic->dev,
5ac2ffa7	357	"No interrupt specified, no interrupts\n");
63063bfb	358	sec_pmic->irq_base = 0;
5ac2ffa7 SK	359	return 0;
	360	}
	361
5ac2ffa7 SK	362	switch (type) {
5ac2ffa7 SK	363	case S5M8763X:
3e1e4a5f	364	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
6445b84a SK	365	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	366	sec_pmic->irq_base, &s5m8763_irq_chip,
	367	&sec_pmic->irq_data);
5ac2ffa7 SK	368	break;
5ac2ffa7 SK	369	case S5M8767X:
3e1e4a5f	370	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
6445b84a SK	371	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	372	sec_pmic->irq_base, &s5m8767_irq_chip,
	373	&sec_pmic->irq_data);
5ac2ffa7	374	break;
6445b84a	375	case S2MPS11X:
3e1e4a5f	376	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
6445b84a SK	377	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	378	sec_pmic->irq_base, &s2mps11_irq_chip,
	379	&sec_pmic->irq_data);
5ac2ffa7	380	break;
dc691966 KK	381	case S2MPS14X:
	382	ret = regmap_add_irq_chip(sec_pmic->regmap_pmic, sec_pmic->irq,
	383	IRQF_TRIGGER_FALLING \| IRQF_ONESHOT,
	384	sec_pmic->irq_base, &s2mps14_irq_chip,
	385	&sec_pmic->irq_data);
	386	break;
5ac2ffa7	387	default:
9549b5ff	388	dev_err(sec_pmic->dev, "Unknown device type %lu\n",
6445b84a SK	389	sec_pmic->device_type);
6445b84a SK	390	return -EINVAL;
5ac2ffa7 SK	391	}
5ac2ffa7 SK	392
6445b84a SK	393	if (ret != 0) {
6445b84a SK	394	dev_err(sec_pmic->dev, "Failed to register IRQ chip: %d\n", ret);
c7a1fcf3 JC	395	return ret;
c7a1fcf3 JC	396	}
5ac2ffa7 SK	397
	398	return 0;
	399	}
	400
63063bfb	401	void sec_irq_exit(struct sec_pmic_dev *sec_pmic)
5ac2ffa7	402	{
6445b84a	403	regmap_del_irq_chip(sec_pmic->irq, sec_pmic->irq_data);
5ac2ffa7	404	}