Commit | Line | Data |
---|---|---|
ada8a8a1 WW |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
3 | * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG <wei_wang@realsil.com.cn> | |
20 | * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China | |
21 | */ | |
22 | ||
23 | #include <linux/pci.h> | |
24 | #include <linux/module.h> | |
aec17ea1 | 25 | #include <linux/slab.h> |
ada8a8a1 WW |
26 | #include <linux/dma-mapping.h> |
27 | #include <linux/highmem.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/idr.h> | |
31 | #include <linux/platform_device.h> | |
32 | #include <linux/mfd/core.h> | |
33 | #include <linux/mfd/rtsx_pci.h> | |
34 | #include <asm/unaligned.h> | |
35 | ||
36 | #include "rtsx_pcr.h" | |
37 | ||
38 | static bool msi_en = true; | |
39 | module_param(msi_en, bool, S_IRUGO | S_IWUSR); | |
40 | MODULE_PARM_DESC(msi_en, "Enable MSI"); | |
41 | ||
42 | static DEFINE_IDR(rtsx_pci_idr); | |
43 | static DEFINE_SPINLOCK(rtsx_pci_lock); | |
44 | ||
45 | static struct mfd_cell rtsx_pcr_cells[] = { | |
46 | [RTSX_SD_CARD] = { | |
47 | .name = DRV_NAME_RTSX_PCI_SDMMC, | |
48 | }, | |
49 | [RTSX_MS_CARD] = { | |
50 | .name = DRV_NAME_RTSX_PCI_MS, | |
51 | }, | |
52 | }; | |
53 | ||
54 | static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = { | |
55 | { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 }, | |
56 | { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 }, | |
57 | { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 }, | |
58 | { 0, } | |
59 | }; | |
60 | ||
61 | MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); | |
62 | ||
63 | void rtsx_pci_start_run(struct rtsx_pcr *pcr) | |
64 | { | |
65 | /* If pci device removed, don't queue idle work any more */ | |
66 | if (pcr->remove_pci) | |
67 | return; | |
68 | ||
69 | if (pcr->state != PDEV_STAT_RUN) { | |
70 | pcr->state = PDEV_STAT_RUN; | |
71 | if (pcr->ops->enable_auto_blink) | |
72 | pcr->ops->enable_auto_blink(pcr); | |
73 | } | |
74 | ||
75 | mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200)); | |
76 | } | |
77 | EXPORT_SYMBOL_GPL(rtsx_pci_start_run); | |
78 | ||
79 | int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) | |
80 | { | |
81 | int i; | |
82 | u32 val = HAIMR_WRITE_START; | |
83 | ||
84 | val |= (u32)(addr & 0x3FFF) << 16; | |
85 | val |= (u32)mask << 8; | |
86 | val |= (u32)data; | |
87 | ||
88 | rtsx_pci_writel(pcr, RTSX_HAIMR, val); | |
89 | ||
90 | for (i = 0; i < MAX_RW_REG_CNT; i++) { | |
91 | val = rtsx_pci_readl(pcr, RTSX_HAIMR); | |
92 | if ((val & HAIMR_TRANS_END) == 0) { | |
93 | if (data != (u8)val) | |
94 | return -EIO; | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
99 | return -ETIMEDOUT; | |
100 | } | |
101 | EXPORT_SYMBOL_GPL(rtsx_pci_write_register); | |
102 | ||
103 | int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data) | |
104 | { | |
105 | u32 val = HAIMR_READ_START; | |
106 | int i; | |
107 | ||
108 | val |= (u32)(addr & 0x3FFF) << 16; | |
109 | rtsx_pci_writel(pcr, RTSX_HAIMR, val); | |
110 | ||
111 | for (i = 0; i < MAX_RW_REG_CNT; i++) { | |
112 | val = rtsx_pci_readl(pcr, RTSX_HAIMR); | |
113 | if ((val & HAIMR_TRANS_END) == 0) | |
114 | break; | |
115 | } | |
116 | ||
117 | if (i >= MAX_RW_REG_CNT) | |
118 | return -ETIMEDOUT; | |
119 | ||
120 | if (data) | |
121 | *data = (u8)(val & 0xFF); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | EXPORT_SYMBOL_GPL(rtsx_pci_read_register); | |
126 | ||
127 | int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) | |
128 | { | |
129 | int err, i, finished = 0; | |
130 | u8 tmp; | |
131 | ||
132 | rtsx_pci_init_cmd(pcr); | |
133 | ||
134 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val); | |
135 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8)); | |
136 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); | |
137 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81); | |
138 | ||
139 | err = rtsx_pci_send_cmd(pcr, 100); | |
140 | if (err < 0) | |
141 | return err; | |
142 | ||
143 | for (i = 0; i < 100000; i++) { | |
144 | err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); | |
145 | if (err < 0) | |
146 | return err; | |
147 | ||
148 | if (!(tmp & 0x80)) { | |
149 | finished = 1; | |
150 | break; | |
151 | } | |
152 | } | |
153 | ||
154 | if (!finished) | |
155 | return -ETIMEDOUT; | |
156 | ||
157 | return 0; | |
158 | } | |
159 | EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register); | |
160 | ||
161 | int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) | |
162 | { | |
163 | int err, i, finished = 0; | |
164 | u16 data; | |
165 | u8 *ptr, tmp; | |
166 | ||
167 | rtsx_pci_init_cmd(pcr); | |
168 | ||
169 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); | |
170 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80); | |
171 | ||
172 | err = rtsx_pci_send_cmd(pcr, 100); | |
173 | if (err < 0) | |
174 | return err; | |
175 | ||
176 | for (i = 0; i < 100000; i++) { | |
177 | err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); | |
178 | if (err < 0) | |
179 | return err; | |
180 | ||
181 | if (!(tmp & 0x80)) { | |
182 | finished = 1; | |
183 | break; | |
184 | } | |
185 | } | |
186 | ||
187 | if (!finished) | |
188 | return -ETIMEDOUT; | |
189 | ||
190 | rtsx_pci_init_cmd(pcr); | |
191 | ||
192 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0); | |
193 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0); | |
194 | ||
195 | err = rtsx_pci_send_cmd(pcr, 100); | |
196 | if (err < 0) | |
197 | return err; | |
198 | ||
199 | ptr = rtsx_pci_get_cmd_data(pcr); | |
200 | data = ((u16)ptr[1] << 8) | ptr[0]; | |
201 | ||
202 | if (val) | |
203 | *val = data; | |
204 | ||
205 | return 0; | |
206 | } | |
207 | EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register); | |
208 | ||
209 | void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr) | |
210 | { | |
211 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); | |
212 | rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); | |
213 | ||
214 | rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); | |
215 | rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); | |
216 | } | |
217 | EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd); | |
218 | ||
219 | void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, | |
220 | u8 cmd_type, u16 reg_addr, u8 mask, u8 data) | |
221 | { | |
222 | unsigned long flags; | |
223 | u32 val = 0; | |
224 | u32 *ptr = (u32 *)(pcr->host_cmds_ptr); | |
225 | ||
226 | val |= (u32)(cmd_type & 0x03) << 30; | |
227 | val |= (u32)(reg_addr & 0x3FFF) << 16; | |
228 | val |= (u32)mask << 8; | |
229 | val |= (u32)data; | |
230 | ||
231 | spin_lock_irqsave(&pcr->lock, flags); | |
232 | ptr += pcr->ci; | |
233 | if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) { | |
234 | put_unaligned_le32(val, ptr); | |
235 | ptr++; | |
236 | pcr->ci++; | |
237 | } | |
238 | spin_unlock_irqrestore(&pcr->lock, flags); | |
239 | } | |
240 | EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd); | |
241 | ||
242 | void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr) | |
243 | { | |
244 | u32 val = 1 << 31; | |
245 | ||
246 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); | |
247 | ||
248 | val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; | |
249 | /* Hardware Auto Response */ | |
250 | val |= 0x40000000; | |
251 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); | |
252 | } | |
253 | EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait); | |
254 | ||
255 | int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout) | |
256 | { | |
257 | struct completion trans_done; | |
258 | u32 val = 1 << 31; | |
259 | long timeleft; | |
260 | unsigned long flags; | |
261 | int err = 0; | |
262 | ||
263 | spin_lock_irqsave(&pcr->lock, flags); | |
264 | ||
265 | /* set up data structures for the wakeup system */ | |
266 | pcr->done = &trans_done; | |
267 | pcr->trans_result = TRANS_NOT_READY; | |
268 | init_completion(&trans_done); | |
269 | ||
270 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); | |
271 | ||
272 | val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; | |
273 | /* Hardware Auto Response */ | |
274 | val |= 0x40000000; | |
275 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); | |
276 | ||
277 | spin_unlock_irqrestore(&pcr->lock, flags); | |
278 | ||
279 | /* Wait for TRANS_OK_INT */ | |
280 | timeleft = wait_for_completion_interruptible_timeout( | |
281 | &trans_done, msecs_to_jiffies(timeout)); | |
282 | if (timeleft <= 0) { | |
283 | dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n", | |
284 | __func__, __LINE__); | |
285 | err = -ETIMEDOUT; | |
286 | goto finish_send_cmd; | |
287 | } | |
288 | ||
289 | spin_lock_irqsave(&pcr->lock, flags); | |
290 | if (pcr->trans_result == TRANS_RESULT_FAIL) | |
291 | err = -EINVAL; | |
292 | else if (pcr->trans_result == TRANS_RESULT_OK) | |
293 | err = 0; | |
294 | else if (pcr->trans_result == TRANS_NO_DEVICE) | |
295 | err = -ENODEV; | |
296 | spin_unlock_irqrestore(&pcr->lock, flags); | |
297 | ||
298 | finish_send_cmd: | |
299 | spin_lock_irqsave(&pcr->lock, flags); | |
300 | pcr->done = NULL; | |
301 | spin_unlock_irqrestore(&pcr->lock, flags); | |
302 | ||
303 | if ((err < 0) && (err != -ENODEV)) | |
304 | rtsx_pci_stop_cmd(pcr); | |
305 | ||
306 | if (pcr->finish_me) | |
307 | complete(pcr->finish_me); | |
308 | ||
309 | return err; | |
310 | } | |
311 | EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd); | |
312 | ||
313 | static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, | |
314 | dma_addr_t addr, unsigned int len, int end) | |
315 | { | |
316 | u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; | |
317 | u64 val; | |
318 | u8 option = SG_VALID | SG_TRANS_DATA; | |
319 | ||
320 | dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n", | |
321 | (unsigned int)addr, len); | |
322 | ||
323 | if (end) | |
324 | option |= SG_END; | |
325 | val = ((u64)addr << 32) | ((u64)len << 12) | option; | |
326 | ||
327 | put_unaligned_le64(val, ptr); | |
328 | ptr++; | |
329 | pcr->sgi++; | |
330 | } | |
331 | ||
332 | int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
333 | int num_sg, bool read, int timeout) | |
334 | { | |
335 | struct completion trans_done; | |
336 | u8 dir; | |
337 | int err = 0, i, count; | |
338 | long timeleft; | |
339 | unsigned long flags; | |
340 | struct scatterlist *sg; | |
341 | enum dma_data_direction dma_dir; | |
342 | u32 val; | |
343 | dma_addr_t addr; | |
344 | unsigned int len; | |
345 | ||
346 | dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg); | |
347 | ||
348 | /* don't transfer data during abort processing */ | |
349 | if (pcr->remove_pci) | |
350 | return -EINVAL; | |
351 | ||
352 | if ((sglist == NULL) || (num_sg <= 0)) | |
353 | return -EINVAL; | |
354 | ||
355 | if (read) { | |
356 | dir = DEVICE_TO_HOST; | |
357 | dma_dir = DMA_FROM_DEVICE; | |
358 | } else { | |
359 | dir = HOST_TO_DEVICE; | |
360 | dma_dir = DMA_TO_DEVICE; | |
361 | } | |
362 | ||
363 | count = dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir); | |
364 | if (count < 1) { | |
365 | dev_err(&(pcr->pci->dev), "scatterlist map failed\n"); | |
366 | return -EINVAL; | |
367 | } | |
368 | dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count); | |
369 | ||
370 | val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; | |
371 | pcr->sgi = 0; | |
372 | for_each_sg(sglist, sg, count, i) { | |
373 | addr = sg_dma_address(sg); | |
374 | len = sg_dma_len(sg); | |
375 | rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1); | |
376 | } | |
377 | ||
378 | spin_lock_irqsave(&pcr->lock, flags); | |
379 | ||
380 | pcr->done = &trans_done; | |
381 | pcr->trans_result = TRANS_NOT_READY; | |
382 | init_completion(&trans_done); | |
383 | rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr); | |
384 | rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); | |
385 | ||
386 | spin_unlock_irqrestore(&pcr->lock, flags); | |
387 | ||
388 | timeleft = wait_for_completion_interruptible_timeout( | |
389 | &trans_done, msecs_to_jiffies(timeout)); | |
390 | if (timeleft <= 0) { | |
391 | dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n", | |
392 | __func__, __LINE__); | |
393 | err = -ETIMEDOUT; | |
394 | goto out; | |
395 | } | |
396 | ||
397 | spin_lock_irqsave(&pcr->lock, flags); | |
398 | ||
399 | if (pcr->trans_result == TRANS_RESULT_FAIL) | |
400 | err = -EINVAL; | |
401 | else if (pcr->trans_result == TRANS_NO_DEVICE) | |
402 | err = -ENODEV; | |
403 | ||
404 | spin_unlock_irqrestore(&pcr->lock, flags); | |
405 | ||
406 | out: | |
407 | spin_lock_irqsave(&pcr->lock, flags); | |
408 | pcr->done = NULL; | |
409 | spin_unlock_irqrestore(&pcr->lock, flags); | |
410 | ||
411 | dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dma_dir); | |
412 | ||
413 | if ((err < 0) && (err != -ENODEV)) | |
414 | rtsx_pci_stop_cmd(pcr); | |
415 | ||
416 | if (pcr->finish_me) | |
417 | complete(pcr->finish_me); | |
418 | ||
419 | return err; | |
420 | } | |
421 | EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data); | |
422 | ||
423 | int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) | |
424 | { | |
425 | int err; | |
426 | int i, j; | |
427 | u16 reg; | |
428 | u8 *ptr; | |
429 | ||
430 | if (buf_len > 512) | |
431 | buf_len = 512; | |
432 | ||
433 | ptr = buf; | |
434 | reg = PPBUF_BASE2; | |
435 | for (i = 0; i < buf_len / 256; i++) { | |
436 | rtsx_pci_init_cmd(pcr); | |
437 | ||
438 | for (j = 0; j < 256; j++) | |
439 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); | |
440 | ||
441 | err = rtsx_pci_send_cmd(pcr, 250); | |
442 | if (err < 0) | |
443 | return err; | |
444 | ||
445 | memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256); | |
446 | ptr += 256; | |
447 | } | |
448 | ||
449 | if (buf_len % 256) { | |
450 | rtsx_pci_init_cmd(pcr); | |
451 | ||
452 | for (j = 0; j < buf_len % 256; j++) | |
453 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); | |
454 | ||
455 | err = rtsx_pci_send_cmd(pcr, 250); | |
456 | if (err < 0) | |
457 | return err; | |
458 | } | |
459 | ||
460 | memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf); | |
465 | ||
466 | int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) | |
467 | { | |
468 | int err; | |
469 | int i, j; | |
470 | u16 reg; | |
471 | u8 *ptr; | |
472 | ||
473 | if (buf_len > 512) | |
474 | buf_len = 512; | |
475 | ||
476 | ptr = buf; | |
477 | reg = PPBUF_BASE2; | |
478 | for (i = 0; i < buf_len / 256; i++) { | |
479 | rtsx_pci_init_cmd(pcr); | |
480 | ||
481 | for (j = 0; j < 256; j++) { | |
482 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
483 | reg++, 0xFF, *ptr); | |
484 | ptr++; | |
485 | } | |
486 | ||
487 | err = rtsx_pci_send_cmd(pcr, 250); | |
488 | if (err < 0) | |
489 | return err; | |
490 | } | |
491 | ||
492 | if (buf_len % 256) { | |
493 | rtsx_pci_init_cmd(pcr); | |
494 | ||
495 | for (j = 0; j < buf_len % 256; j++) { | |
496 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
497 | reg++, 0xFF, *ptr); | |
498 | ptr++; | |
499 | } | |
500 | ||
501 | err = rtsx_pci_send_cmd(pcr, 250); | |
502 | if (err < 0) | |
503 | return err; | |
504 | } | |
505 | ||
506 | return 0; | |
507 | } | |
508 | EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf); | |
509 | ||
510 | static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl) | |
511 | { | |
512 | int err; | |
513 | ||
514 | rtsx_pci_init_cmd(pcr); | |
515 | ||
516 | while (*tbl & 0xFFFF0000) { | |
517 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
518 | (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); | |
519 | tbl++; | |
520 | } | |
521 | ||
522 | err = rtsx_pci_send_cmd(pcr, 100); | |
523 | if (err < 0) | |
524 | return err; | |
525 | ||
526 | return 0; | |
527 | } | |
528 | ||
529 | int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card) | |
530 | { | |
531 | const u32 *tbl; | |
532 | ||
533 | if (card == RTSX_SD_CARD) | |
534 | tbl = pcr->sd_pull_ctl_enable_tbl; | |
535 | else if (card == RTSX_MS_CARD) | |
536 | tbl = pcr->ms_pull_ctl_enable_tbl; | |
537 | else | |
538 | return -EINVAL; | |
539 | ||
540 | return rtsx_pci_set_pull_ctl(pcr, tbl); | |
541 | } | |
542 | EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable); | |
543 | ||
544 | int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card) | |
545 | { | |
546 | const u32 *tbl; | |
547 | ||
548 | if (card == RTSX_SD_CARD) | |
549 | tbl = pcr->sd_pull_ctl_disable_tbl; | |
550 | else if (card == RTSX_MS_CARD) | |
551 | tbl = pcr->ms_pull_ctl_disable_tbl; | |
552 | else | |
553 | return -EINVAL; | |
554 | ||
555 | ||
556 | return rtsx_pci_set_pull_ctl(pcr, tbl); | |
557 | } | |
558 | EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable); | |
559 | ||
560 | static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr) | |
561 | { | |
562 | pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN; | |
563 | ||
564 | if (pcr->num_slots > 1) | |
565 | pcr->bier |= MS_INT_EN; | |
566 | ||
567 | /* Enable Bus Interrupt */ | |
568 | rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier); | |
569 | ||
570 | dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier); | |
571 | } | |
572 | ||
573 | static inline u8 double_ssc_depth(u8 depth) | |
574 | { | |
575 | return ((depth > 1) ? (depth - 1) : depth); | |
576 | } | |
577 | ||
578 | static u8 revise_ssc_depth(u8 ssc_depth, u8 div) | |
579 | { | |
580 | if (div > CLK_DIV_1) { | |
581 | if (ssc_depth > (div - 1)) | |
582 | ssc_depth -= (div - 1); | |
583 | else | |
584 | ssc_depth = SSC_DEPTH_4M; | |
585 | } | |
586 | ||
587 | return ssc_depth; | |
588 | } | |
589 | ||
590 | int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, | |
591 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) | |
592 | { | |
593 | int err, clk; | |
594 | u8 N, min_N, max_N, clk_divider; | |
595 | u8 mcu_cnt, div, max_div; | |
596 | u8 depth[] = { | |
597 | [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, | |
598 | [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M, | |
599 | [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M, | |
600 | [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K, | |
601 | [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K, | |
602 | }; | |
603 | ||
604 | if (initial_mode) { | |
605 | /* We use 250k(around) here, in initial stage */ | |
606 | clk_divider = SD_CLK_DIVIDE_128; | |
607 | card_clock = 30000000; | |
608 | } else { | |
609 | clk_divider = SD_CLK_DIVIDE_0; | |
610 | } | |
611 | err = rtsx_pci_write_register(pcr, SD_CFG1, | |
612 | SD_CLK_DIVIDE_MASK, clk_divider); | |
613 | if (err < 0) | |
614 | return err; | |
615 | ||
616 | card_clock /= 1000000; | |
617 | dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock); | |
618 | ||
619 | min_N = 80; | |
620 | max_N = 208; | |
621 | max_div = CLK_DIV_8; | |
622 | ||
623 | clk = card_clock; | |
624 | if (!initial_mode && double_clk) | |
625 | clk = card_clock * 2; | |
626 | dev_dbg(&(pcr->pci->dev), | |
627 | "Internal SSC clock: %dMHz (cur_clock = %d)\n", | |
628 | clk, pcr->cur_clock); | |
629 | ||
630 | if (clk == pcr->cur_clock) | |
631 | return 0; | |
632 | ||
ab4e8f8b WW |
633 | if (pcr->ops->conv_clk_and_div_n) |
634 | N = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); | |
635 | else | |
636 | N = (u8)(clk - 2); | |
ada8a8a1 WW |
637 | if ((clk <= 2) || (N > max_N)) |
638 | return -EINVAL; | |
639 | ||
640 | mcu_cnt = (u8)(125/clk + 3); | |
641 | if (mcu_cnt > 15) | |
642 | mcu_cnt = 15; | |
643 | ||
644 | /* Make sure that the SSC clock div_n is equal or greater than min_N */ | |
645 | div = CLK_DIV_1; | |
646 | while ((N < min_N) && (div < max_div)) { | |
ab4e8f8b WW |
647 | if (pcr->ops->conv_clk_and_div_n) { |
648 | int dbl_clk = pcr->ops->conv_clk_and_div_n(N, | |
649 | DIV_N_TO_CLK) * 2; | |
650 | N = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, | |
651 | CLK_TO_DIV_N); | |
652 | } else { | |
653 | N = (N + 2) * 2 - 2; | |
654 | } | |
ada8a8a1 WW |
655 | div++; |
656 | } | |
657 | dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div); | |
658 | ||
659 | ssc_depth = depth[ssc_depth]; | |
660 | if (double_clk) | |
661 | ssc_depth = double_ssc_depth(ssc_depth); | |
662 | ||
663 | ssc_depth = revise_ssc_depth(ssc_depth, div); | |
664 | dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth); | |
665 | ||
666 | rtsx_pci_init_cmd(pcr); | |
667 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
668 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
669 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, | |
670 | 0xFF, (div << 4) | mcu_cnt); | |
671 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); | |
672 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, | |
673 | SSC_DEPTH_MASK, ssc_depth); | |
674 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N); | |
675 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); | |
676 | if (vpclk) { | |
677 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, | |
678 | PHASE_NOT_RESET, 0); | |
679 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, | |
680 | PHASE_NOT_RESET, PHASE_NOT_RESET); | |
681 | } | |
682 | ||
683 | err = rtsx_pci_send_cmd(pcr, 2000); | |
684 | if (err < 0) | |
685 | return err; | |
686 | ||
687 | /* Wait SSC clock stable */ | |
688 | udelay(10); | |
689 | err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); | |
690 | if (err < 0) | |
691 | return err; | |
692 | ||
693 | pcr->cur_clock = clk; | |
694 | return 0; | |
695 | } | |
696 | EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock); | |
697 | ||
698 | int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card) | |
699 | { | |
700 | if (pcr->ops->card_power_on) | |
701 | return pcr->ops->card_power_on(pcr, card); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on); | |
706 | ||
707 | int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card) | |
708 | { | |
709 | if (pcr->ops->card_power_off) | |
710 | return pcr->ops->card_power_off(pcr, card); | |
711 | ||
712 | return 0; | |
713 | } | |
714 | EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off); | |
715 | ||
d817ac4e WW |
716 | int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) |
717 | { | |
718 | if (pcr->ops->switch_output_voltage) | |
719 | return pcr->ops->switch_output_voltage(pcr, voltage); | |
720 | ||
721 | return 0; | |
722 | } | |
723 | EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage); | |
724 | ||
ada8a8a1 WW |
725 | unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr) |
726 | { | |
727 | unsigned int val; | |
728 | ||
729 | val = rtsx_pci_readl(pcr, RTSX_BIPR); | |
730 | if (pcr->ops->cd_deglitch) | |
731 | val = pcr->ops->cd_deglitch(pcr); | |
732 | ||
733 | return val; | |
734 | } | |
735 | EXPORT_SYMBOL_GPL(rtsx_pci_card_exist); | |
736 | ||
737 | void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr) | |
738 | { | |
739 | struct completion finish; | |
740 | ||
741 | pcr->finish_me = &finish; | |
742 | init_completion(&finish); | |
743 | ||
744 | if (pcr->done) | |
745 | complete(pcr->done); | |
746 | ||
747 | if (!pcr->remove_pci) | |
748 | rtsx_pci_stop_cmd(pcr); | |
749 | ||
750 | wait_for_completion_interruptible_timeout(&finish, | |
751 | msecs_to_jiffies(2)); | |
752 | pcr->finish_me = NULL; | |
753 | } | |
754 | EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer); | |
755 | ||
756 | static void rtsx_pci_card_detect(struct work_struct *work) | |
757 | { | |
758 | struct delayed_work *dwork; | |
759 | struct rtsx_pcr *pcr; | |
760 | unsigned long flags; | |
761 | unsigned int card_detect = 0; | |
762 | u32 irq_status; | |
763 | ||
764 | dwork = to_delayed_work(work); | |
765 | pcr = container_of(dwork, struct rtsx_pcr, carddet_work); | |
766 | ||
767 | dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__); | |
768 | ||
769 | spin_lock_irqsave(&pcr->lock, flags); | |
770 | ||
771 | irq_status = rtsx_pci_readl(pcr, RTSX_BIPR); | |
772 | dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status); | |
773 | ||
774 | if (pcr->card_inserted || pcr->card_removed) { | |
775 | dev_dbg(&(pcr->pci->dev), | |
776 | "card_inserted: 0x%x, card_removed: 0x%x\n", | |
777 | pcr->card_inserted, pcr->card_removed); | |
778 | ||
779 | if (pcr->ops->cd_deglitch) | |
780 | pcr->card_inserted = pcr->ops->cd_deglitch(pcr); | |
781 | ||
782 | card_detect = pcr->card_inserted | pcr->card_removed; | |
783 | pcr->card_inserted = 0; | |
784 | pcr->card_removed = 0; | |
785 | } | |
786 | ||
787 | spin_unlock_irqrestore(&pcr->lock, flags); | |
788 | ||
789 | if (card_detect & SD_EXIST) | |
790 | pcr->slots[RTSX_SD_CARD].card_event( | |
791 | pcr->slots[RTSX_SD_CARD].p_dev); | |
792 | if (card_detect & MS_EXIST) | |
793 | pcr->slots[RTSX_MS_CARD].card_event( | |
794 | pcr->slots[RTSX_MS_CARD].p_dev); | |
795 | } | |
796 | ||
797 | static irqreturn_t rtsx_pci_isr(int irq, void *dev_id) | |
798 | { | |
799 | struct rtsx_pcr *pcr = dev_id; | |
800 | u32 int_reg; | |
801 | ||
802 | if (!pcr) | |
803 | return IRQ_NONE; | |
804 | ||
805 | spin_lock(&pcr->lock); | |
806 | ||
807 | int_reg = rtsx_pci_readl(pcr, RTSX_BIPR); | |
808 | /* Clear interrupt flag */ | |
809 | rtsx_pci_writel(pcr, RTSX_BIPR, int_reg); | |
810 | if ((int_reg & pcr->bier) == 0) { | |
811 | spin_unlock(&pcr->lock); | |
812 | return IRQ_NONE; | |
813 | } | |
814 | if (int_reg == 0xFFFFFFFF) { | |
815 | spin_unlock(&pcr->lock); | |
816 | return IRQ_HANDLED; | |
817 | } | |
818 | ||
819 | int_reg &= (pcr->bier | 0x7FFFFF); | |
820 | ||
821 | if (int_reg & SD_INT) { | |
822 | if (int_reg & SD_EXIST) { | |
823 | pcr->card_inserted |= SD_EXIST; | |
824 | } else { | |
825 | pcr->card_removed |= SD_EXIST; | |
826 | pcr->card_inserted &= ~SD_EXIST; | |
827 | } | |
828 | } | |
829 | ||
830 | if (int_reg & MS_INT) { | |
831 | if (int_reg & MS_EXIST) { | |
832 | pcr->card_inserted |= MS_EXIST; | |
833 | } else { | |
834 | pcr->card_removed |= MS_EXIST; | |
835 | pcr->card_inserted &= ~MS_EXIST; | |
836 | } | |
837 | } | |
838 | ||
839 | if (pcr->card_inserted || pcr->card_removed) | |
840 | schedule_delayed_work(&pcr->carddet_work, | |
841 | msecs_to_jiffies(200)); | |
842 | ||
843 | if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) { | |
844 | if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) { | |
845 | pcr->trans_result = TRANS_RESULT_FAIL; | |
846 | if (pcr->done) | |
847 | complete(pcr->done); | |
848 | } else if (int_reg & TRANS_OK_INT) { | |
849 | pcr->trans_result = TRANS_RESULT_OK; | |
850 | if (pcr->done) | |
851 | complete(pcr->done); | |
852 | } | |
853 | } | |
854 | ||
855 | spin_unlock(&pcr->lock); | |
856 | return IRQ_HANDLED; | |
857 | } | |
858 | ||
859 | static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr) | |
860 | { | |
861 | dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n", | |
862 | __func__, pcr->msi_en, pcr->pci->irq); | |
863 | ||
864 | if (request_irq(pcr->pci->irq, rtsx_pci_isr, | |
865 | pcr->msi_en ? 0 : IRQF_SHARED, | |
866 | DRV_NAME_RTSX_PCI, pcr)) { | |
867 | dev_err(&(pcr->pci->dev), | |
868 | "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n", | |
869 | pcr->pci->irq); | |
870 | return -1; | |
871 | } | |
872 | ||
873 | pcr->irq = pcr->pci->irq; | |
874 | pci_intx(pcr->pci, !pcr->msi_en); | |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
879 | static void rtsx_pci_idle_work(struct work_struct *work) | |
880 | { | |
881 | struct delayed_work *dwork = to_delayed_work(work); | |
882 | struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work); | |
883 | ||
884 | dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__); | |
885 | ||
886 | mutex_lock(&pcr->pcr_mutex); | |
887 | ||
888 | pcr->state = PDEV_STAT_IDLE; | |
889 | ||
890 | if (pcr->ops->disable_auto_blink) | |
891 | pcr->ops->disable_auto_blink(pcr); | |
892 | if (pcr->ops->turn_off_led) | |
893 | pcr->ops->turn_off_led(pcr); | |
894 | ||
895 | mutex_unlock(&pcr->pcr_mutex); | |
896 | } | |
897 | ||
898 | static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) | |
899 | { | |
900 | int err; | |
901 | ||
902 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); | |
903 | ||
904 | rtsx_pci_enable_bus_int(pcr); | |
905 | ||
906 | /* Power on SSC */ | |
907 | err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); | |
908 | if (err < 0) | |
909 | return err; | |
910 | ||
911 | /* Wait SSC power stable */ | |
912 | udelay(200); | |
913 | ||
914 | if (pcr->ops->optimize_phy) { | |
915 | err = pcr->ops->optimize_phy(pcr); | |
916 | if (err < 0) | |
917 | return err; | |
918 | } | |
919 | ||
920 | rtsx_pci_init_cmd(pcr); | |
921 | ||
922 | /* Set mcu_cnt to 7 to ensure data can be sampled properly */ | |
923 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); | |
924 | ||
925 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); | |
926 | /* Disable card clock */ | |
927 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); | |
928 | /* Reset ASPM state to default value */ | |
929 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); | |
930 | /* Reset delink mode */ | |
931 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); | |
932 | /* Card driving select */ | |
933 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, | |
934 | 0x07, DRIVER_TYPE_D); | |
935 | /* Enable SSC Clock */ | |
936 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, | |
937 | 0xFF, SSC_8X_EN | SSC_SEL_4M); | |
938 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); | |
939 | /* Disable cd_pwr_save */ | |
940 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); | |
941 | /* Clear Link Ready Interrupt */ | |
942 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, | |
943 | LINK_RDY_INT, LINK_RDY_INT); | |
944 | /* Enlarge the estimation window of PERST# glitch | |
945 | * to reduce the chance of invalid card interrupt | |
946 | */ | |
947 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); | |
948 | /* Update RC oscillator to 400k | |
949 | * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 | |
950 | * 1: 2M 0: 400k | |
951 | */ | |
952 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); | |
953 | /* Set interrupt write clear | |
954 | * bit 1: U_elbi_if_rd_clr_en | |
955 | * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear | |
956 | * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear | |
957 | */ | |
958 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); | |
959 | /* Force CLKREQ# PIN to drive 0 to request clock */ | |
960 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08); | |
961 | ||
962 | err = rtsx_pci_send_cmd(pcr, 100); | |
963 | if (err < 0) | |
964 | return err; | |
965 | ||
966 | /* Enable clk_request_n to enable clock power management */ | |
967 | rtsx_pci_write_config_byte(pcr, 0x81, 1); | |
968 | /* Enter L1 when host tx idle */ | |
969 | rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B); | |
970 | ||
971 | if (pcr->ops->extra_init_hw) { | |
972 | err = pcr->ops->extra_init_hw(pcr); | |
973 | if (err < 0) | |
974 | return err; | |
975 | } | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
980 | static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) | |
981 | { | |
982 | int err; | |
983 | ||
984 | spin_lock_init(&pcr->lock); | |
985 | mutex_init(&pcr->pcr_mutex); | |
986 | ||
987 | switch (PCI_PID(pcr)) { | |
988 | default: | |
989 | case 0x5209: | |
990 | rts5209_init_params(pcr); | |
991 | break; | |
992 | ||
993 | case 0x5229: | |
994 | rts5229_init_params(pcr); | |
995 | break; | |
996 | ||
997 | case 0x5289: | |
998 | rtl8411_init_params(pcr); | |
999 | break; | |
1000 | } | |
1001 | ||
1002 | dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n", | |
1003 | PCI_PID(pcr), pcr->ic_version); | |
1004 | ||
1005 | pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot), | |
1006 | GFP_KERNEL); | |
1007 | if (!pcr->slots) | |
1008 | return -ENOMEM; | |
1009 | ||
1010 | pcr->state = PDEV_STAT_IDLE; | |
1011 | err = rtsx_pci_init_hw(pcr); | |
1012 | if (err < 0) { | |
1013 | kfree(pcr->slots); | |
1014 | return err; | |
1015 | } | |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
612b95cd GKH |
1020 | static int rtsx_pci_probe(struct pci_dev *pcidev, |
1021 | const struct pci_device_id *id) | |
ada8a8a1 WW |
1022 | { |
1023 | struct rtsx_pcr *pcr; | |
1024 | struct pcr_handle *handle; | |
1025 | u32 base, len; | |
1026 | int ret, i; | |
1027 | ||
1028 | dev_dbg(&(pcidev->dev), | |
1029 | ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", | |
1030 | pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, | |
1031 | (int)pcidev->revision); | |
1032 | ||
1033 | ret = pci_enable_device(pcidev); | |
1034 | if (ret) | |
1035 | return ret; | |
1036 | ||
1037 | ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI); | |
1038 | if (ret) | |
1039 | goto disable; | |
1040 | ||
1041 | pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); | |
1042 | if (!pcr) { | |
1043 | ret = -ENOMEM; | |
1044 | goto release_pci; | |
1045 | } | |
1046 | ||
1047 | handle = kzalloc(sizeof(*handle), GFP_KERNEL); | |
1048 | if (!handle) { | |
1049 | ret = -ENOMEM; | |
1050 | goto free_pcr; | |
1051 | } | |
1052 | handle->pcr = pcr; | |
1053 | ||
1054 | if (!idr_pre_get(&rtsx_pci_idr, GFP_KERNEL)) { | |
1055 | ret = -ENOMEM; | |
1056 | goto free_handle; | |
1057 | } | |
1058 | ||
1059 | spin_lock(&rtsx_pci_lock); | |
1060 | ret = idr_get_new(&rtsx_pci_idr, pcr, &pcr->id); | |
1061 | spin_unlock(&rtsx_pci_lock); | |
1062 | if (ret) | |
1063 | goto free_handle; | |
1064 | ||
1065 | pcr->pci = pcidev; | |
1066 | dev_set_drvdata(&pcidev->dev, handle); | |
1067 | ||
1068 | len = pci_resource_len(pcidev, 0); | |
1069 | base = pci_resource_start(pcidev, 0); | |
1070 | pcr->remap_addr = ioremap_nocache(base, len); | |
1071 | if (!pcr->remap_addr) { | |
1072 | ret = -ENOMEM; | |
1073 | goto free_host; | |
1074 | } | |
1075 | ||
1076 | pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), | |
1077 | RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr), | |
1078 | GFP_KERNEL); | |
1079 | if (pcr->rtsx_resv_buf == NULL) { | |
1080 | ret = -ENXIO; | |
1081 | goto unmap; | |
1082 | } | |
1083 | pcr->host_cmds_ptr = pcr->rtsx_resv_buf; | |
1084 | pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; | |
1085 | pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; | |
1086 | pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; | |
1087 | ||
1088 | pcr->card_inserted = 0; | |
1089 | pcr->card_removed = 0; | |
1090 | INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); | |
1091 | INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work); | |
1092 | ||
1093 | pcr->msi_en = msi_en; | |
1094 | if (pcr->msi_en) { | |
1095 | ret = pci_enable_msi(pcidev); | |
1096 | if (ret < 0) | |
1097 | pcr->msi_en = false; | |
1098 | } | |
1099 | ||
1100 | ret = rtsx_pci_acquire_irq(pcr); | |
1101 | if (ret < 0) | |
1102 | goto free_dma; | |
1103 | ||
1104 | pci_set_master(pcidev); | |
1105 | synchronize_irq(pcr->irq); | |
1106 | ||
1107 | ret = rtsx_pci_init_chip(pcr); | |
1108 | if (ret < 0) | |
1109 | goto disable_irq; | |
1110 | ||
1111 | for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { | |
1112 | rtsx_pcr_cells[i].platform_data = handle; | |
1113 | rtsx_pcr_cells[i].pdata_size = sizeof(*handle); | |
1114 | } | |
1115 | ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells, | |
1116 | ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); | |
1117 | if (ret < 0) | |
1118 | goto disable_irq; | |
1119 | ||
1120 | schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); | |
1121 | ||
1122 | return 0; | |
1123 | ||
1124 | disable_irq: | |
1125 | free_irq(pcr->irq, (void *)pcr); | |
1126 | free_dma: | |
1127 | dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, | |
1128 | pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); | |
1129 | unmap: | |
1130 | iounmap(pcr->remap_addr); | |
1131 | free_host: | |
1132 | dev_set_drvdata(&pcidev->dev, NULL); | |
1133 | free_handle: | |
1134 | kfree(handle); | |
1135 | free_pcr: | |
1136 | kfree(pcr); | |
1137 | release_pci: | |
1138 | pci_release_regions(pcidev); | |
1139 | disable: | |
1140 | pci_disable_device(pcidev); | |
1141 | ||
1142 | return ret; | |
1143 | } | |
1144 | ||
612b95cd | 1145 | static void rtsx_pci_remove(struct pci_dev *pcidev) |
ada8a8a1 WW |
1146 | { |
1147 | struct pcr_handle *handle = pci_get_drvdata(pcidev); | |
1148 | struct rtsx_pcr *pcr = handle->pcr; | |
1149 | ||
1150 | pcr->remove_pci = true; | |
1151 | ||
1152 | cancel_delayed_work(&pcr->carddet_work); | |
1153 | cancel_delayed_work(&pcr->idle_work); | |
1154 | ||
1155 | mfd_remove_devices(&pcidev->dev); | |
1156 | ||
1157 | dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, | |
1158 | pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); | |
1159 | free_irq(pcr->irq, (void *)pcr); | |
1160 | if (pcr->msi_en) | |
1161 | pci_disable_msi(pcr->pci); | |
1162 | iounmap(pcr->remap_addr); | |
1163 | ||
1164 | dev_set_drvdata(&pcidev->dev, NULL); | |
1165 | pci_release_regions(pcidev); | |
1166 | pci_disable_device(pcidev); | |
1167 | ||
1168 | spin_lock(&rtsx_pci_lock); | |
1169 | idr_remove(&rtsx_pci_idr, pcr->id); | |
1170 | spin_unlock(&rtsx_pci_lock); | |
1171 | ||
1172 | kfree(pcr->slots); | |
1173 | kfree(pcr); | |
1174 | kfree(handle); | |
1175 | ||
1176 | dev_dbg(&(pcidev->dev), | |
1177 | ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n", | |
1178 | pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); | |
1179 | } | |
1180 | ||
1181 | #ifdef CONFIG_PM | |
1182 | ||
1183 | static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state) | |
1184 | { | |
1185 | struct pcr_handle *handle; | |
1186 | struct rtsx_pcr *pcr; | |
1187 | int ret = 0; | |
1188 | ||
1189 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1190 | ||
1191 | handle = pci_get_drvdata(pcidev); | |
1192 | pcr = handle->pcr; | |
1193 | ||
1194 | cancel_delayed_work(&pcr->carddet_work); | |
1195 | cancel_delayed_work(&pcr->idle_work); | |
1196 | ||
1197 | mutex_lock(&pcr->pcr_mutex); | |
1198 | ||
1199 | if (pcr->ops->turn_off_led) | |
1200 | pcr->ops->turn_off_led(pcr); | |
1201 | ||
1202 | rtsx_pci_writel(pcr, RTSX_BIER, 0); | |
1203 | pcr->bier = 0; | |
1204 | ||
1205 | rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); | |
1206 | rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x02); | |
1207 | ||
1208 | pci_save_state(pcidev); | |
1209 | pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); | |
1210 | pci_disable_device(pcidev); | |
1211 | pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); | |
1212 | ||
1213 | mutex_unlock(&pcr->pcr_mutex); | |
1214 | return ret; | |
1215 | } | |
1216 | ||
1217 | static int rtsx_pci_resume(struct pci_dev *pcidev) | |
1218 | { | |
1219 | struct pcr_handle *handle; | |
1220 | struct rtsx_pcr *pcr; | |
1221 | int ret = 0; | |
1222 | ||
1223 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1224 | ||
1225 | handle = pci_get_drvdata(pcidev); | |
1226 | pcr = handle->pcr; | |
1227 | ||
1228 | mutex_lock(&pcr->pcr_mutex); | |
1229 | ||
1230 | pci_set_power_state(pcidev, PCI_D0); | |
1231 | pci_restore_state(pcidev); | |
1232 | ret = pci_enable_device(pcidev); | |
1233 | if (ret) | |
1234 | goto out; | |
1235 | pci_set_master(pcidev); | |
1236 | ||
1237 | ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); | |
1238 | if (ret) | |
1239 | goto out; | |
1240 | ||
1241 | ret = rtsx_pci_init_hw(pcr); | |
1242 | if (ret) | |
1243 | goto out; | |
1244 | ||
1245 | schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); | |
1246 | ||
1247 | out: | |
1248 | mutex_unlock(&pcr->pcr_mutex); | |
1249 | return ret; | |
1250 | } | |
1251 | ||
1252 | #else /* CONFIG_PM */ | |
1253 | ||
1254 | #define rtsx_pci_suspend NULL | |
1255 | #define rtsx_pci_resume NULL | |
1256 | ||
1257 | #endif /* CONFIG_PM */ | |
1258 | ||
1259 | static struct pci_driver rtsx_pci_driver = { | |
1260 | .name = DRV_NAME_RTSX_PCI, | |
1261 | .id_table = rtsx_pci_ids, | |
1262 | .probe = rtsx_pci_probe, | |
612b95cd | 1263 | .remove = rtsx_pci_remove, |
ada8a8a1 WW |
1264 | .suspend = rtsx_pci_suspend, |
1265 | .resume = rtsx_pci_resume, | |
1266 | }; | |
1267 | module_pci_driver(rtsx_pci_driver); | |
1268 | ||
1269 | MODULE_LICENSE("GPL"); | |
1270 | MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); | |
1271 | MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver"); |