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mfd: da9062-core: Rename get_device_type to da9062_get_device_type
[linux-2.6-block.git] / drivers / mfd / rtsx_pcr.c
CommitLineData
ada8a8a1
WW		 1/* Driver for Realtek PCI-Express card reader
2 *
09fd8678 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
ada8a8a1
WW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
ada8a8a1
WW		 20 */
21
22#include <linux/pci.h>
23#include <linux/module.h>
aec17ea1 24#include <linux/slab.h>
ada8a8a1
WW		 25#include <linux/dma-mapping.h>
26#include <linux/highmem.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/idr.h>
30#include <linux/platform_device.h>
31#include <linux/mfd/core.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35#include "rtsx_pcr.h"
36
37static bool msi_en = true;
38module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(msi_en, "Enable MSI");
40
41static DEFINE_IDR(rtsx_pci_idr);
42static DEFINE_SPINLOCK(rtsx_pci_lock);
43
44static struct mfd_cell rtsx_pcr_cells[] = {
45 [RTSX_SD_CARD] = {
46 .name = DRV_NAME_RTSX_PCI_SDMMC,
47 },
48 [RTSX_MS_CARD] = {
49 .name = DRV_NAME_RTSX_PCI_MS,
50 },
51};
52
36fcd06c 53static const struct pci_device_id rtsx_pci_ids[] = {
ada8a8a1
WW		 54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
e1237932 57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
4c4b8c10 58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
9032eabd 59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56cb3cc1 60 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
663c425f 61 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
41bc2334 62 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
ada8a8a1
WW		 63 { 0, }
64};
65
66MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
67
19f3bd54
MC		 68static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
69{
70 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
71 0xFC, pcr->aspm_en);
72}
73
74static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
75{
76 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
77 0xFC, 0);
78}
79
ada8a8a1
WW		 80void rtsx_pci_start_run(struct rtsx_pcr *pcr)
81{
82 /* If pci device removed, don't queue idle work any more */
83 if (pcr->remove_pci)
84 return;
85
86 if (pcr->state != PDEV_STAT_RUN) {
87 pcr->state = PDEV_STAT_RUN;
88 if (pcr->ops->enable_auto_blink)
89 pcr->ops->enable_auto_blink(pcr);
773ccdfd
WW		 90
91 if (pcr->aspm_en)
19f3bd54 92 rtsx_pci_disable_aspm(pcr);
ada8a8a1
WW		 93 }
94
95 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
96}
97EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
98
99int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
100{
101 int i;
102 u32 val = HAIMR_WRITE_START;
103
104 val |= (u32)(addr & 0x3FFF) << 16;
105 val |= (u32)mask << 8;
106 val |= (u32)data;
107
108 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
109
110 for (i = 0; i < MAX_RW_REG_CNT; i++) {
111 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
112 if ((val & HAIMR_TRANS_END) == 0) {
113 if (data != (u8)val)
114 return -EIO;
115 return 0;
116 }
117 }
118
119 return -ETIMEDOUT;
120}
121EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
122
123int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
124{
125 u32 val = HAIMR_READ_START;
126 int i;
127
128 val |= (u32)(addr & 0x3FFF) << 16;
129 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
130
131 for (i = 0; i < MAX_RW_REG_CNT; i++) {
132 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
133 if ((val & HAIMR_TRANS_END) == 0)
134 break;
135 }
136
137 if (i >= MAX_RW_REG_CNT)
138 return -ETIMEDOUT;
139
140 if (data)
141 *data = (u8)(val & 0xFF);
142
143 return 0;
144}
145EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
146
663c425f 147int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
ada8a8a1
WW		 148{
149 int err, i, finished = 0;
150 u8 tmp;
151
152 rtsx_pci_init_cmd(pcr);
153
154 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
155 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
158
159 err = rtsx_pci_send_cmd(pcr, 100);
160 if (err < 0)
161 return err;
162
163 for (i = 0; i < 100000; i++) {
164 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
165 if (err < 0)
166 return err;
167
168 if (!(tmp & 0x80)) {
169 finished = 1;
170 break;
171 }
172 }
173
174 if (!finished)
175 return -ETIMEDOUT;
176
177 return 0;
178}
663c425f
MC		 179
180int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
181{
182 if (pcr->ops->write_phy)
183 return pcr->ops->write_phy(pcr, addr, val);
184
185 return __rtsx_pci_write_phy_register(pcr, addr, val);
186}
ada8a8a1
WW		 187EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
188
663c425f 189int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
ada8a8a1
WW		 190{
191 int err, i, finished = 0;
192 u16 data;
193 u8 *ptr, tmp;
194
195 rtsx_pci_init_cmd(pcr);
196
197 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
199
200 err = rtsx_pci_send_cmd(pcr, 100);
201 if (err < 0)
202 return err;
203
204 for (i = 0; i < 100000; i++) {
205 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
206 if (err < 0)
207 return err;
208
209 if (!(tmp & 0x80)) {
210 finished = 1;
211 break;
212 }
213 }
214
215 if (!finished)
216 return -ETIMEDOUT;
217
218 rtsx_pci_init_cmd(pcr);
219
220 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
221 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
222
223 err = rtsx_pci_send_cmd(pcr, 100);
224 if (err < 0)
225 return err;
226
227 ptr = rtsx_pci_get_cmd_data(pcr);
228 data = ((u16)ptr[1] << 8) | ptr[0];
229
230 if (val)
231 *val = data;
232
233 return 0;
234}
663c425f
MC		 235
236int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
237{
238 if (pcr->ops->read_phy)
239 return pcr->ops->read_phy(pcr, addr, val);
240
241 return __rtsx_pci_read_phy_register(pcr, addr, val);
242}
ada8a8a1
WW		 243EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
244
245void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
246{
247 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
248 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
249
250 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
251 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
252}
253EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
254
255void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
256 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
257{
258 unsigned long flags;
259 u32 val = 0;
260 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
261
262 val |= (u32)(cmd_type & 0x03) << 30;
263 val |= (u32)(reg_addr & 0x3FFF) << 16;
264 val |= (u32)mask << 8;
265 val |= (u32)data;
266
267 spin_lock_irqsave(&pcr->lock, flags);
268 ptr += pcr->ci;
269 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
270 put_unaligned_le32(val, ptr);
271 ptr++;
272 pcr->ci++;
273 }
274 spin_unlock_irqrestore(&pcr->lock, flags);
275}
276EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
277
278void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
279{
280 u32 val = 1 << 31;
281
282 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
283
284 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
285 /* Hardware Auto Response */
286 val |= 0x40000000;
287 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
288}
289EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
290
291int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
292{
293 struct completion trans_done;
294 u32 val = 1 << 31;
295 long timeleft;
296 unsigned long flags;
297 int err = 0;
298
299 spin_lock_irqsave(&pcr->lock, flags);
300
301 /* set up data structures for the wakeup system */
302 pcr->done = &trans_done;
303 pcr->trans_result = TRANS_NOT_READY;
304 init_completion(&trans_done);
305
306 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
307
308 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
309 /* Hardware Auto Response */
310 val |= 0x40000000;
311 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
312
313 spin_unlock_irqrestore(&pcr->lock, flags);
314
315 /* Wait for TRANS_OK_INT */
316 timeleft = wait_for_completion_interruptible_timeout(
317 &trans_done, msecs_to_jiffies(timeout));
318 if (timeleft <= 0) {
0523b8f4 319 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
ada8a8a1
WW		 320 err = -ETIMEDOUT;
321 goto finish_send_cmd;
322 }
323
324 spin_lock_irqsave(&pcr->lock, flags);
325 if (pcr->trans_result == TRANS_RESULT_FAIL)
326 err = -EINVAL;
327 else if (pcr->trans_result == TRANS_RESULT_OK)
328 err = 0;
329 else if (pcr->trans_result == TRANS_NO_DEVICE)
330 err = -ENODEV;
331 spin_unlock_irqrestore(&pcr->lock, flags);
332
333finish_send_cmd:
334 spin_lock_irqsave(&pcr->lock, flags);
335 pcr->done = NULL;
336 spin_unlock_irqrestore(&pcr->lock, flags);
337
338 if ((err < 0) && (err != -ENODEV))
339 rtsx_pci_stop_cmd(pcr);
340
341 if (pcr->finish_me)
342 complete(pcr->finish_me);
343
344 return err;
345}
346EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
347
348static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
349 dma_addr_t addr, unsigned int len, int end)
350{
351 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
352 u64 val;
353 u8 option = SG_VALID | SG_TRANS_DATA;
354
0523b8f4 355 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
ada8a8a1
WW		 356
357 if (end)
358 option |= SG_END;
359 val = ((u64)addr << 32) | ((u64)len << 12) | option;
360
361 put_unaligned_le64(val, ptr);
ada8a8a1
WW		 362 pcr->sgi++;
363}
364
365int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
366 int num_sg, bool read, int timeout)
367{
8cd11830 368 int err = 0, count;
98fcc576 369
0523b8f4 370 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
8cd11830
MC		 371 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
372 if (count < 1)
373 return -EINVAL;
0523b8f4 374 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
8cd11830
MC		 375
376 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
377
378 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
379
380 return err;
381}
382EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
383
384int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
385 int num_sg, bool read)
386{
387 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
98fcc576 388
98fcc576
MC		 389 if (pcr->remove_pci)
390 return -EINVAL;
391
392 if ((sglist == NULL) || (num_sg <= 0))
393 return -EINVAL;
ada8a8a1 394
8cd11830
MC		 395 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
396}
397EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
398
399void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
400 int num_sg, bool read)
401{
402 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
403
404 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
405}
406EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
407
408int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
409 int count, bool read, int timeout)
410{
411 struct completion trans_done;
412 struct scatterlist *sg;
413 dma_addr_t addr;
414 long timeleft;
415 unsigned long flags;
416 unsigned int len;
417 int i, err = 0;
418 u32 val;
419 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
98fcc576 420
8cd11830
MC		 421 if (pcr->remove_pci)
422 return -ENODEV;
423
424 if ((sglist == NULL) || (count < 1))
ada8a8a1 425 return -EINVAL;
ada8a8a1 426
98fcc576
MC		 427 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
428 pcr->sgi = 0;
429 for_each_sg(sglist, sg, count, i) {
430 addr = sg_dma_address(sg);
431 len = sg_dma_len(sg);
432 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
433 }
ada8a8a1
WW		 434
435 spin_lock_irqsave(&pcr->lock, flags);
436
437 pcr->done = &trans_done;
438 pcr->trans_result = TRANS_NOT_READY;
439 init_completion(&trans_done);
98fcc576
MC		 440 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
441 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
ada8a8a1
WW		 442
443 spin_unlock_irqrestore(&pcr->lock, flags);
444
445 timeleft = wait_for_completion_interruptible_timeout(
446 &trans_done, msecs_to_jiffies(timeout));
447 if (timeleft <= 0) {
0523b8f4 448 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
ada8a8a1
WW		 449 err = -ETIMEDOUT;
450 goto out;
451 }
452
453 spin_lock_irqsave(&pcr->lock, flags);
ada8a8a1
WW		 454 if (pcr->trans_result == TRANS_RESULT_FAIL)
455 err = -EINVAL;
456 else if (pcr->trans_result == TRANS_NO_DEVICE)
457 err = -ENODEV;
ada8a8a1
WW		 458 spin_unlock_irqrestore(&pcr->lock, flags);
459
460out:
461 spin_lock_irqsave(&pcr->lock, flags);
462 pcr->done = NULL;
463 spin_unlock_irqrestore(&pcr->lock, flags);
464
ada8a8a1
WW		 465 if ((err < 0) && (err != -ENODEV))
466 rtsx_pci_stop_cmd(pcr);
467
468 if (pcr->finish_me)
469 complete(pcr->finish_me);
470
471 return err;
472}
8cd11830 473EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
ada8a8a1
WW		 474
475int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
476{
477 int err;
478 int i, j;
479 u16 reg;
480 u8 *ptr;
481
482 if (buf_len > 512)
483 buf_len = 512;
484
485 ptr = buf;
486 reg = PPBUF_BASE2;
487 for (i = 0; i < buf_len / 256; i++) {
488 rtsx_pci_init_cmd(pcr);
489
490 for (j = 0; j < 256; j++)
491 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
492
493 err = rtsx_pci_send_cmd(pcr, 250);
494 if (err < 0)
495 return err;
496
497 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
498 ptr += 256;
499 }
500
501 if (buf_len % 256) {
502 rtsx_pci_init_cmd(pcr);
503
504 for (j = 0; j < buf_len % 256; j++)
505 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
506
507 err = rtsx_pci_send_cmd(pcr, 250);
508 if (err < 0)
509 return err;
510 }
511
512 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
513
514 return 0;
515}
516EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
517
518int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
519{
520 int err;
521 int i, j;
522 u16 reg;
523 u8 *ptr;
524
525 if (buf_len > 512)
526 buf_len = 512;
527
528 ptr = buf;
529 reg = PPBUF_BASE2;
530 for (i = 0; i < buf_len / 256; i++) {
531 rtsx_pci_init_cmd(pcr);
532
533 for (j = 0; j < 256; j++) {
534 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
535 reg++, 0xFF, *ptr);
536 ptr++;
537 }
538
539 err = rtsx_pci_send_cmd(pcr, 250);
540 if (err < 0)
541 return err;
542 }
543
544 if (buf_len % 256) {
545 rtsx_pci_init_cmd(pcr);
546
547 for (j = 0; j < buf_len % 256; j++) {
548 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
549 reg++, 0xFF, *ptr);
550 ptr++;
551 }
552
553 err = rtsx_pci_send_cmd(pcr, 250);
554 if (err < 0)
555 return err;
556 }
557
558 return 0;
559}
560EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
561
562static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
563{
564 int err;
565
566 rtsx_pci_init_cmd(pcr);
567
568 while (*tbl & 0xFFFF0000) {
569 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
570 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
571 tbl++;
572 }
573
b158b69a 574 return rtsx_pci_send_cmd(pcr, 100);
ada8a8a1
WW		 575}
576
577int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
578{
579 const u32 *tbl;
580
581 if (card == RTSX_SD_CARD)
582 tbl = pcr->sd_pull_ctl_enable_tbl;
583 else if (card == RTSX_MS_CARD)
584 tbl = pcr->ms_pull_ctl_enable_tbl;
585 else
586 return -EINVAL;
587
588 return rtsx_pci_set_pull_ctl(pcr, tbl);
589}
590EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
591
592int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
593{
594 const u32 *tbl;
595
596 if (card == RTSX_SD_CARD)
597 tbl = pcr->sd_pull_ctl_disable_tbl;
598 else if (card == RTSX_MS_CARD)
599 tbl = pcr->ms_pull_ctl_disable_tbl;
600 else
601 return -EINVAL;
602
603
604 return rtsx_pci_set_pull_ctl(pcr, tbl);
605}
606EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
607
608static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
609{
610 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
611
612 if (pcr->num_slots > 1)
613 pcr->bier |= MS_INT_EN;
614
615 /* Enable Bus Interrupt */
616 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
617
0523b8f4 618 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
ada8a8a1
WW		 619}
620
621static inline u8 double_ssc_depth(u8 depth)
622{
623 return ((depth > 1) ? (depth - 1) : depth);
624}
625
626static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
627{
628 if (div > CLK_DIV_1) {
629 if (ssc_depth > (div - 1))
630 ssc_depth -= (div - 1);
631 else
632 ssc_depth = SSC_DEPTH_4M;
633 }
634
635 return ssc_depth;
636}
637
638int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
639 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
640{
641 int err, clk;
eebbe254 642 u8 n, clk_divider, mcu_cnt, div;
ada8a8a1
WW		 643 u8 depth[] = {
644 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
645 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
646 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
647 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
648 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
649 };
650
651 if (initial_mode) {
652 /* We use 250k(around) here, in initial stage */
653 clk_divider = SD_CLK_DIVIDE_128;
654 card_clock = 30000000;
655 } else {
656 clk_divider = SD_CLK_DIVIDE_0;
657 }
658 err = rtsx_pci_write_register(pcr, SD_CFG1,
659 SD_CLK_DIVIDE_MASK, clk_divider);
660 if (err < 0)
661 return err;
662
663 card_clock /= 1000000;
0523b8f4 664 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
ada8a8a1 665
ada8a8a1
WW		 666 clk = card_clock;
667 if (!initial_mode && double_clk)
668 clk = card_clock * 2;
0523b8f4
MC		 669 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
670 clk, pcr->cur_clock);
ada8a8a1
WW		 671
672 if (clk == pcr->cur_clock)
673 return 0;
674
ab4e8f8b 675 if (pcr->ops->conv_clk_and_div_n)
678cacdf 676 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
ab4e8f8b 677 else
678cacdf 678 n = (u8)(clk - 2);
eebbe254 679 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
ada8a8a1
WW		 680 return -EINVAL;
681
682 mcu_cnt = (u8)(125/clk + 3);
683 if (mcu_cnt > 15)
684 mcu_cnt = 15;
685
eebbe254 686 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
ada8a8a1 687 div = CLK_DIV_1;
eebbe254 688 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
ab4e8f8b 689 if (pcr->ops->conv_clk_and_div_n) {
678cacdf 690 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
ab4e8f8b 691 DIV_N_TO_CLK) * 2;
678cacdf 692 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
ab4e8f8b
WW		 693 CLK_TO_DIV_N);
694 } else {
678cacdf 695 n = (n + 2) * 2 - 2;
ab4e8f8b 696 }
ada8a8a1
WW		 697 div++;
698 }
0523b8f4 699 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
ada8a8a1
WW		 700
701 ssc_depth = depth[ssc_depth];
702 if (double_clk)
703 ssc_depth = double_ssc_depth(ssc_depth);
704
705 ssc_depth = revise_ssc_depth(ssc_depth, div);
0523b8f4 706 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
ada8a8a1
WW		 707
708 rtsx_pci_init_cmd(pcr);
709 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
710 CLK_LOW_FREQ, CLK_LOW_FREQ);
711 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
712 0xFF, (div << 4) | mcu_cnt);
713 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
714 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
715 SSC_DEPTH_MASK, ssc_depth);
678cacdf 716 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
ada8a8a1
WW		 717 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
718 if (vpclk) {
719 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
720 PHASE_NOT_RESET, 0);
721 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
722 PHASE_NOT_RESET, PHASE_NOT_RESET);
723 }
724
725 err = rtsx_pci_send_cmd(pcr, 2000);
726 if (err < 0)
727 return err;
728
729 /* Wait SSC clock stable */
730 udelay(10);
731 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
732 if (err < 0)
733 return err;
734
735 pcr->cur_clock = clk;
736 return 0;
737}
738EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
739
740int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
741{
742 if (pcr->ops->card_power_on)
743 return pcr->ops->card_power_on(pcr, card);
744
745 return 0;
746}
747EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
748
749int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
750{
751 if (pcr->ops->card_power_off)
752 return pcr->ops->card_power_off(pcr, card);
753
754 return 0;
755}
756EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
757
c3481955
WW		 758int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
759{
760 unsigned int cd_mask[] = {
761 [RTSX_SD_CARD] = SD_EXIST,
762 [RTSX_MS_CARD] = MS_EXIST
763 };
764
773ccdfd 765 if (!(pcr->flags & PCR_MS_PMOS)) {
c3481955
WW		 766 /* When using single PMOS, accessing card is not permitted
767 * if the existing card is not the designated one.
768 */
769 if (pcr->card_exist & (~cd_mask[card]))
770 return -EIO;
771 }
772
773 return 0;
774}
775EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
776
d817ac4e
WW		 777int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
778{
779 if (pcr->ops->switch_output_voltage)
780 return pcr->ops->switch_output_voltage(pcr, voltage);
781
782 return 0;
783}
784EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
785
ada8a8a1
WW		 786unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
787{
788 unsigned int val;
789
790 val = rtsx_pci_readl(pcr, RTSX_BIPR);
791 if (pcr->ops->cd_deglitch)
792 val = pcr->ops->cd_deglitch(pcr);
793
794 return val;
795}
796EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
797
798void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
799{
800 struct completion finish;
801
802 pcr->finish_me = &finish;
803 init_completion(&finish);
804
805 if (pcr->done)
806 complete(pcr->done);
807
808 if (!pcr->remove_pci)
809 rtsx_pci_stop_cmd(pcr);
810
811 wait_for_completion_interruptible_timeout(&finish,
812 msecs_to_jiffies(2));
813 pcr->finish_me = NULL;
814}
815EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
816
817static void rtsx_pci_card_detect(struct work_struct *work)
818{
819 struct delayed_work *dwork;
820 struct rtsx_pcr *pcr;
821 unsigned long flags;
504decc0 822 unsigned int card_detect = 0, card_inserted, card_removed;
ada8a8a1
WW		 823 u32 irq_status;
824
825 dwork = to_delayed_work(work);
826 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
827
0523b8f4 828 pcr_dbg(pcr, "--> %s\n", __func__);
ada8a8a1 829
504decc0 830 mutex_lock(&pcr->pcr_mutex);
ada8a8a1
WW		 831 spin_lock_irqsave(&pcr->lock, flags);
832
833 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
0523b8f4 834 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
ada8a8a1 835
504decc0
WW		 836 irq_status &= CARD_EXIST;
837 card_inserted = pcr->card_inserted & irq_status;
838 card_removed = pcr->card_removed;
839 pcr->card_inserted = 0;
840 pcr->card_removed = 0;
841
842 spin_unlock_irqrestore(&pcr->lock, flags);
843
844 if (card_inserted || card_removed) {
0523b8f4
MC		 845 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
846 card_inserted, card_removed);
ada8a8a1
WW		 847
848 if (pcr->ops->cd_deglitch)
504decc0 849 card_inserted = pcr->ops->cd_deglitch(pcr);
ada8a8a1 850
504decc0 851 card_detect = card_inserted | card_removed;
c3481955
WW		 852
853 pcr->card_exist |= card_inserted;
854 pcr->card_exist &= ~card_removed;
ada8a8a1
WW		 855 }
856
504decc0 857 mutex_unlock(&pcr->pcr_mutex);
ada8a8a1 858
2d1484f5 859 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
ada8a8a1
WW		 860 pcr->slots[RTSX_SD_CARD].card_event(
861 pcr->slots[RTSX_SD_CARD].p_dev);
2d1484f5 862 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
ada8a8a1
WW		 863 pcr->slots[RTSX_MS_CARD].card_event(
864 pcr->slots[RTSX_MS_CARD].p_dev);
865}
866
867static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
868{
869 struct rtsx_pcr *pcr = dev_id;
870 u32 int_reg;
871
872 if (!pcr)
873 return IRQ_NONE;
874
875 spin_lock(&pcr->lock);
876
877 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
878 /* Clear interrupt flag */
879 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
880 if ((int_reg & pcr->bier) == 0) {
881 spin_unlock(&pcr->lock);
882 return IRQ_NONE;
883 }
884 if (int_reg == 0xFFFFFFFF) {
885 spin_unlock(&pcr->lock);
886 return IRQ_HANDLED;
887 }
888
889 int_reg &= (pcr->bier | 0x7FFFFF);
890
891 if (int_reg & SD_INT) {
892 if (int_reg & SD_EXIST) {
893 pcr->card_inserted |= SD_EXIST;
894 } else {
895 pcr->card_removed |= SD_EXIST;
896 pcr->card_inserted &= ~SD_EXIST;
897 }
898 }
899
900 if (int_reg & MS_INT) {
901 if (int_reg & MS_EXIST) {
902 pcr->card_inserted |= MS_EXIST;
903 } else {
904 pcr->card_removed |= MS_EXIST;
905 pcr->card_inserted &= ~MS_EXIST;
906 }
907 }
908
ada8a8a1 909 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
98fcc576 910 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
ada8a8a1 911 pcr->trans_result = TRANS_RESULT_FAIL;
98fcc576
MC		 912 if (pcr->done)
913 complete(pcr->done);
914 } else if (int_reg & TRANS_OK_INT) {
ada8a8a1 915 pcr->trans_result = TRANS_RESULT_OK;
98fcc576
MC		 916 if (pcr->done)
917 complete(pcr->done);
ada8a8a1
WW		 918 }
919 }
920
504decc0
WW		 921 if (pcr->card_inserted || pcr->card_removed)
922 schedule_delayed_work(&pcr->carddet_work,
923 msecs_to_jiffies(200));
924
ada8a8a1
WW		 925 spin_unlock(&pcr->lock);
926 return IRQ_HANDLED;
927}
928
929static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
930{
931 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
932 __func__, pcr->msi_en, pcr->pci->irq);
933
934 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
935 pcr->msi_en ? 0 : IRQF_SHARED,
936 DRV_NAME_RTSX_PCI, pcr)) {
937 dev_err(&(pcr->pci->dev),
938 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
939 pcr->pci->irq);
940 return -1;
941 }
942
943 pcr->irq = pcr->pci->irq;
944 pci_intx(pcr->pci, !pcr->msi_en);
945
946 return 0;
947}
948
949static void rtsx_pci_idle_work(struct work_struct *work)
950{
951 struct delayed_work *dwork = to_delayed_work(work);
952 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
953
0523b8f4 954 pcr_dbg(pcr, "--> %s\n", __func__);
ada8a8a1
WW		 955
956 mutex_lock(&pcr->pcr_mutex);
957
958 pcr->state = PDEV_STAT_IDLE;
959
960 if (pcr->ops->disable_auto_blink)
961 pcr->ops->disable_auto_blink(pcr);
962 if (pcr->ops->turn_off_led)
963 pcr->ops->turn_off_led(pcr);
964
773ccdfd 965 if (pcr->aspm_en)
19f3bd54 966 rtsx_pci_enable_aspm(pcr);
773ccdfd 967
ada8a8a1
WW		 968 mutex_unlock(&pcr->pcr_mutex);
969}
970
451be648 971#ifdef CONFIG_PM
5947c167
WW		 972static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
973{
974 if (pcr->ops->turn_off_led)
975 pcr->ops->turn_off_led(pcr);
976
977 rtsx_pci_writel(pcr, RTSX_BIER, 0);
978 pcr->bier = 0;
979
980 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
981 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
982
983 if (pcr->ops->force_power_down)
eb891c65 984 pcr->ops->force_power_down(pcr, pm_state);
5947c167 985}
451be648 986#endif
5947c167 987
ada8a8a1
WW		 988static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
989{
990 int err;
991
19f3bd54 992 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
ada8a8a1
WW		 993 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
994
995 rtsx_pci_enable_bus_int(pcr);
996
997 /* Power on SSC */
998 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
999 if (err < 0)
1000 return err;
1001
1002 /* Wait SSC power stable */
1003 udelay(200);
1004
19f3bd54 1005 rtsx_pci_disable_aspm(pcr);
ada8a8a1
WW		 1006 if (pcr->ops->optimize_phy) {
1007 err = pcr->ops->optimize_phy(pcr);
1008 if (err < 0)
1009 return err;
1010 }
1011
1012 rtsx_pci_init_cmd(pcr);
1013
1014 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1015 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1016
1017 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1018 /* Disable card clock */
1019 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
ada8a8a1
WW		 1020 /* Reset delink mode */
1021 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1022 /* Card driving select */
773ccdfd
WW		 1023 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1024 0xFF, pcr->card_drive_sel);
ada8a8a1
WW		 1025 /* Enable SSC Clock */
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1027 0xFF, SSC_8X_EN | SSC_SEL_4M);
1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1029 /* Disable cd_pwr_save */
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1031 /* Clear Link Ready Interrupt */
1032 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1033 LINK_RDY_INT, LINK_RDY_INT);
1034 /* Enlarge the estimation window of PERST# glitch
1035 * to reduce the chance of invalid card interrupt
1036 */
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1038 /* Update RC oscillator to 400k
1039 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1040 * 1: 2M 0: 400k
1041 */
1042 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1043 /* Set interrupt write clear
1044 * bit 1: U_elbi_if_rd_clr_en
1045 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1046 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1047 */
1048 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
ada8a8a1
WW		 1049
1050 err = rtsx_pci_send_cmd(pcr, 100);
1051 if (err < 0)
1052 return err;
1053
1054 /* Enable clk_request_n to enable clock power management */
19f3bd54 1055 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
ada8a8a1
WW		 1056 /* Enter L1 when host tx idle */
1057 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1058
1059 if (pcr->ops->extra_init_hw) {
1060 err = pcr->ops->extra_init_hw(pcr);
1061 if (err < 0)
1062 return err;
1063 }
1064
c3481955
WW		 1065 /* No CD interrupt if probing driver with card inserted.
1066 * So we need to initialize pcr->card_exist here.
1067 */
1068 if (pcr->ops->cd_deglitch)
1069 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1070 else
1071 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1072
ada8a8a1
WW		 1073 return 0;
1074}
1075
1076static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1077{
1078 int err;
1079
1080 spin_lock_init(&pcr->lock);
1081 mutex_init(&pcr->pcr_mutex);
1082
1083 switch (PCI_PID(pcr)) {
1084 default:
1085 case 0x5209:
1086 rts5209_init_params(pcr);
1087 break;
1088
1089 case 0x5229:
1090 rts5229_init_params(pcr);
1091 break;
1092
1093 case 0x5289:
1094 rtl8411_init_params(pcr);
1095 break;
e1237932
RT		 1096
1097 case 0x5227:
1098 rts5227_init_params(pcr);
1099 break;
4c4b8c10
WW		 1100
1101 case 0x5249:
1102 rts5249_init_params(pcr);
1103 break;
9032eabd 1104
663c425f
MC		 1105 case 0x524A:
1106 rts524a_init_params(pcr);
1107 break;
1108
41bc2334
MC		 1109 case 0x525A:
1110 rts525a_init_params(pcr);
1111 break;
1112
9032eabd
RT		 1113 case 0x5287:
1114 rtl8411b_init_params(pcr);
1115 break;
56cb3cc1
MC		 1116
1117 case 0x5286:
1118 rtl8402_init_params(pcr);
1119 break;
ada8a8a1
WW		 1120 }
1121
0523b8f4 1122 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
ada8a8a1
WW		 1123 PCI_PID(pcr), pcr->ic_version);
1124
1125 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1126 GFP_KERNEL);
1127 if (!pcr->slots)
1128 return -ENOMEM;
1129
773ccdfd
WW		 1130 if (pcr->ops->fetch_vendor_settings)
1131 pcr->ops->fetch_vendor_settings(pcr);
1132
0523b8f4
MC		 1133 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1134 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
773ccdfd 1135 pcr->sd30_drive_sel_1v8);
0523b8f4 1136 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
773ccdfd 1137 pcr->sd30_drive_sel_3v3);
0523b8f4 1138 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
773ccdfd 1139 pcr->card_drive_sel);
0523b8f4 1140 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
773ccdfd 1141
ada8a8a1
WW		 1142 pcr->state = PDEV_STAT_IDLE;
1143 err = rtsx_pci_init_hw(pcr);
1144 if (err < 0) {
1145 kfree(pcr->slots);
1146 return err;
1147 }
1148
1149 return 0;
1150}
1151
612b95cd
GKH		 1152static int rtsx_pci_probe(struct pci_dev *pcidev,
1153 const struct pci_device_id *id)
ada8a8a1
WW		 1154{
1155 struct rtsx_pcr *pcr;
1156 struct pcr_handle *handle;
1157 u32 base, len;
41bc2334 1158 int ret, i, bar = 0;
ada8a8a1
WW		 1159
1160 dev_dbg(&(pcidev->dev),
1161 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1162 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1163 (int)pcidev->revision);
1164
f84ef042
WW		 1165 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1166 if (ret < 0)
1167 return ret;
1168
ada8a8a1
WW		 1169 ret = pci_enable_device(pcidev);
1170 if (ret)
1171 return ret;
1172
1173 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1174 if (ret)
1175 goto disable;
1176
1177 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1178 if (!pcr) {
1179 ret = -ENOMEM;
1180 goto release_pci;
1181 }
1182
1183 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1184 if (!handle) {
1185 ret = -ENOMEM;
1186 goto free_pcr;
1187 }
1188 handle->pcr = pcr;
1189
9f12563d 1190 idr_preload(GFP_KERNEL);
ada8a8a1 1191 spin_lock(&rtsx_pci_lock);
9f12563d
TH		 1192 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1193 if (ret >= 0)
1194 pcr->id = ret;
ada8a8a1 1195 spin_unlock(&rtsx_pci_lock);
9f12563d
TH		 1196 idr_preload_end();
1197 if (ret < 0)
ada8a8a1
WW		 1198 goto free_handle;
1199
1200 pcr->pci = pcidev;
1201 dev_set_drvdata(&pcidev->dev, handle);
1202
41bc2334
MC		 1203 if (CHK_PCI_PID(pcr, 0x525A))
1204 bar = 1;
1205 len = pci_resource_len(pcidev, bar);
1206 base = pci_resource_start(pcidev, bar);
ada8a8a1
WW		 1207 pcr->remap_addr = ioremap_nocache(base, len);
1208 if (!pcr->remap_addr) {
1209 ret = -ENOMEM;
af1192d7 1210 goto free_handle;
ada8a8a1
WW		 1211 }
1212
1213 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1214 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1215 GFP_KERNEL);
1216 if (pcr->rtsx_resv_buf == NULL) {
1217 ret = -ENXIO;
1218 goto unmap;
1219 }
1220 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1221 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1222 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1223 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1224
1225 pcr->card_inserted = 0;
1226 pcr->card_removed = 0;
1227 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1228 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1229
1230 pcr->msi_en = msi_en;
1231 if (pcr->msi_en) {
1232 ret = pci_enable_msi(pcidev);
51529705 1233 if (ret)
ada8a8a1
WW		 1234 pcr->msi_en = false;
1235 }
1236
1237 ret = rtsx_pci_acquire_irq(pcr);
1238 if (ret < 0)
9d66b568 1239 goto disable_msi;
ada8a8a1
WW		 1240
1241 pci_set_master(pcidev);
1242 synchronize_irq(pcr->irq);
1243
1244 ret = rtsx_pci_init_chip(pcr);
1245 if (ret < 0)
1246 goto disable_irq;
1247
1248 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1249 rtsx_pcr_cells[i].platform_data = handle;
1250 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1251 }
1252 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1253 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1254 if (ret < 0)
1255 goto disable_irq;
1256
1257 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1258
1259 return 0;
1260
1261disable_irq:
1262 free_irq(pcr->irq, (void *)pcr);
9d66b568
JS		 1263disable_msi:
1264 if (pcr->msi_en)
1265 pci_disable_msi(pcr->pci);
ada8a8a1
WW		 1266 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1267 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1268unmap:
1269 iounmap(pcr->remap_addr);
ada8a8a1
WW		 1270free_handle:
1271 kfree(handle);
1272free_pcr:
1273 kfree(pcr);
1274release_pci:
1275 pci_release_regions(pcidev);
1276disable:
1277 pci_disable_device(pcidev);
1278
1279 return ret;
1280}
1281
612b95cd 1282static void rtsx_pci_remove(struct pci_dev *pcidev)
ada8a8a1
WW		 1283{
1284 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1285 struct rtsx_pcr *pcr = handle->pcr;
1286
1287 pcr->remove_pci = true;
1288
73beb63d
TG		 1289 /* Disable interrupts at the pcr level */
1290 spin_lock_irq(&pcr->lock);
1291 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1292 pcr->bier = 0;
1293 spin_unlock_irq(&pcr->lock);
1294
1295 cancel_delayed_work_sync(&pcr->carddet_work);
1296 cancel_delayed_work_sync(&pcr->idle_work);
ada8a8a1
WW		 1297
1298 mfd_remove_devices(&pcidev->dev);
1299
1300 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1301 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1302 free_irq(pcr->irq, (void *)pcr);
1303 if (pcr->msi_en)
1304 pci_disable_msi(pcr->pci);
1305 iounmap(pcr->remap_addr);
1306
ada8a8a1
WW		 1307 pci_release_regions(pcidev);
1308 pci_disable_device(pcidev);
1309
1310 spin_lock(&rtsx_pci_lock);
1311 idr_remove(&rtsx_pci_idr, pcr->id);
1312 spin_unlock(&rtsx_pci_lock);
1313
1314 kfree(pcr->slots);
1315 kfree(pcr);
1316 kfree(handle);
1317
1318 dev_dbg(&(pcidev->dev),
1319 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1320 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1321}
1322
1323#ifdef CONFIG_PM
1324
1325static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1326{
1327 struct pcr_handle *handle;
1328 struct rtsx_pcr *pcr;
ada8a8a1
WW		 1329
1330 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1331
1332 handle = pci_get_drvdata(pcidev);
1333 pcr = handle->pcr;
1334
1335 cancel_delayed_work(&pcr->carddet_work);
1336 cancel_delayed_work(&pcr->idle_work);
1337
1338 mutex_lock(&pcr->pcr_mutex);
1339
5947c167 1340 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
ada8a8a1
WW		 1341
1342 pci_save_state(pcidev);
1343 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1344 pci_disable_device(pcidev);
1345 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1346
1347 mutex_unlock(&pcr->pcr_mutex);
5947c167 1348 return 0;
ada8a8a1
WW		 1349}
1350
1351static int rtsx_pci_resume(struct pci_dev *pcidev)
1352{
1353 struct pcr_handle *handle;
1354 struct rtsx_pcr *pcr;
1355 int ret = 0;
1356
1357 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1358
1359 handle = pci_get_drvdata(pcidev);
1360 pcr = handle->pcr;
1361
1362 mutex_lock(&pcr->pcr_mutex);
1363
1364 pci_set_power_state(pcidev, PCI_D0);
1365 pci_restore_state(pcidev);
1366 ret = pci_enable_device(pcidev);
1367 if (ret)
1368 goto out;
1369 pci_set_master(pcidev);
1370
1371 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1372 if (ret)
1373 goto out;
1374
1375 ret = rtsx_pci_init_hw(pcr);
1376 if (ret)
1377 goto out;
1378
1379 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1380
1381out:
1382 mutex_unlock(&pcr->pcr_mutex);
1383 return ret;
1384}
1385
5947c167
WW		 1386static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1387{
1388 struct pcr_handle *handle;
1389 struct rtsx_pcr *pcr;
1390
1391 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1392
1393 handle = pci_get_drvdata(pcidev);
1394 pcr = handle->pcr;
1395 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1396
1397 pci_disable_device(pcidev);
1398}
1399
ada8a8a1
WW		 1400#else /* CONFIG_PM */
1401
1402#define rtsx_pci_suspend NULL
1403#define rtsx_pci_resume NULL
5947c167 1404#define rtsx_pci_shutdown NULL
ada8a8a1
WW		 1405
1406#endif /* CONFIG_PM */
1407
1408static struct pci_driver rtsx_pci_driver = {
1409 .name = DRV_NAME_RTSX_PCI,
1410 .id_table = rtsx_pci_ids,
1411 .probe = rtsx_pci_probe,
612b95cd 1412 .remove = rtsx_pci_remove,
ada8a8a1
WW		 1413 .suspend = rtsx_pci_suspend,
1414 .resume = rtsx_pci_resume,
5947c167 1415 .shutdown = rtsx_pci_shutdown,
ada8a8a1
WW		 1416};
1417module_pci_driver(rtsx_pci_driver);
1418
1419MODULE_LICENSE("GPL");
1420MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1421MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Linux 6.x block layer and io_uring tree(s)