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mfd: rtsx: Add support for rts525A
[linux-2.6-block.git] / drivers / mfd / rtsx_pcr.c
CommitLineData
ada8a8a1
WW		 1/* Driver for Realtek PCI-Express card reader
2 *
09fd8678 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
ada8a8a1
WW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
ada8a8a1
WW		 20 */
21
22#include <linux/pci.h>
23#include <linux/module.h>
aec17ea1 24#include <linux/slab.h>
ada8a8a1
WW		 25#include <linux/dma-mapping.h>
26#include <linux/highmem.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/idr.h>
30#include <linux/platform_device.h>
31#include <linux/mfd/core.h>
32#include <linux/mfd/rtsx_pci.h>
33#include <asm/unaligned.h>
34
35#include "rtsx_pcr.h"
36
37static bool msi_en = true;
38module_param(msi_en, bool, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(msi_en, "Enable MSI");
40
41static DEFINE_IDR(rtsx_pci_idr);
42static DEFINE_SPINLOCK(rtsx_pci_lock);
43
44static struct mfd_cell rtsx_pcr_cells[] = {
45 [RTSX_SD_CARD] = {
46 .name = DRV_NAME_RTSX_PCI_SDMMC,
47 },
48 [RTSX_MS_CARD] = {
49 .name = DRV_NAME_RTSX_PCI_MS,
50 },
51};
52
36fcd06c 53static const struct pci_device_id rtsx_pci_ids[] = {
ada8a8a1
WW		 54 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 },
55 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
e1237932 57 { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
4c4b8c10 58 { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
9032eabd 59 { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 },
56cb3cc1 60 { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 },
663c425f 61 { PCI_DEVICE(0x10EC, 0x524A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
41bc2334 62 { PCI_DEVICE(0x10EC, 0x525A), PCI_CLASS_OTHERS << 16, 0xFF0000 },
ada8a8a1
WW		 63 { 0, }
64};
65
66MODULE_DEVICE_TABLE(pci, rtsx_pci_ids);
67
19f3bd54
MC		 68static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr)
69{
70 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
71 0xFC, pcr->aspm_en);
72}
73
74static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr)
75{
76 rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL,
77 0xFC, 0);
78}
79
ada8a8a1
WW		 80void rtsx_pci_start_run(struct rtsx_pcr *pcr)
81{
82 /* If pci device removed, don't queue idle work any more */
83 if (pcr->remove_pci)
84 return;
85
86 if (pcr->state != PDEV_STAT_RUN) {
87 pcr->state = PDEV_STAT_RUN;
88 if (pcr->ops->enable_auto_blink)
89 pcr->ops->enable_auto_blink(pcr);
773ccdfd
WW		 90
91 if (pcr->aspm_en)
19f3bd54 92 rtsx_pci_disable_aspm(pcr);
ada8a8a1
WW		 93 }
94
95 mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200));
96}
97EXPORT_SYMBOL_GPL(rtsx_pci_start_run);
98
99int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
100{
101 int i;
102 u32 val = HAIMR_WRITE_START;
103
104 val |= (u32)(addr & 0x3FFF) << 16;
105 val |= (u32)mask << 8;
106 val |= (u32)data;
107
108 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
109
110 for (i = 0; i < MAX_RW_REG_CNT; i++) {
111 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
112 if ((val & HAIMR_TRANS_END) == 0) {
113 if (data != (u8)val)
114 return -EIO;
115 return 0;
116 }
117 }
118
119 return -ETIMEDOUT;
120}
121EXPORT_SYMBOL_GPL(rtsx_pci_write_register);
122
123int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
124{
125 u32 val = HAIMR_READ_START;
126 int i;
127
128 val |= (u32)(addr & 0x3FFF) << 16;
129 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
130
131 for (i = 0; i < MAX_RW_REG_CNT; i++) {
132 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
133 if ((val & HAIMR_TRANS_END) == 0)
134 break;
135 }
136
137 if (i >= MAX_RW_REG_CNT)
138 return -ETIMEDOUT;
139
140 if (data)
141 *data = (u8)(val & 0xFF);
142
143 return 0;
144}
145EXPORT_SYMBOL_GPL(rtsx_pci_read_register);
146
663c425f 147int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
ada8a8a1
WW		 148{
149 int err, i, finished = 0;
150 u8 tmp;
151
152 rtsx_pci_init_cmd(pcr);
153
154 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val);
155 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8));
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
157 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81);
158
159 err = rtsx_pci_send_cmd(pcr, 100);
160 if (err < 0)
161 return err;
162
163 for (i = 0; i < 100000; i++) {
164 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
165 if (err < 0)
166 return err;
167
168 if (!(tmp & 0x80)) {
169 finished = 1;
170 break;
171 }
172 }
173
174 if (!finished)
175 return -ETIMEDOUT;
176
177 return 0;
178}
663c425f
MC		 179
180int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
181{
182 if (pcr->ops->write_phy)
183 return pcr->ops->write_phy(pcr, addr, val);
184
185 return __rtsx_pci_write_phy_register(pcr, addr, val);
186}
ada8a8a1
WW		 187EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register);
188
663c425f 189int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
ada8a8a1
WW		 190{
191 int err, i, finished = 0;
192 u16 data;
193 u8 *ptr, tmp;
194
195 rtsx_pci_init_cmd(pcr);
196
197 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr);
198 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80);
199
200 err = rtsx_pci_send_cmd(pcr, 100);
201 if (err < 0)
202 return err;
203
204 for (i = 0; i < 100000; i++) {
205 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
206 if (err < 0)
207 return err;
208
209 if (!(tmp & 0x80)) {
210 finished = 1;
211 break;
212 }
213 }
214
215 if (!finished)
216 return -ETIMEDOUT;
217
218 rtsx_pci_init_cmd(pcr);
219
220 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0);
221 rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0);
222
223 err = rtsx_pci_send_cmd(pcr, 100);
224 if (err < 0)
225 return err;
226
227 ptr = rtsx_pci_get_cmd_data(pcr);
228 data = ((u16)ptr[1] << 8) | ptr[0];
229
230 if (val)
231 *val = data;
232
233 return 0;
234}
663c425f
MC		 235
236int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
237{
238 if (pcr->ops->read_phy)
239 return pcr->ops->read_phy(pcr, addr, val);
240
241 return __rtsx_pci_read_phy_register(pcr, addr, val);
242}
ada8a8a1
WW		 243EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register);
244
245void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
246{
247 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
248 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
249
250 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
251 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
252}
253EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd);
254
255void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
256 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
257{
258 unsigned long flags;
259 u32 val = 0;
260 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
261
262 val |= (u32)(cmd_type & 0x03) << 30;
263 val |= (u32)(reg_addr & 0x3FFF) << 16;
264 val |= (u32)mask << 8;
265 val |= (u32)data;
266
267 spin_lock_irqsave(&pcr->lock, flags);
268 ptr += pcr->ci;
269 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
270 put_unaligned_le32(val, ptr);
271 ptr++;
272 pcr->ci++;
273 }
274 spin_unlock_irqrestore(&pcr->lock, flags);
275}
276EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd);
277
278void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
279{
280 u32 val = 1 << 31;
281
282 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
283
284 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
285 /* Hardware Auto Response */
286 val |= 0x40000000;
287 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
288}
289EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait);
290
291int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
292{
293 struct completion trans_done;
294 u32 val = 1 << 31;
295 long timeleft;
296 unsigned long flags;
297 int err = 0;
298
299 spin_lock_irqsave(&pcr->lock, flags);
300
301 /* set up data structures for the wakeup system */
302 pcr->done = &trans_done;
303 pcr->trans_result = TRANS_NOT_READY;
304 init_completion(&trans_done);
305
306 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
307
308 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
309 /* Hardware Auto Response */
310 val |= 0x40000000;
311 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
312
313 spin_unlock_irqrestore(&pcr->lock, flags);
314
315 /* Wait for TRANS_OK_INT */
316 timeleft = wait_for_completion_interruptible_timeout(
317 &trans_done, msecs_to_jiffies(timeout));
318 if (timeleft <= 0) {
319 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
320 __func__, __LINE__);
321 err = -ETIMEDOUT;
322 goto finish_send_cmd;
323 }
324
325 spin_lock_irqsave(&pcr->lock, flags);
326 if (pcr->trans_result == TRANS_RESULT_FAIL)
327 err = -EINVAL;
328 else if (pcr->trans_result == TRANS_RESULT_OK)
329 err = 0;
330 else if (pcr->trans_result == TRANS_NO_DEVICE)
331 err = -ENODEV;
332 spin_unlock_irqrestore(&pcr->lock, flags);
333
334finish_send_cmd:
335 spin_lock_irqsave(&pcr->lock, flags);
336 pcr->done = NULL;
337 spin_unlock_irqrestore(&pcr->lock, flags);
338
339 if ((err < 0) && (err != -ENODEV))
340 rtsx_pci_stop_cmd(pcr);
341
342 if (pcr->finish_me)
343 complete(pcr->finish_me);
344
345 return err;
346}
347EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd);
348
349static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
350 dma_addr_t addr, unsigned int len, int end)
351{
352 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
353 u64 val;
354 u8 option = SG_VALID | SG_TRANS_DATA;
355
356 dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n",
357 (unsigned int)addr, len);
358
359 if (end)
360 option |= SG_END;
361 val = ((u64)addr << 32) | ((u64)len << 12) | option;
362
363 put_unaligned_le64(val, ptr);
ada8a8a1
WW		 364 pcr->sgi++;
365}
366
367int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
368 int num_sg, bool read, int timeout)
369{
8cd11830 370 int err = 0, count;
98fcc576
MC		 371
372 dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg);
8cd11830
MC		 373 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
374 if (count < 1)
375 return -EINVAL;
376 dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count);
377
378 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
379
380 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
381
382 return err;
383}
384EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data);
385
386int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
387 int num_sg, bool read)
388{
389 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
98fcc576 390
98fcc576
MC		 391 if (pcr->remove_pci)
392 return -EINVAL;
393
394 if ((sglist == NULL) || (num_sg <= 0))
395 return -EINVAL;
ada8a8a1 396
8cd11830
MC		 397 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
398}
399EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg);
400
401void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
402 int num_sg, bool read)
403{
404 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
405
406 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
407}
408EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg);
409
410int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
411 int count, bool read, int timeout)
412{
413 struct completion trans_done;
414 struct scatterlist *sg;
415 dma_addr_t addr;
416 long timeleft;
417 unsigned long flags;
418 unsigned int len;
419 int i, err = 0;
420 u32 val;
421 u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE;
98fcc576 422
8cd11830
MC		 423 if (pcr->remove_pci)
424 return -ENODEV;
425
426 if ((sglist == NULL) || (count < 1))
ada8a8a1 427 return -EINVAL;
ada8a8a1 428
98fcc576
MC		 429 val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE;
430 pcr->sgi = 0;
431 for_each_sg(sglist, sg, count, i) {
432 addr = sg_dma_address(sg);
433 len = sg_dma_len(sg);
434 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
435 }
ada8a8a1
WW		 436
437 spin_lock_irqsave(&pcr->lock, flags);
438
439 pcr->done = &trans_done;
440 pcr->trans_result = TRANS_NOT_READY;
441 init_completion(&trans_done);
98fcc576
MC		 442 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
443 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
ada8a8a1
WW		 444
445 spin_unlock_irqrestore(&pcr->lock, flags);
446
447 timeleft = wait_for_completion_interruptible_timeout(
448 &trans_done, msecs_to_jiffies(timeout));
449 if (timeleft <= 0) {
450 dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n",
451 __func__, __LINE__);
452 err = -ETIMEDOUT;
453 goto out;
454 }
455
456 spin_lock_irqsave(&pcr->lock, flags);
ada8a8a1
WW		 457 if (pcr->trans_result == TRANS_RESULT_FAIL)
458 err = -EINVAL;
459 else if (pcr->trans_result == TRANS_NO_DEVICE)
460 err = -ENODEV;
ada8a8a1
WW		 461 spin_unlock_irqrestore(&pcr->lock, flags);
462
463out:
464 spin_lock_irqsave(&pcr->lock, flags);
465 pcr->done = NULL;
466 spin_unlock_irqrestore(&pcr->lock, flags);
467
ada8a8a1
WW		 468 if ((err < 0) && (err != -ENODEV))
469 rtsx_pci_stop_cmd(pcr);
470
471 if (pcr->finish_me)
472 complete(pcr->finish_me);
473
474 return err;
475}
8cd11830 476EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer);
ada8a8a1
WW		 477
478int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
479{
480 int err;
481 int i, j;
482 u16 reg;
483 u8 *ptr;
484
485 if (buf_len > 512)
486 buf_len = 512;
487
488 ptr = buf;
489 reg = PPBUF_BASE2;
490 for (i = 0; i < buf_len / 256; i++) {
491 rtsx_pci_init_cmd(pcr);
492
493 for (j = 0; j < 256; j++)
494 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
495
496 err = rtsx_pci_send_cmd(pcr, 250);
497 if (err < 0)
498 return err;
499
500 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
501 ptr += 256;
502 }
503
504 if (buf_len % 256) {
505 rtsx_pci_init_cmd(pcr);
506
507 for (j = 0; j < buf_len % 256; j++)
508 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
509
510 err = rtsx_pci_send_cmd(pcr, 250);
511 if (err < 0)
512 return err;
513 }
514
515 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
516
517 return 0;
518}
519EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf);
520
521int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
522{
523 int err;
524 int i, j;
525 u16 reg;
526 u8 *ptr;
527
528 if (buf_len > 512)
529 buf_len = 512;
530
531 ptr = buf;
532 reg = PPBUF_BASE2;
533 for (i = 0; i < buf_len / 256; i++) {
534 rtsx_pci_init_cmd(pcr);
535
536 for (j = 0; j < 256; j++) {
537 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
538 reg++, 0xFF, *ptr);
539 ptr++;
540 }
541
542 err = rtsx_pci_send_cmd(pcr, 250);
543 if (err < 0)
544 return err;
545 }
546
547 if (buf_len % 256) {
548 rtsx_pci_init_cmd(pcr);
549
550 for (j = 0; j < buf_len % 256; j++) {
551 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
552 reg++, 0xFF, *ptr);
553 ptr++;
554 }
555
556 err = rtsx_pci_send_cmd(pcr, 250);
557 if (err < 0)
558 return err;
559 }
560
561 return 0;
562}
563EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf);
564
565static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
566{
567 int err;
568
569 rtsx_pci_init_cmd(pcr);
570
571 while (*tbl & 0xFFFF0000) {
572 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
573 (u16)(*tbl >> 16), 0xFF, (u8)(*tbl));
574 tbl++;
575 }
576
577 err = rtsx_pci_send_cmd(pcr, 100);
578 if (err < 0)
579 return err;
580
581 return 0;
582}
583
584int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
585{
586 const u32 *tbl;
587
588 if (card == RTSX_SD_CARD)
589 tbl = pcr->sd_pull_ctl_enable_tbl;
590 else if (card == RTSX_MS_CARD)
591 tbl = pcr->ms_pull_ctl_enable_tbl;
592 else
593 return -EINVAL;
594
595 return rtsx_pci_set_pull_ctl(pcr, tbl);
596}
597EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable);
598
599int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
600{
601 const u32 *tbl;
602
603 if (card == RTSX_SD_CARD)
604 tbl = pcr->sd_pull_ctl_disable_tbl;
605 else if (card == RTSX_MS_CARD)
606 tbl = pcr->ms_pull_ctl_disable_tbl;
607 else
608 return -EINVAL;
609
610
611 return rtsx_pci_set_pull_ctl(pcr, tbl);
612}
613EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable);
614
615static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
616{
617 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN;
618
619 if (pcr->num_slots > 1)
620 pcr->bier |= MS_INT_EN;
621
622 /* Enable Bus Interrupt */
623 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
624
625 dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier);
626}
627
628static inline u8 double_ssc_depth(u8 depth)
629{
630 return ((depth > 1) ? (depth - 1) : depth);
631}
632
633static u8 revise_ssc_depth(u8 ssc_depth, u8 div)
634{
635 if (div > CLK_DIV_1) {
636 if (ssc_depth > (div - 1))
637 ssc_depth -= (div - 1);
638 else
639 ssc_depth = SSC_DEPTH_4M;
640 }
641
642 return ssc_depth;
643}
644
645int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
646 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk)
647{
648 int err, clk;
eebbe254 649 u8 n, clk_divider, mcu_cnt, div;
ada8a8a1
WW		 650 u8 depth[] = {
651 [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M,
652 [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M,
653 [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M,
654 [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K,
655 [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K,
656 };
657
658 if (initial_mode) {
659 /* We use 250k(around) here, in initial stage */
660 clk_divider = SD_CLK_DIVIDE_128;
661 card_clock = 30000000;
662 } else {
663 clk_divider = SD_CLK_DIVIDE_0;
664 }
665 err = rtsx_pci_write_register(pcr, SD_CFG1,
666 SD_CLK_DIVIDE_MASK, clk_divider);
667 if (err < 0)
668 return err;
669
670 card_clock /= 1000000;
671 dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock);
672
ada8a8a1
WW		 673 clk = card_clock;
674 if (!initial_mode && double_clk)
675 clk = card_clock * 2;
676 dev_dbg(&(pcr->pci->dev),
677 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
678 clk, pcr->cur_clock);
679
680 if (clk == pcr->cur_clock)
681 return 0;
682
ab4e8f8b 683 if (pcr->ops->conv_clk_and_div_n)
678cacdf 684 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
ab4e8f8b 685 else
678cacdf 686 n = (u8)(clk - 2);
eebbe254 687 if ((clk <= 2) || (n > MAX_DIV_N_PCR))
ada8a8a1
WW		 688 return -EINVAL;
689
690 mcu_cnt = (u8)(125/clk + 3);
691 if (mcu_cnt > 15)
692 mcu_cnt = 15;
693
eebbe254 694 /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
ada8a8a1 695 div = CLK_DIV_1;
eebbe254 696 while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) {
ab4e8f8b 697 if (pcr->ops->conv_clk_and_div_n) {
678cacdf 698 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
ab4e8f8b 699 DIV_N_TO_CLK) * 2;
678cacdf 700 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
ab4e8f8b
WW		 701 CLK_TO_DIV_N);
702 } else {
678cacdf 703 n = (n + 2) * 2 - 2;
ab4e8f8b 704 }
ada8a8a1
WW		 705 div++;
706 }
678cacdf 707 dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div);
ada8a8a1
WW		 708
709 ssc_depth = depth[ssc_depth];
710 if (double_clk)
711 ssc_depth = double_ssc_depth(ssc_depth);
712
713 ssc_depth = revise_ssc_depth(ssc_depth, div);
714 dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth);
715
716 rtsx_pci_init_cmd(pcr);
717 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
718 CLK_LOW_FREQ, CLK_LOW_FREQ);
719 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
720 0xFF, (div << 4) | mcu_cnt);
721 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
722 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
723 SSC_DEPTH_MASK, ssc_depth);
678cacdf 724 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
ada8a8a1
WW		 725 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
726 if (vpclk) {
727 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
728 PHASE_NOT_RESET, 0);
729 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
730 PHASE_NOT_RESET, PHASE_NOT_RESET);
731 }
732
733 err = rtsx_pci_send_cmd(pcr, 2000);
734 if (err < 0)
735 return err;
736
737 /* Wait SSC clock stable */
738 udelay(10);
739 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
740 if (err < 0)
741 return err;
742
743 pcr->cur_clock = clk;
744 return 0;
745}
746EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock);
747
748int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
749{
750 if (pcr->ops->card_power_on)
751 return pcr->ops->card_power_on(pcr, card);
752
753 return 0;
754}
755EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on);
756
757int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
758{
759 if (pcr->ops->card_power_off)
760 return pcr->ops->card_power_off(pcr, card);
761
762 return 0;
763}
764EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off);
765
c3481955
WW		 766int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
767{
768 unsigned int cd_mask[] = {
769 [RTSX_SD_CARD] = SD_EXIST,
770 [RTSX_MS_CARD] = MS_EXIST
771 };
772
773ccdfd 773 if (!(pcr->flags & PCR_MS_PMOS)) {
c3481955
WW		 774 /* When using single PMOS, accessing card is not permitted
775 * if the existing card is not the designated one.
776 */
777 if (pcr->card_exist & (~cd_mask[card]))
778 return -EIO;
779 }
780
781 return 0;
782}
783EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check);
784
d817ac4e
WW		 785int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
786{
787 if (pcr->ops->switch_output_voltage)
788 return pcr->ops->switch_output_voltage(pcr, voltage);
789
790 return 0;
791}
792EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage);
793
ada8a8a1
WW		 794unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
795{
796 unsigned int val;
797
798 val = rtsx_pci_readl(pcr, RTSX_BIPR);
799 if (pcr->ops->cd_deglitch)
800 val = pcr->ops->cd_deglitch(pcr);
801
802 return val;
803}
804EXPORT_SYMBOL_GPL(rtsx_pci_card_exist);
805
806void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
807{
808 struct completion finish;
809
810 pcr->finish_me = &finish;
811 init_completion(&finish);
812
813 if (pcr->done)
814 complete(pcr->done);
815
816 if (!pcr->remove_pci)
817 rtsx_pci_stop_cmd(pcr);
818
819 wait_for_completion_interruptible_timeout(&finish,
820 msecs_to_jiffies(2));
821 pcr->finish_me = NULL;
822}
823EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer);
824
825static void rtsx_pci_card_detect(struct work_struct *work)
826{
827 struct delayed_work *dwork;
828 struct rtsx_pcr *pcr;
829 unsigned long flags;
504decc0 830 unsigned int card_detect = 0, card_inserted, card_removed;
ada8a8a1
WW		 831 u32 irq_status;
832
833 dwork = to_delayed_work(work);
834 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
835
836 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
837
504decc0 838 mutex_lock(&pcr->pcr_mutex);
ada8a8a1
WW		 839 spin_lock_irqsave(&pcr->lock, flags);
840
841 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
842 dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status);
843
504decc0
WW		 844 irq_status &= CARD_EXIST;
845 card_inserted = pcr->card_inserted & irq_status;
846 card_removed = pcr->card_removed;
847 pcr->card_inserted = 0;
848 pcr->card_removed = 0;
849
850 spin_unlock_irqrestore(&pcr->lock, flags);
851
852 if (card_inserted || card_removed) {
ada8a8a1
WW		 853 dev_dbg(&(pcr->pci->dev),
854 "card_inserted: 0x%x, card_removed: 0x%x\n",
504decc0 855 card_inserted, card_removed);
ada8a8a1
WW		 856
857 if (pcr->ops->cd_deglitch)
504decc0 858 card_inserted = pcr->ops->cd_deglitch(pcr);
ada8a8a1 859
504decc0 860 card_detect = card_inserted | card_removed;
c3481955
WW		 861
862 pcr->card_exist |= card_inserted;
863 pcr->card_exist &= ~card_removed;
ada8a8a1
WW		 864 }
865
504decc0 866 mutex_unlock(&pcr->pcr_mutex);
ada8a8a1 867
2d1484f5 868 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
ada8a8a1
WW		 869 pcr->slots[RTSX_SD_CARD].card_event(
870 pcr->slots[RTSX_SD_CARD].p_dev);
2d1484f5 871 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
ada8a8a1
WW		 872 pcr->slots[RTSX_MS_CARD].card_event(
873 pcr->slots[RTSX_MS_CARD].p_dev);
874}
875
876static irqreturn_t rtsx_pci_isr(int irq, void *dev_id)
877{
878 struct rtsx_pcr *pcr = dev_id;
879 u32 int_reg;
880
881 if (!pcr)
882 return IRQ_NONE;
883
884 spin_lock(&pcr->lock);
885
886 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
887 /* Clear interrupt flag */
888 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
889 if ((int_reg & pcr->bier) == 0) {
890 spin_unlock(&pcr->lock);
891 return IRQ_NONE;
892 }
893 if (int_reg == 0xFFFFFFFF) {
894 spin_unlock(&pcr->lock);
895 return IRQ_HANDLED;
896 }
897
898 int_reg &= (pcr->bier | 0x7FFFFF);
899
900 if (int_reg & SD_INT) {
901 if (int_reg & SD_EXIST) {
902 pcr->card_inserted |= SD_EXIST;
903 } else {
904 pcr->card_removed |= SD_EXIST;
905 pcr->card_inserted &= ~SD_EXIST;
906 }
907 }
908
909 if (int_reg & MS_INT) {
910 if (int_reg & MS_EXIST) {
911 pcr->card_inserted |= MS_EXIST;
912 } else {
913 pcr->card_removed |= MS_EXIST;
914 pcr->card_inserted &= ~MS_EXIST;
915 }
916 }
917
ada8a8a1 918 if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) {
98fcc576 919 if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) {
ada8a8a1 920 pcr->trans_result = TRANS_RESULT_FAIL;
98fcc576
MC		 921 if (pcr->done)
922 complete(pcr->done);
923 } else if (int_reg & TRANS_OK_INT) {
ada8a8a1 924 pcr->trans_result = TRANS_RESULT_OK;
98fcc576
MC		 925 if (pcr->done)
926 complete(pcr->done);
ada8a8a1
WW		 927 }
928 }
929
504decc0
WW		 930 if (pcr->card_inserted || pcr->card_removed)
931 schedule_delayed_work(&pcr->carddet_work,
932 msecs_to_jiffies(200));
933
ada8a8a1
WW		 934 spin_unlock(&pcr->lock);
935 return IRQ_HANDLED;
936}
937
938static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
939{
940 dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n",
941 __func__, pcr->msi_en, pcr->pci->irq);
942
943 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
944 pcr->msi_en ? 0 : IRQF_SHARED,
945 DRV_NAME_RTSX_PCI, pcr)) {
946 dev_err(&(pcr->pci->dev),
947 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
948 pcr->pci->irq);
949 return -1;
950 }
951
952 pcr->irq = pcr->pci->irq;
953 pci_intx(pcr->pci, !pcr->msi_en);
954
955 return 0;
956}
957
958static void rtsx_pci_idle_work(struct work_struct *work)
959{
960 struct delayed_work *dwork = to_delayed_work(work);
961 struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work);
962
963 dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__);
964
965 mutex_lock(&pcr->pcr_mutex);
966
967 pcr->state = PDEV_STAT_IDLE;
968
969 if (pcr->ops->disable_auto_blink)
970 pcr->ops->disable_auto_blink(pcr);
971 if (pcr->ops->turn_off_led)
972 pcr->ops->turn_off_led(pcr);
973
773ccdfd 974 if (pcr->aspm_en)
19f3bd54 975 rtsx_pci_enable_aspm(pcr);
773ccdfd 976
ada8a8a1
WW		 977 mutex_unlock(&pcr->pcr_mutex);
978}
979
451be648 980#ifdef CONFIG_PM
5947c167
WW		 981static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state)
982{
983 if (pcr->ops->turn_off_led)
984 pcr->ops->turn_off_led(pcr);
985
986 rtsx_pci_writel(pcr, RTSX_BIER, 0);
987 pcr->bier = 0;
988
989 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
990 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
991
992 if (pcr->ops->force_power_down)
eb891c65 993 pcr->ops->force_power_down(pcr, pm_state);
5947c167 994}
451be648 995#endif
5947c167 996
ada8a8a1
WW		 997static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
998{
999 int err;
1000
19f3bd54 1001 pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP);
ada8a8a1
WW		 1002 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1003
1004 rtsx_pci_enable_bus_int(pcr);
1005
1006 /* Power on SSC */
1007 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1008 if (err < 0)
1009 return err;
1010
1011 /* Wait SSC power stable */
1012 udelay(200);
1013
19f3bd54 1014 rtsx_pci_disable_aspm(pcr);
ada8a8a1
WW		 1015 if (pcr->ops->optimize_phy) {
1016 err = pcr->ops->optimize_phy(pcr);
1017 if (err < 0)
1018 return err;
1019 }
1020
1021 rtsx_pci_init_cmd(pcr);
1022
1023 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1025
1026 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1027 /* Disable card clock */
1028 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
ada8a8a1
WW		 1029 /* Reset delink mode */
1030 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1031 /* Card driving select */
773ccdfd
WW		 1032 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1033 0xFF, pcr->card_drive_sel);
ada8a8a1
WW		 1034 /* Enable SSC Clock */
1035 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1036 0xFF, SSC_8X_EN | SSC_SEL_4M);
1037 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1038 /* Disable cd_pwr_save */
1039 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1040 /* Clear Link Ready Interrupt */
1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1042 LINK_RDY_INT, LINK_RDY_INT);
1043 /* Enlarge the estimation window of PERST# glitch
1044 * to reduce the chance of invalid card interrupt
1045 */
1046 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1047 /* Update RC oscillator to 400k
1048 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
1049 * 1: 2M 0: 400k
1050 */
1051 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1052 /* Set interrupt write clear
1053 * bit 1: U_elbi_if_rd_clr_en
1054 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
1055 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
1056 */
1057 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
ada8a8a1
WW		 1058
1059 err = rtsx_pci_send_cmd(pcr, 100);
1060 if (err < 0)
1061 return err;
1062
1063 /* Enable clk_request_n to enable clock power management */
19f3bd54 1064 rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1);
ada8a8a1
WW		 1065 /* Enter L1 when host tx idle */
1066 rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B);
1067
1068 if (pcr->ops->extra_init_hw) {
1069 err = pcr->ops->extra_init_hw(pcr);
1070 if (err < 0)
1071 return err;
1072 }
1073
c3481955
WW		 1074 /* No CD interrupt if probing driver with card inserted.
1075 * So we need to initialize pcr->card_exist here.
1076 */
1077 if (pcr->ops->cd_deglitch)
1078 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1079 else
1080 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1081
ada8a8a1
WW		 1082 return 0;
1083}
1084
1085static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1086{
1087 int err;
1088
1089 spin_lock_init(&pcr->lock);
1090 mutex_init(&pcr->pcr_mutex);
1091
1092 switch (PCI_PID(pcr)) {
1093 default:
1094 case 0x5209:
1095 rts5209_init_params(pcr);
1096 break;
1097
1098 case 0x5229:
1099 rts5229_init_params(pcr);
1100 break;
1101
1102 case 0x5289:
1103 rtl8411_init_params(pcr);
1104 break;
e1237932
RT		 1105
1106 case 0x5227:
1107 rts5227_init_params(pcr);
1108 break;
4c4b8c10
WW		 1109
1110 case 0x5249:
1111 rts5249_init_params(pcr);
1112 break;
9032eabd 1113
663c425f
MC		 1114 case 0x524A:
1115 rts524a_init_params(pcr);
1116 break;
1117
41bc2334
MC		 1118 case 0x525A:
1119 rts525a_init_params(pcr);
1120 break;
1121
9032eabd
RT		 1122 case 0x5287:
1123 rtl8411b_init_params(pcr);
1124 break;
56cb3cc1
MC		 1125
1126 case 0x5286:
1127 rtl8402_init_params(pcr);
1128 break;
ada8a8a1
WW		 1129 }
1130
1131 dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
1132 PCI_PID(pcr), pcr->ic_version);
1133
1134 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1135 GFP_KERNEL);
1136 if (!pcr->slots)
1137 return -ENOMEM;
1138
773ccdfd
WW		 1139 if (pcr->ops->fetch_vendor_settings)
1140 pcr->ops->fetch_vendor_settings(pcr);
1141
1142 dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1143 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1144 pcr->sd30_drive_sel_1v8);
1145 dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1146 pcr->sd30_drive_sel_3v3);
1147 dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n",
1148 pcr->card_drive_sel);
1149 dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags);
1150
ada8a8a1
WW		 1151 pcr->state = PDEV_STAT_IDLE;
1152 err = rtsx_pci_init_hw(pcr);
1153 if (err < 0) {
1154 kfree(pcr->slots);
1155 return err;
1156 }
1157
1158 return 0;
1159}
1160
612b95cd
GKH		 1161static int rtsx_pci_probe(struct pci_dev *pcidev,
1162 const struct pci_device_id *id)
ada8a8a1
WW		 1163{
1164 struct rtsx_pcr *pcr;
1165 struct pcr_handle *handle;
1166 u32 base, len;
41bc2334 1167 int ret, i, bar = 0;
ada8a8a1
WW		 1168
1169 dev_dbg(&(pcidev->dev),
1170 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1171 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device,
1172 (int)pcidev->revision);
1173
f84ef042
WW		 1174 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
1175 if (ret < 0)
1176 return ret;
1177
ada8a8a1
WW		 1178 ret = pci_enable_device(pcidev);
1179 if (ret)
1180 return ret;
1181
1182 ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI);
1183 if (ret)
1184 goto disable;
1185
1186 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1187 if (!pcr) {
1188 ret = -ENOMEM;
1189 goto release_pci;
1190 }
1191
1192 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
1193 if (!handle) {
1194 ret = -ENOMEM;
1195 goto free_pcr;
1196 }
1197 handle->pcr = pcr;
1198
9f12563d 1199 idr_preload(GFP_KERNEL);
ada8a8a1 1200 spin_lock(&rtsx_pci_lock);
9f12563d
TH		 1201 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1202 if (ret >= 0)
1203 pcr->id = ret;
ada8a8a1 1204 spin_unlock(&rtsx_pci_lock);
9f12563d
TH		 1205 idr_preload_end();
1206 if (ret < 0)
ada8a8a1
WW		 1207 goto free_handle;
1208
1209 pcr->pci = pcidev;
1210 dev_set_drvdata(&pcidev->dev, handle);
1211
41bc2334
MC		 1212 if (CHK_PCI_PID(pcr, 0x525A))
1213 bar = 1;
1214 len = pci_resource_len(pcidev, bar);
1215 base = pci_resource_start(pcidev, bar);
ada8a8a1
WW		 1216 pcr->remap_addr = ioremap_nocache(base, len);
1217 if (!pcr->remap_addr) {
1218 ret = -ENOMEM;
af1192d7 1219 goto free_handle;
ada8a8a1
WW		 1220 }
1221
1222 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1223 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1224 GFP_KERNEL);
1225 if (pcr->rtsx_resv_buf == NULL) {
1226 ret = -ENXIO;
1227 goto unmap;
1228 }
1229 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1230 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1231 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1232 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1233
1234 pcr->card_inserted = 0;
1235 pcr->card_removed = 0;
1236 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1237 INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work);
1238
1239 pcr->msi_en = msi_en;
1240 if (pcr->msi_en) {
1241 ret = pci_enable_msi(pcidev);
51529705 1242 if (ret)
ada8a8a1
WW		 1243 pcr->msi_en = false;
1244 }
1245
1246 ret = rtsx_pci_acquire_irq(pcr);
1247 if (ret < 0)
9d66b568 1248 goto disable_msi;
ada8a8a1
WW		 1249
1250 pci_set_master(pcidev);
1251 synchronize_irq(pcr->irq);
1252
1253 ret = rtsx_pci_init_chip(pcr);
1254 if (ret < 0)
1255 goto disable_irq;
1256
1257 for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) {
1258 rtsx_pcr_cells[i].platform_data = handle;
1259 rtsx_pcr_cells[i].pdata_size = sizeof(*handle);
1260 }
1261 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1262 ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL);
1263 if (ret < 0)
1264 goto disable_irq;
1265
1266 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1267
1268 return 0;
1269
1270disable_irq:
1271 free_irq(pcr->irq, (void *)pcr);
9d66b568
JS		 1272disable_msi:
1273 if (pcr->msi_en)
1274 pci_disable_msi(pcr->pci);
ada8a8a1
WW		 1275 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1276 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1277unmap:
1278 iounmap(pcr->remap_addr);
ada8a8a1
WW		 1279free_handle:
1280 kfree(handle);
1281free_pcr:
1282 kfree(pcr);
1283release_pci:
1284 pci_release_regions(pcidev);
1285disable:
1286 pci_disable_device(pcidev);
1287
1288 return ret;
1289}
1290
612b95cd 1291static void rtsx_pci_remove(struct pci_dev *pcidev)
ada8a8a1
WW		 1292{
1293 struct pcr_handle *handle = pci_get_drvdata(pcidev);
1294 struct rtsx_pcr *pcr = handle->pcr;
1295
1296 pcr->remove_pci = true;
1297
73beb63d
TG		 1298 /* Disable interrupts at the pcr level */
1299 spin_lock_irq(&pcr->lock);
1300 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1301 pcr->bier = 0;
1302 spin_unlock_irq(&pcr->lock);
1303
1304 cancel_delayed_work_sync(&pcr->carddet_work);
1305 cancel_delayed_work_sync(&pcr->idle_work);
ada8a8a1
WW		 1306
1307 mfd_remove_devices(&pcidev->dev);
1308
1309 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1310 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1311 free_irq(pcr->irq, (void *)pcr);
1312 if (pcr->msi_en)
1313 pci_disable_msi(pcr->pci);
1314 iounmap(pcr->remap_addr);
1315
ada8a8a1
WW		 1316 pci_release_regions(pcidev);
1317 pci_disable_device(pcidev);
1318
1319 spin_lock(&rtsx_pci_lock);
1320 idr_remove(&rtsx_pci_idr, pcr->id);
1321 spin_unlock(&rtsx_pci_lock);
1322
1323 kfree(pcr->slots);
1324 kfree(pcr);
1325 kfree(handle);
1326
1327 dev_dbg(&(pcidev->dev),
1328 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1329 pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device);
1330}
1331
1332#ifdef CONFIG_PM
1333
1334static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state)
1335{
1336 struct pcr_handle *handle;
1337 struct rtsx_pcr *pcr;
ada8a8a1
WW		 1338
1339 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1340
1341 handle = pci_get_drvdata(pcidev);
1342 pcr = handle->pcr;
1343
1344 cancel_delayed_work(&pcr->carddet_work);
1345 cancel_delayed_work(&pcr->idle_work);
1346
1347 mutex_lock(&pcr->pcr_mutex);
1348
5947c167 1349 rtsx_pci_power_off(pcr, HOST_ENTER_S3);
ada8a8a1
WW		 1350
1351 pci_save_state(pcidev);
1352 pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0);
1353 pci_disable_device(pcidev);
1354 pci_set_power_state(pcidev, pci_choose_state(pcidev, state));
1355
1356 mutex_unlock(&pcr->pcr_mutex);
5947c167 1357 return 0;
ada8a8a1
WW		 1358}
1359
1360static int rtsx_pci_resume(struct pci_dev *pcidev)
1361{
1362 struct pcr_handle *handle;
1363 struct rtsx_pcr *pcr;
1364 int ret = 0;
1365
1366 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1367
1368 handle = pci_get_drvdata(pcidev);
1369 pcr = handle->pcr;
1370
1371 mutex_lock(&pcr->pcr_mutex);
1372
1373 pci_set_power_state(pcidev, PCI_D0);
1374 pci_restore_state(pcidev);
1375 ret = pci_enable_device(pcidev);
1376 if (ret)
1377 goto out;
1378 pci_set_master(pcidev);
1379
1380 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1381 if (ret)
1382 goto out;
1383
1384 ret = rtsx_pci_init_hw(pcr);
1385 if (ret)
1386 goto out;
1387
1388 schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200));
1389
1390out:
1391 mutex_unlock(&pcr->pcr_mutex);
1392 return ret;
1393}
1394
5947c167
WW		 1395static void rtsx_pci_shutdown(struct pci_dev *pcidev)
1396{
1397 struct pcr_handle *handle;
1398 struct rtsx_pcr *pcr;
1399
1400 dev_dbg(&(pcidev->dev), "--> %s\n", __func__);
1401
1402 handle = pci_get_drvdata(pcidev);
1403 pcr = handle->pcr;
1404 rtsx_pci_power_off(pcr, HOST_ENTER_S1);
1405
1406 pci_disable_device(pcidev);
1407}
1408
ada8a8a1
WW		 1409#else /* CONFIG_PM */
1410
1411#define rtsx_pci_suspend NULL
1412#define rtsx_pci_resume NULL
5947c167 1413#define rtsx_pci_shutdown NULL
ada8a8a1
WW		 1414
1415#endif /* CONFIG_PM */
1416
1417static struct pci_driver rtsx_pci_driver = {
1418 .name = DRV_NAME_RTSX_PCI,
1419 .id_table = rtsx_pci_ids,
1420 .probe = rtsx_pci_probe,
612b95cd 1421 .remove = rtsx_pci_remove,
ada8a8a1
WW		 1422 .suspend = rtsx_pci_suspend,
1423 .resume = rtsx_pci_resume,
5947c167 1424 .shutdown = rtsx_pci_shutdown,
ada8a8a1
WW		 1425};
1426module_pci_driver(rtsx_pci_driver);
1427
1428MODULE_LICENSE("GPL");
1429MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1430MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");
Linux 6.x block layer and io_uring tree(s)