Commit | Line | Data |
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ada8a8a1 WW |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
09fd8678 | 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
ada8a8a1 WW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG <wei_wang@realsil.com.cn> | |
ada8a8a1 WW |
20 | */ |
21 | ||
22 | #include <linux/pci.h> | |
23 | #include <linux/module.h> | |
aec17ea1 | 24 | #include <linux/slab.h> |
ada8a8a1 WW |
25 | #include <linux/dma-mapping.h> |
26 | #include <linux/highmem.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/idr.h> | |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/mfd/core.h> | |
32 | #include <linux/mfd/rtsx_pci.h> | |
33 | #include <asm/unaligned.h> | |
34 | ||
35 | #include "rtsx_pcr.h" | |
36 | ||
37 | static bool msi_en = true; | |
38 | module_param(msi_en, bool, S_IRUGO | S_IWUSR); | |
39 | MODULE_PARM_DESC(msi_en, "Enable MSI"); | |
40 | ||
41 | static DEFINE_IDR(rtsx_pci_idr); | |
42 | static DEFINE_SPINLOCK(rtsx_pci_lock); | |
43 | ||
44 | static struct mfd_cell rtsx_pcr_cells[] = { | |
45 | [RTSX_SD_CARD] = { | |
46 | .name = DRV_NAME_RTSX_PCI_SDMMC, | |
47 | }, | |
48 | [RTSX_MS_CARD] = { | |
49 | .name = DRV_NAME_RTSX_PCI_MS, | |
50 | }, | |
51 | }; | |
52 | ||
36fcd06c | 53 | static const struct pci_device_id rtsx_pci_ids[] = { |
ada8a8a1 WW |
54 | { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
55 | { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 }, | |
56 | { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 }, | |
e1237932 | 57 | { PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
4c4b8c10 | 58 | { PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
9032eabd | 59 | { PCI_DEVICE(0x10EC, 0x5287), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
56cb3cc1 | 60 | { PCI_DEVICE(0x10EC, 0x5286), PCI_CLASS_OTHERS << 16, 0xFF0000 }, |
ada8a8a1 WW |
61 | { 0, } |
62 | }; | |
63 | ||
64 | MODULE_DEVICE_TABLE(pci, rtsx_pci_ids); | |
65 | ||
19f3bd54 MC |
66 | static inline void rtsx_pci_enable_aspm(struct rtsx_pcr *pcr) |
67 | { | |
68 | rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, | |
69 | 0xFC, pcr->aspm_en); | |
70 | } | |
71 | ||
72 | static inline void rtsx_pci_disable_aspm(struct rtsx_pcr *pcr) | |
73 | { | |
74 | rtsx_pci_update_cfg_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL, | |
75 | 0xFC, 0); | |
76 | } | |
77 | ||
ada8a8a1 WW |
78 | void rtsx_pci_start_run(struct rtsx_pcr *pcr) |
79 | { | |
80 | /* If pci device removed, don't queue idle work any more */ | |
81 | if (pcr->remove_pci) | |
82 | return; | |
83 | ||
84 | if (pcr->state != PDEV_STAT_RUN) { | |
85 | pcr->state = PDEV_STAT_RUN; | |
86 | if (pcr->ops->enable_auto_blink) | |
87 | pcr->ops->enable_auto_blink(pcr); | |
773ccdfd WW |
88 | |
89 | if (pcr->aspm_en) | |
19f3bd54 | 90 | rtsx_pci_disable_aspm(pcr); |
ada8a8a1 WW |
91 | } |
92 | ||
93 | mod_delayed_work(system_wq, &pcr->idle_work, msecs_to_jiffies(200)); | |
94 | } | |
95 | EXPORT_SYMBOL_GPL(rtsx_pci_start_run); | |
96 | ||
97 | int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data) | |
98 | { | |
99 | int i; | |
100 | u32 val = HAIMR_WRITE_START; | |
101 | ||
102 | val |= (u32)(addr & 0x3FFF) << 16; | |
103 | val |= (u32)mask << 8; | |
104 | val |= (u32)data; | |
105 | ||
106 | rtsx_pci_writel(pcr, RTSX_HAIMR, val); | |
107 | ||
108 | for (i = 0; i < MAX_RW_REG_CNT; i++) { | |
109 | val = rtsx_pci_readl(pcr, RTSX_HAIMR); | |
110 | if ((val & HAIMR_TRANS_END) == 0) { | |
111 | if (data != (u8)val) | |
112 | return -EIO; | |
113 | return 0; | |
114 | } | |
115 | } | |
116 | ||
117 | return -ETIMEDOUT; | |
118 | } | |
119 | EXPORT_SYMBOL_GPL(rtsx_pci_write_register); | |
120 | ||
121 | int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data) | |
122 | { | |
123 | u32 val = HAIMR_READ_START; | |
124 | int i; | |
125 | ||
126 | val |= (u32)(addr & 0x3FFF) << 16; | |
127 | rtsx_pci_writel(pcr, RTSX_HAIMR, val); | |
128 | ||
129 | for (i = 0; i < MAX_RW_REG_CNT; i++) { | |
130 | val = rtsx_pci_readl(pcr, RTSX_HAIMR); | |
131 | if ((val & HAIMR_TRANS_END) == 0) | |
132 | break; | |
133 | } | |
134 | ||
135 | if (i >= MAX_RW_REG_CNT) | |
136 | return -ETIMEDOUT; | |
137 | ||
138 | if (data) | |
139 | *data = (u8)(val & 0xFF); | |
140 | ||
141 | return 0; | |
142 | } | |
143 | EXPORT_SYMBOL_GPL(rtsx_pci_read_register); | |
144 | ||
145 | int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val) | |
146 | { | |
147 | int err, i, finished = 0; | |
148 | u8 tmp; | |
149 | ||
150 | rtsx_pci_init_cmd(pcr); | |
151 | ||
152 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA0, 0xFF, (u8)val); | |
153 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYDATA1, 0xFF, (u8)(val >> 8)); | |
154 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); | |
155 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x81); | |
156 | ||
157 | err = rtsx_pci_send_cmd(pcr, 100); | |
158 | if (err < 0) | |
159 | return err; | |
160 | ||
161 | for (i = 0; i < 100000; i++) { | |
162 | err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); | |
163 | if (err < 0) | |
164 | return err; | |
165 | ||
166 | if (!(tmp & 0x80)) { | |
167 | finished = 1; | |
168 | break; | |
169 | } | |
170 | } | |
171 | ||
172 | if (!finished) | |
173 | return -ETIMEDOUT; | |
174 | ||
175 | return 0; | |
176 | } | |
177 | EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register); | |
178 | ||
179 | int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val) | |
180 | { | |
181 | int err, i, finished = 0; | |
182 | u16 data; | |
183 | u8 *ptr, tmp; | |
184 | ||
185 | rtsx_pci_init_cmd(pcr); | |
186 | ||
187 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYADDR, 0xFF, addr); | |
188 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PHYRWCTL, 0xFF, 0x80); | |
189 | ||
190 | err = rtsx_pci_send_cmd(pcr, 100); | |
191 | if (err < 0) | |
192 | return err; | |
193 | ||
194 | for (i = 0; i < 100000; i++) { | |
195 | err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp); | |
196 | if (err < 0) | |
197 | return err; | |
198 | ||
199 | if (!(tmp & 0x80)) { | |
200 | finished = 1; | |
201 | break; | |
202 | } | |
203 | } | |
204 | ||
205 | if (!finished) | |
206 | return -ETIMEDOUT; | |
207 | ||
208 | rtsx_pci_init_cmd(pcr); | |
209 | ||
210 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA0, 0, 0); | |
211 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, PHYDATA1, 0, 0); | |
212 | ||
213 | err = rtsx_pci_send_cmd(pcr, 100); | |
214 | if (err < 0) | |
215 | return err; | |
216 | ||
217 | ptr = rtsx_pci_get_cmd_data(pcr); | |
218 | data = ((u16)ptr[1] << 8) | ptr[0]; | |
219 | ||
220 | if (val) | |
221 | *val = data; | |
222 | ||
223 | return 0; | |
224 | } | |
225 | EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register); | |
226 | ||
227 | void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr) | |
228 | { | |
229 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); | |
230 | rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); | |
231 | ||
232 | rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80); | |
233 | rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80); | |
234 | } | |
235 | EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd); | |
236 | ||
237 | void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, | |
238 | u8 cmd_type, u16 reg_addr, u8 mask, u8 data) | |
239 | { | |
240 | unsigned long flags; | |
241 | u32 val = 0; | |
242 | u32 *ptr = (u32 *)(pcr->host_cmds_ptr); | |
243 | ||
244 | val |= (u32)(cmd_type & 0x03) << 30; | |
245 | val |= (u32)(reg_addr & 0x3FFF) << 16; | |
246 | val |= (u32)mask << 8; | |
247 | val |= (u32)data; | |
248 | ||
249 | spin_lock_irqsave(&pcr->lock, flags); | |
250 | ptr += pcr->ci; | |
251 | if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) { | |
252 | put_unaligned_le32(val, ptr); | |
253 | ptr++; | |
254 | pcr->ci++; | |
255 | } | |
256 | spin_unlock_irqrestore(&pcr->lock, flags); | |
257 | } | |
258 | EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd); | |
259 | ||
260 | void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr) | |
261 | { | |
262 | u32 val = 1 << 31; | |
263 | ||
264 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); | |
265 | ||
266 | val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; | |
267 | /* Hardware Auto Response */ | |
268 | val |= 0x40000000; | |
269 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); | |
270 | } | |
271 | EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait); | |
272 | ||
273 | int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout) | |
274 | { | |
275 | struct completion trans_done; | |
276 | u32 val = 1 << 31; | |
277 | long timeleft; | |
278 | unsigned long flags; | |
279 | int err = 0; | |
280 | ||
281 | spin_lock_irqsave(&pcr->lock, flags); | |
282 | ||
283 | /* set up data structures for the wakeup system */ | |
284 | pcr->done = &trans_done; | |
285 | pcr->trans_result = TRANS_NOT_READY; | |
286 | init_completion(&trans_done); | |
287 | ||
288 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); | |
289 | ||
290 | val |= (u32)(pcr->ci * 4) & 0x00FFFFFF; | |
291 | /* Hardware Auto Response */ | |
292 | val |= 0x40000000; | |
293 | rtsx_pci_writel(pcr, RTSX_HCBCTLR, val); | |
294 | ||
295 | spin_unlock_irqrestore(&pcr->lock, flags); | |
296 | ||
297 | /* Wait for TRANS_OK_INT */ | |
298 | timeleft = wait_for_completion_interruptible_timeout( | |
299 | &trans_done, msecs_to_jiffies(timeout)); | |
300 | if (timeleft <= 0) { | |
301 | dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n", | |
302 | __func__, __LINE__); | |
303 | err = -ETIMEDOUT; | |
304 | goto finish_send_cmd; | |
305 | } | |
306 | ||
307 | spin_lock_irqsave(&pcr->lock, flags); | |
308 | if (pcr->trans_result == TRANS_RESULT_FAIL) | |
309 | err = -EINVAL; | |
310 | else if (pcr->trans_result == TRANS_RESULT_OK) | |
311 | err = 0; | |
312 | else if (pcr->trans_result == TRANS_NO_DEVICE) | |
313 | err = -ENODEV; | |
314 | spin_unlock_irqrestore(&pcr->lock, flags); | |
315 | ||
316 | finish_send_cmd: | |
317 | spin_lock_irqsave(&pcr->lock, flags); | |
318 | pcr->done = NULL; | |
319 | spin_unlock_irqrestore(&pcr->lock, flags); | |
320 | ||
321 | if ((err < 0) && (err != -ENODEV)) | |
322 | rtsx_pci_stop_cmd(pcr); | |
323 | ||
324 | if (pcr->finish_me) | |
325 | complete(pcr->finish_me); | |
326 | ||
327 | return err; | |
328 | } | |
329 | EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd); | |
330 | ||
331 | static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr, | |
332 | dma_addr_t addr, unsigned int len, int end) | |
333 | { | |
334 | u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi; | |
335 | u64 val; | |
336 | u8 option = SG_VALID | SG_TRANS_DATA; | |
337 | ||
338 | dev_dbg(&(pcr->pci->dev), "DMA addr: 0x%x, Len: 0x%x\n", | |
339 | (unsigned int)addr, len); | |
340 | ||
341 | if (end) | |
342 | option |= SG_END; | |
343 | val = ((u64)addr << 32) | ((u64)len << 12) | option; | |
344 | ||
345 | put_unaligned_le64(val, ptr); | |
ada8a8a1 WW |
346 | pcr->sgi++; |
347 | } | |
348 | ||
349 | int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
350 | int num_sg, bool read, int timeout) | |
351 | { | |
8cd11830 | 352 | int err = 0, count; |
98fcc576 MC |
353 | |
354 | dev_dbg(&(pcr->pci->dev), "--> %s: num_sg = %d\n", __func__, num_sg); | |
8cd11830 MC |
355 | count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read); |
356 | if (count < 1) | |
357 | return -EINVAL; | |
358 | dev_dbg(&(pcr->pci->dev), "DMA mapping count: %d\n", count); | |
359 | ||
360 | err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout); | |
361 | ||
362 | rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read); | |
363 | ||
364 | return err; | |
365 | } | |
366 | EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data); | |
367 | ||
368 | int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
369 | int num_sg, bool read) | |
370 | { | |
371 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
98fcc576 | 372 | |
98fcc576 MC |
373 | if (pcr->remove_pci) |
374 | return -EINVAL; | |
375 | ||
376 | if ((sglist == NULL) || (num_sg <= 0)) | |
377 | return -EINVAL; | |
ada8a8a1 | 378 | |
8cd11830 MC |
379 | return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir); |
380 | } | |
381 | EXPORT_SYMBOL_GPL(rtsx_pci_dma_map_sg); | |
382 | ||
383 | void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
384 | int num_sg, bool read) | |
385 | { | |
386 | enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
387 | ||
388 | dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir); | |
389 | } | |
390 | EXPORT_SYMBOL_GPL(rtsx_pci_dma_unmap_sg); | |
391 | ||
392 | int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
393 | int count, bool read, int timeout) | |
394 | { | |
395 | struct completion trans_done; | |
396 | struct scatterlist *sg; | |
397 | dma_addr_t addr; | |
398 | long timeleft; | |
399 | unsigned long flags; | |
400 | unsigned int len; | |
401 | int i, err = 0; | |
402 | u32 val; | |
403 | u8 dir = read ? DEVICE_TO_HOST : HOST_TO_DEVICE; | |
98fcc576 | 404 | |
8cd11830 MC |
405 | if (pcr->remove_pci) |
406 | return -ENODEV; | |
407 | ||
408 | if ((sglist == NULL) || (count < 1)) | |
ada8a8a1 | 409 | return -EINVAL; |
ada8a8a1 | 410 | |
98fcc576 MC |
411 | val = ((u32)(dir & 0x01) << 29) | TRIG_DMA | ADMA_MODE; |
412 | pcr->sgi = 0; | |
413 | for_each_sg(sglist, sg, count, i) { | |
414 | addr = sg_dma_address(sg); | |
415 | len = sg_dma_len(sg); | |
416 | rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1); | |
417 | } | |
ada8a8a1 WW |
418 | |
419 | spin_lock_irqsave(&pcr->lock, flags); | |
420 | ||
421 | pcr->done = &trans_done; | |
422 | pcr->trans_result = TRANS_NOT_READY; | |
423 | init_completion(&trans_done); | |
98fcc576 MC |
424 | rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr); |
425 | rtsx_pci_writel(pcr, RTSX_HDBCTLR, val); | |
ada8a8a1 WW |
426 | |
427 | spin_unlock_irqrestore(&pcr->lock, flags); | |
428 | ||
429 | timeleft = wait_for_completion_interruptible_timeout( | |
430 | &trans_done, msecs_to_jiffies(timeout)); | |
431 | if (timeleft <= 0) { | |
432 | dev_dbg(&(pcr->pci->dev), "Timeout (%s %d)\n", | |
433 | __func__, __LINE__); | |
434 | err = -ETIMEDOUT; | |
435 | goto out; | |
436 | } | |
437 | ||
438 | spin_lock_irqsave(&pcr->lock, flags); | |
ada8a8a1 WW |
439 | if (pcr->trans_result == TRANS_RESULT_FAIL) |
440 | err = -EINVAL; | |
441 | else if (pcr->trans_result == TRANS_NO_DEVICE) | |
442 | err = -ENODEV; | |
ada8a8a1 WW |
443 | spin_unlock_irqrestore(&pcr->lock, flags); |
444 | ||
445 | out: | |
446 | spin_lock_irqsave(&pcr->lock, flags); | |
447 | pcr->done = NULL; | |
448 | spin_unlock_irqrestore(&pcr->lock, flags); | |
449 | ||
ada8a8a1 WW |
450 | if ((err < 0) && (err != -ENODEV)) |
451 | rtsx_pci_stop_cmd(pcr); | |
452 | ||
453 | if (pcr->finish_me) | |
454 | complete(pcr->finish_me); | |
455 | ||
456 | return err; | |
457 | } | |
8cd11830 | 458 | EXPORT_SYMBOL_GPL(rtsx_pci_dma_transfer); |
ada8a8a1 WW |
459 | |
460 | int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) | |
461 | { | |
462 | int err; | |
463 | int i, j; | |
464 | u16 reg; | |
465 | u8 *ptr; | |
466 | ||
467 | if (buf_len > 512) | |
468 | buf_len = 512; | |
469 | ||
470 | ptr = buf; | |
471 | reg = PPBUF_BASE2; | |
472 | for (i = 0; i < buf_len / 256; i++) { | |
473 | rtsx_pci_init_cmd(pcr); | |
474 | ||
475 | for (j = 0; j < 256; j++) | |
476 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); | |
477 | ||
478 | err = rtsx_pci_send_cmd(pcr, 250); | |
479 | if (err < 0) | |
480 | return err; | |
481 | ||
482 | memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256); | |
483 | ptr += 256; | |
484 | } | |
485 | ||
486 | if (buf_len % 256) { | |
487 | rtsx_pci_init_cmd(pcr); | |
488 | ||
489 | for (j = 0; j < buf_len % 256; j++) | |
490 | rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0); | |
491 | ||
492 | err = rtsx_pci_send_cmd(pcr, 250); | |
493 | if (err < 0) | |
494 | return err; | |
495 | } | |
496 | ||
497 | memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256); | |
498 | ||
499 | return 0; | |
500 | } | |
501 | EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf); | |
502 | ||
503 | int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len) | |
504 | { | |
505 | int err; | |
506 | int i, j; | |
507 | u16 reg; | |
508 | u8 *ptr; | |
509 | ||
510 | if (buf_len > 512) | |
511 | buf_len = 512; | |
512 | ||
513 | ptr = buf; | |
514 | reg = PPBUF_BASE2; | |
515 | for (i = 0; i < buf_len / 256; i++) { | |
516 | rtsx_pci_init_cmd(pcr); | |
517 | ||
518 | for (j = 0; j < 256; j++) { | |
519 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
520 | reg++, 0xFF, *ptr); | |
521 | ptr++; | |
522 | } | |
523 | ||
524 | err = rtsx_pci_send_cmd(pcr, 250); | |
525 | if (err < 0) | |
526 | return err; | |
527 | } | |
528 | ||
529 | if (buf_len % 256) { | |
530 | rtsx_pci_init_cmd(pcr); | |
531 | ||
532 | for (j = 0; j < buf_len % 256; j++) { | |
533 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
534 | reg++, 0xFF, *ptr); | |
535 | ptr++; | |
536 | } | |
537 | ||
538 | err = rtsx_pci_send_cmd(pcr, 250); | |
539 | if (err < 0) | |
540 | return err; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf); | |
546 | ||
547 | static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl) | |
548 | { | |
549 | int err; | |
550 | ||
551 | rtsx_pci_init_cmd(pcr); | |
552 | ||
553 | while (*tbl & 0xFFFF0000) { | |
554 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
555 | (u16)(*tbl >> 16), 0xFF, (u8)(*tbl)); | |
556 | tbl++; | |
557 | } | |
558 | ||
559 | err = rtsx_pci_send_cmd(pcr, 100); | |
560 | if (err < 0) | |
561 | return err; | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card) | |
567 | { | |
568 | const u32 *tbl; | |
569 | ||
570 | if (card == RTSX_SD_CARD) | |
571 | tbl = pcr->sd_pull_ctl_enable_tbl; | |
572 | else if (card == RTSX_MS_CARD) | |
573 | tbl = pcr->ms_pull_ctl_enable_tbl; | |
574 | else | |
575 | return -EINVAL; | |
576 | ||
577 | return rtsx_pci_set_pull_ctl(pcr, tbl); | |
578 | } | |
579 | EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable); | |
580 | ||
581 | int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card) | |
582 | { | |
583 | const u32 *tbl; | |
584 | ||
585 | if (card == RTSX_SD_CARD) | |
586 | tbl = pcr->sd_pull_ctl_disable_tbl; | |
587 | else if (card == RTSX_MS_CARD) | |
588 | tbl = pcr->ms_pull_ctl_disable_tbl; | |
589 | else | |
590 | return -EINVAL; | |
591 | ||
592 | ||
593 | return rtsx_pci_set_pull_ctl(pcr, tbl); | |
594 | } | |
595 | EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable); | |
596 | ||
597 | static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr) | |
598 | { | |
599 | pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN; | |
600 | ||
601 | if (pcr->num_slots > 1) | |
602 | pcr->bier |= MS_INT_EN; | |
603 | ||
604 | /* Enable Bus Interrupt */ | |
605 | rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier); | |
606 | ||
607 | dev_dbg(&(pcr->pci->dev), "RTSX_BIER: 0x%08x\n", pcr->bier); | |
608 | } | |
609 | ||
610 | static inline u8 double_ssc_depth(u8 depth) | |
611 | { | |
612 | return ((depth > 1) ? (depth - 1) : depth); | |
613 | } | |
614 | ||
615 | static u8 revise_ssc_depth(u8 ssc_depth, u8 div) | |
616 | { | |
617 | if (div > CLK_DIV_1) { | |
618 | if (ssc_depth > (div - 1)) | |
619 | ssc_depth -= (div - 1); | |
620 | else | |
621 | ssc_depth = SSC_DEPTH_4M; | |
622 | } | |
623 | ||
624 | return ssc_depth; | |
625 | } | |
626 | ||
627 | int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, | |
628 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) | |
629 | { | |
630 | int err, clk; | |
eebbe254 | 631 | u8 n, clk_divider, mcu_cnt, div; |
ada8a8a1 WW |
632 | u8 depth[] = { |
633 | [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, | |
634 | [RTSX_SSC_DEPTH_2M] = SSC_DEPTH_2M, | |
635 | [RTSX_SSC_DEPTH_1M] = SSC_DEPTH_1M, | |
636 | [RTSX_SSC_DEPTH_500K] = SSC_DEPTH_500K, | |
637 | [RTSX_SSC_DEPTH_250K] = SSC_DEPTH_250K, | |
638 | }; | |
639 | ||
640 | if (initial_mode) { | |
641 | /* We use 250k(around) here, in initial stage */ | |
642 | clk_divider = SD_CLK_DIVIDE_128; | |
643 | card_clock = 30000000; | |
644 | } else { | |
645 | clk_divider = SD_CLK_DIVIDE_0; | |
646 | } | |
647 | err = rtsx_pci_write_register(pcr, SD_CFG1, | |
648 | SD_CLK_DIVIDE_MASK, clk_divider); | |
649 | if (err < 0) | |
650 | return err; | |
651 | ||
652 | card_clock /= 1000000; | |
653 | dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock); | |
654 | ||
ada8a8a1 WW |
655 | clk = card_clock; |
656 | if (!initial_mode && double_clk) | |
657 | clk = card_clock * 2; | |
658 | dev_dbg(&(pcr->pci->dev), | |
659 | "Internal SSC clock: %dMHz (cur_clock = %d)\n", | |
660 | clk, pcr->cur_clock); | |
661 | ||
662 | if (clk == pcr->cur_clock) | |
663 | return 0; | |
664 | ||
ab4e8f8b | 665 | if (pcr->ops->conv_clk_and_div_n) |
678cacdf | 666 | n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); |
ab4e8f8b | 667 | else |
678cacdf | 668 | n = (u8)(clk - 2); |
eebbe254 | 669 | if ((clk <= 2) || (n > MAX_DIV_N_PCR)) |
ada8a8a1 WW |
670 | return -EINVAL; |
671 | ||
672 | mcu_cnt = (u8)(125/clk + 3); | |
673 | if (mcu_cnt > 15) | |
674 | mcu_cnt = 15; | |
675 | ||
eebbe254 | 676 | /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */ |
ada8a8a1 | 677 | div = CLK_DIV_1; |
eebbe254 | 678 | while ((n < MIN_DIV_N_PCR) && (div < CLK_DIV_8)) { |
ab4e8f8b | 679 | if (pcr->ops->conv_clk_and_div_n) { |
678cacdf | 680 | int dbl_clk = pcr->ops->conv_clk_and_div_n(n, |
ab4e8f8b | 681 | DIV_N_TO_CLK) * 2; |
678cacdf | 682 | n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, |
ab4e8f8b WW |
683 | CLK_TO_DIV_N); |
684 | } else { | |
678cacdf | 685 | n = (n + 2) * 2 - 2; |
ab4e8f8b | 686 | } |
ada8a8a1 WW |
687 | div++; |
688 | } | |
678cacdf | 689 | dev_dbg(&(pcr->pci->dev), "n = %d, div = %d\n", n, div); |
ada8a8a1 WW |
690 | |
691 | ssc_depth = depth[ssc_depth]; | |
692 | if (double_clk) | |
693 | ssc_depth = double_ssc_depth(ssc_depth); | |
694 | ||
695 | ssc_depth = revise_ssc_depth(ssc_depth, div); | |
696 | dev_dbg(&(pcr->pci->dev), "ssc_depth = %d\n", ssc_depth); | |
697 | ||
698 | rtsx_pci_init_cmd(pcr); | |
699 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, | |
700 | CLK_LOW_FREQ, CLK_LOW_FREQ); | |
701 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, | |
702 | 0xFF, (div << 4) | mcu_cnt); | |
703 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); | |
704 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, | |
705 | SSC_DEPTH_MASK, ssc_depth); | |
678cacdf | 706 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); |
ada8a8a1 WW |
707 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); |
708 | if (vpclk) { | |
709 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, | |
710 | PHASE_NOT_RESET, 0); | |
711 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, | |
712 | PHASE_NOT_RESET, PHASE_NOT_RESET); | |
713 | } | |
714 | ||
715 | err = rtsx_pci_send_cmd(pcr, 2000); | |
716 | if (err < 0) | |
717 | return err; | |
718 | ||
719 | /* Wait SSC clock stable */ | |
720 | udelay(10); | |
721 | err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); | |
722 | if (err < 0) | |
723 | return err; | |
724 | ||
725 | pcr->cur_clock = clk; | |
726 | return 0; | |
727 | } | |
728 | EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock); | |
729 | ||
730 | int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card) | |
731 | { | |
732 | if (pcr->ops->card_power_on) | |
733 | return pcr->ops->card_power_on(pcr, card); | |
734 | ||
735 | return 0; | |
736 | } | |
737 | EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on); | |
738 | ||
739 | int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card) | |
740 | { | |
741 | if (pcr->ops->card_power_off) | |
742 | return pcr->ops->card_power_off(pcr, card); | |
743 | ||
744 | return 0; | |
745 | } | |
746 | EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off); | |
747 | ||
c3481955 WW |
748 | int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card) |
749 | { | |
750 | unsigned int cd_mask[] = { | |
751 | [RTSX_SD_CARD] = SD_EXIST, | |
752 | [RTSX_MS_CARD] = MS_EXIST | |
753 | }; | |
754 | ||
773ccdfd | 755 | if (!(pcr->flags & PCR_MS_PMOS)) { |
c3481955 WW |
756 | /* When using single PMOS, accessing card is not permitted |
757 | * if the existing card is not the designated one. | |
758 | */ | |
759 | if (pcr->card_exist & (~cd_mask[card])) | |
760 | return -EIO; | |
761 | } | |
762 | ||
763 | return 0; | |
764 | } | |
765 | EXPORT_SYMBOL_GPL(rtsx_pci_card_exclusive_check); | |
766 | ||
d817ac4e WW |
767 | int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) |
768 | { | |
769 | if (pcr->ops->switch_output_voltage) | |
770 | return pcr->ops->switch_output_voltage(pcr, voltage); | |
771 | ||
772 | return 0; | |
773 | } | |
774 | EXPORT_SYMBOL_GPL(rtsx_pci_switch_output_voltage); | |
775 | ||
ada8a8a1 WW |
776 | unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr) |
777 | { | |
778 | unsigned int val; | |
779 | ||
780 | val = rtsx_pci_readl(pcr, RTSX_BIPR); | |
781 | if (pcr->ops->cd_deglitch) | |
782 | val = pcr->ops->cd_deglitch(pcr); | |
783 | ||
784 | return val; | |
785 | } | |
786 | EXPORT_SYMBOL_GPL(rtsx_pci_card_exist); | |
787 | ||
788 | void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr) | |
789 | { | |
790 | struct completion finish; | |
791 | ||
792 | pcr->finish_me = &finish; | |
793 | init_completion(&finish); | |
794 | ||
795 | if (pcr->done) | |
796 | complete(pcr->done); | |
797 | ||
798 | if (!pcr->remove_pci) | |
799 | rtsx_pci_stop_cmd(pcr); | |
800 | ||
801 | wait_for_completion_interruptible_timeout(&finish, | |
802 | msecs_to_jiffies(2)); | |
803 | pcr->finish_me = NULL; | |
804 | } | |
805 | EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer); | |
806 | ||
807 | static void rtsx_pci_card_detect(struct work_struct *work) | |
808 | { | |
809 | struct delayed_work *dwork; | |
810 | struct rtsx_pcr *pcr; | |
811 | unsigned long flags; | |
504decc0 | 812 | unsigned int card_detect = 0, card_inserted, card_removed; |
ada8a8a1 WW |
813 | u32 irq_status; |
814 | ||
815 | dwork = to_delayed_work(work); | |
816 | pcr = container_of(dwork, struct rtsx_pcr, carddet_work); | |
817 | ||
818 | dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__); | |
819 | ||
504decc0 | 820 | mutex_lock(&pcr->pcr_mutex); |
ada8a8a1 WW |
821 | spin_lock_irqsave(&pcr->lock, flags); |
822 | ||
823 | irq_status = rtsx_pci_readl(pcr, RTSX_BIPR); | |
824 | dev_dbg(&(pcr->pci->dev), "irq_status: 0x%08x\n", irq_status); | |
825 | ||
504decc0 WW |
826 | irq_status &= CARD_EXIST; |
827 | card_inserted = pcr->card_inserted & irq_status; | |
828 | card_removed = pcr->card_removed; | |
829 | pcr->card_inserted = 0; | |
830 | pcr->card_removed = 0; | |
831 | ||
832 | spin_unlock_irqrestore(&pcr->lock, flags); | |
833 | ||
834 | if (card_inserted || card_removed) { | |
ada8a8a1 WW |
835 | dev_dbg(&(pcr->pci->dev), |
836 | "card_inserted: 0x%x, card_removed: 0x%x\n", | |
504decc0 | 837 | card_inserted, card_removed); |
ada8a8a1 WW |
838 | |
839 | if (pcr->ops->cd_deglitch) | |
504decc0 | 840 | card_inserted = pcr->ops->cd_deglitch(pcr); |
ada8a8a1 | 841 | |
504decc0 | 842 | card_detect = card_inserted | card_removed; |
c3481955 WW |
843 | |
844 | pcr->card_exist |= card_inserted; | |
845 | pcr->card_exist &= ~card_removed; | |
ada8a8a1 WW |
846 | } |
847 | ||
504decc0 | 848 | mutex_unlock(&pcr->pcr_mutex); |
ada8a8a1 | 849 | |
2d1484f5 | 850 | if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event) |
ada8a8a1 WW |
851 | pcr->slots[RTSX_SD_CARD].card_event( |
852 | pcr->slots[RTSX_SD_CARD].p_dev); | |
2d1484f5 | 853 | if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event) |
ada8a8a1 WW |
854 | pcr->slots[RTSX_MS_CARD].card_event( |
855 | pcr->slots[RTSX_MS_CARD].p_dev); | |
856 | } | |
857 | ||
858 | static irqreturn_t rtsx_pci_isr(int irq, void *dev_id) | |
859 | { | |
860 | struct rtsx_pcr *pcr = dev_id; | |
861 | u32 int_reg; | |
862 | ||
863 | if (!pcr) | |
864 | return IRQ_NONE; | |
865 | ||
866 | spin_lock(&pcr->lock); | |
867 | ||
868 | int_reg = rtsx_pci_readl(pcr, RTSX_BIPR); | |
869 | /* Clear interrupt flag */ | |
870 | rtsx_pci_writel(pcr, RTSX_BIPR, int_reg); | |
871 | if ((int_reg & pcr->bier) == 0) { | |
872 | spin_unlock(&pcr->lock); | |
873 | return IRQ_NONE; | |
874 | } | |
875 | if (int_reg == 0xFFFFFFFF) { | |
876 | spin_unlock(&pcr->lock); | |
877 | return IRQ_HANDLED; | |
878 | } | |
879 | ||
880 | int_reg &= (pcr->bier | 0x7FFFFF); | |
881 | ||
882 | if (int_reg & SD_INT) { | |
883 | if (int_reg & SD_EXIST) { | |
884 | pcr->card_inserted |= SD_EXIST; | |
885 | } else { | |
886 | pcr->card_removed |= SD_EXIST; | |
887 | pcr->card_inserted &= ~SD_EXIST; | |
888 | } | |
889 | } | |
890 | ||
891 | if (int_reg & MS_INT) { | |
892 | if (int_reg & MS_EXIST) { | |
893 | pcr->card_inserted |= MS_EXIST; | |
894 | } else { | |
895 | pcr->card_removed |= MS_EXIST; | |
896 | pcr->card_inserted &= ~MS_EXIST; | |
897 | } | |
898 | } | |
899 | ||
ada8a8a1 | 900 | if (int_reg & (NEED_COMPLETE_INT | DELINK_INT)) { |
98fcc576 | 901 | if (int_reg & (TRANS_FAIL_INT | DELINK_INT)) { |
ada8a8a1 | 902 | pcr->trans_result = TRANS_RESULT_FAIL; |
98fcc576 MC |
903 | if (pcr->done) |
904 | complete(pcr->done); | |
905 | } else if (int_reg & TRANS_OK_INT) { | |
ada8a8a1 | 906 | pcr->trans_result = TRANS_RESULT_OK; |
98fcc576 MC |
907 | if (pcr->done) |
908 | complete(pcr->done); | |
ada8a8a1 WW |
909 | } |
910 | } | |
911 | ||
504decc0 WW |
912 | if (pcr->card_inserted || pcr->card_removed) |
913 | schedule_delayed_work(&pcr->carddet_work, | |
914 | msecs_to_jiffies(200)); | |
915 | ||
ada8a8a1 WW |
916 | spin_unlock(&pcr->lock); |
917 | return IRQ_HANDLED; | |
918 | } | |
919 | ||
920 | static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr) | |
921 | { | |
922 | dev_info(&(pcr->pci->dev), "%s: pcr->msi_en = %d, pci->irq = %d\n", | |
923 | __func__, pcr->msi_en, pcr->pci->irq); | |
924 | ||
925 | if (request_irq(pcr->pci->irq, rtsx_pci_isr, | |
926 | pcr->msi_en ? 0 : IRQF_SHARED, | |
927 | DRV_NAME_RTSX_PCI, pcr)) { | |
928 | dev_err(&(pcr->pci->dev), | |
929 | "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n", | |
930 | pcr->pci->irq); | |
931 | return -1; | |
932 | } | |
933 | ||
934 | pcr->irq = pcr->pci->irq; | |
935 | pci_intx(pcr->pci, !pcr->msi_en); | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static void rtsx_pci_idle_work(struct work_struct *work) | |
941 | { | |
942 | struct delayed_work *dwork = to_delayed_work(work); | |
943 | struct rtsx_pcr *pcr = container_of(dwork, struct rtsx_pcr, idle_work); | |
944 | ||
945 | dev_dbg(&(pcr->pci->dev), "--> %s\n", __func__); | |
946 | ||
947 | mutex_lock(&pcr->pcr_mutex); | |
948 | ||
949 | pcr->state = PDEV_STAT_IDLE; | |
950 | ||
951 | if (pcr->ops->disable_auto_blink) | |
952 | pcr->ops->disable_auto_blink(pcr); | |
953 | if (pcr->ops->turn_off_led) | |
954 | pcr->ops->turn_off_led(pcr); | |
955 | ||
773ccdfd | 956 | if (pcr->aspm_en) |
19f3bd54 | 957 | rtsx_pci_enable_aspm(pcr); |
773ccdfd | 958 | |
ada8a8a1 WW |
959 | mutex_unlock(&pcr->pcr_mutex); |
960 | } | |
961 | ||
451be648 | 962 | #ifdef CONFIG_PM |
5947c167 WW |
963 | static void rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state) |
964 | { | |
965 | if (pcr->ops->turn_off_led) | |
966 | pcr->ops->turn_off_led(pcr); | |
967 | ||
968 | rtsx_pci_writel(pcr, RTSX_BIER, 0); | |
969 | pcr->bier = 0; | |
970 | ||
971 | rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08); | |
972 | rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state); | |
973 | ||
974 | if (pcr->ops->force_power_down) | |
eb891c65 | 975 | pcr->ops->force_power_down(pcr, pm_state); |
5947c167 | 976 | } |
451be648 | 977 | #endif |
5947c167 | 978 | |
ada8a8a1 WW |
979 | static int rtsx_pci_init_hw(struct rtsx_pcr *pcr) |
980 | { | |
981 | int err; | |
982 | ||
19f3bd54 | 983 | pcr->pcie_cap = pci_find_capability(pcr->pci, PCI_CAP_ID_EXP); |
ada8a8a1 WW |
984 | rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr); |
985 | ||
986 | rtsx_pci_enable_bus_int(pcr); | |
987 | ||
988 | /* Power on SSC */ | |
989 | err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0); | |
990 | if (err < 0) | |
991 | return err; | |
992 | ||
993 | /* Wait SSC power stable */ | |
994 | udelay(200); | |
995 | ||
19f3bd54 | 996 | rtsx_pci_disable_aspm(pcr); |
ada8a8a1 WW |
997 | if (pcr->ops->optimize_phy) { |
998 | err = pcr->ops->optimize_phy(pcr); | |
999 | if (err < 0) | |
1000 | return err; | |
1001 | } | |
1002 | ||
1003 | rtsx_pci_init_cmd(pcr); | |
1004 | ||
1005 | /* Set mcu_cnt to 7 to ensure data can be sampled properly */ | |
1006 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); | |
1007 | ||
1008 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00); | |
1009 | /* Disable card clock */ | |
1010 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0); | |
ada8a8a1 WW |
1011 | /* Reset delink mode */ |
1012 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0); | |
1013 | /* Card driving select */ | |
773ccdfd WW |
1014 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL, |
1015 | 0xFF, pcr->card_drive_sel); | |
ada8a8a1 WW |
1016 | /* Enable SSC Clock */ |
1017 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, | |
1018 | 0xFF, SSC_8X_EN | SSC_SEL_4M); | |
1019 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12); | |
1020 | /* Disable cd_pwr_save */ | |
1021 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10); | |
1022 | /* Clear Link Ready Interrupt */ | |
1023 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, | |
1024 | LINK_RDY_INT, LINK_RDY_INT); | |
1025 | /* Enlarge the estimation window of PERST# glitch | |
1026 | * to reduce the chance of invalid card interrupt | |
1027 | */ | |
1028 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80); | |
1029 | /* Update RC oscillator to 400k | |
1030 | * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1 | |
1031 | * 1: 2M 0: 400k | |
1032 | */ | |
1033 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00); | |
1034 | /* Set interrupt write clear | |
1035 | * bit 1: U_elbi_if_rd_clr_en | |
1036 | * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear | |
1037 | * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear | |
1038 | */ | |
1039 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0); | |
ada8a8a1 WW |
1040 | |
1041 | err = rtsx_pci_send_cmd(pcr, 100); | |
1042 | if (err < 0) | |
1043 | return err; | |
1044 | ||
1045 | /* Enable clk_request_n to enable clock power management */ | |
19f3bd54 | 1046 | rtsx_pci_write_config_byte(pcr, pcr->pcie_cap + PCI_EXP_LNKCTL + 1, 1); |
ada8a8a1 WW |
1047 | /* Enter L1 when host tx idle */ |
1048 | rtsx_pci_write_config_byte(pcr, 0x70F, 0x5B); | |
1049 | ||
1050 | if (pcr->ops->extra_init_hw) { | |
1051 | err = pcr->ops->extra_init_hw(pcr); | |
1052 | if (err < 0) | |
1053 | return err; | |
1054 | } | |
1055 | ||
c3481955 WW |
1056 | /* No CD interrupt if probing driver with card inserted. |
1057 | * So we need to initialize pcr->card_exist here. | |
1058 | */ | |
1059 | if (pcr->ops->cd_deglitch) | |
1060 | pcr->card_exist = pcr->ops->cd_deglitch(pcr); | |
1061 | else | |
1062 | pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST; | |
1063 | ||
ada8a8a1 WW |
1064 | return 0; |
1065 | } | |
1066 | ||
1067 | static int rtsx_pci_init_chip(struct rtsx_pcr *pcr) | |
1068 | { | |
1069 | int err; | |
1070 | ||
1071 | spin_lock_init(&pcr->lock); | |
1072 | mutex_init(&pcr->pcr_mutex); | |
1073 | ||
1074 | switch (PCI_PID(pcr)) { | |
1075 | default: | |
1076 | case 0x5209: | |
1077 | rts5209_init_params(pcr); | |
1078 | break; | |
1079 | ||
1080 | case 0x5229: | |
1081 | rts5229_init_params(pcr); | |
1082 | break; | |
1083 | ||
1084 | case 0x5289: | |
1085 | rtl8411_init_params(pcr); | |
1086 | break; | |
e1237932 RT |
1087 | |
1088 | case 0x5227: | |
1089 | rts5227_init_params(pcr); | |
1090 | break; | |
4c4b8c10 WW |
1091 | |
1092 | case 0x5249: | |
1093 | rts5249_init_params(pcr); | |
1094 | break; | |
9032eabd RT |
1095 | |
1096 | case 0x5287: | |
1097 | rtl8411b_init_params(pcr); | |
1098 | break; | |
56cb3cc1 MC |
1099 | |
1100 | case 0x5286: | |
1101 | rtl8402_init_params(pcr); | |
1102 | break; | |
ada8a8a1 WW |
1103 | } |
1104 | ||
1105 | dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n", | |
1106 | PCI_PID(pcr), pcr->ic_version); | |
1107 | ||
1108 | pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot), | |
1109 | GFP_KERNEL); | |
1110 | if (!pcr->slots) | |
1111 | return -ENOMEM; | |
1112 | ||
773ccdfd WW |
1113 | if (pcr->ops->fetch_vendor_settings) |
1114 | pcr->ops->fetch_vendor_settings(pcr); | |
1115 | ||
1116 | dev_dbg(&(pcr->pci->dev), "pcr->aspm_en = 0x%x\n", pcr->aspm_en); | |
1117 | dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_1v8 = 0x%x\n", | |
1118 | pcr->sd30_drive_sel_1v8); | |
1119 | dev_dbg(&(pcr->pci->dev), "pcr->sd30_drive_sel_3v3 = 0x%x\n", | |
1120 | pcr->sd30_drive_sel_3v3); | |
1121 | dev_dbg(&(pcr->pci->dev), "pcr->card_drive_sel = 0x%x\n", | |
1122 | pcr->card_drive_sel); | |
1123 | dev_dbg(&(pcr->pci->dev), "pcr->flags = 0x%x\n", pcr->flags); | |
1124 | ||
ada8a8a1 WW |
1125 | pcr->state = PDEV_STAT_IDLE; |
1126 | err = rtsx_pci_init_hw(pcr); | |
1127 | if (err < 0) { | |
1128 | kfree(pcr->slots); | |
1129 | return err; | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
612b95cd GKH |
1135 | static int rtsx_pci_probe(struct pci_dev *pcidev, |
1136 | const struct pci_device_id *id) | |
ada8a8a1 WW |
1137 | { |
1138 | struct rtsx_pcr *pcr; | |
1139 | struct pcr_handle *handle; | |
1140 | u32 base, len; | |
1141 | int ret, i; | |
1142 | ||
1143 | dev_dbg(&(pcidev->dev), | |
1144 | ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n", | |
1145 | pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device, | |
1146 | (int)pcidev->revision); | |
1147 | ||
f84ef042 WW |
1148 | ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); |
1149 | if (ret < 0) | |
1150 | return ret; | |
1151 | ||
ada8a8a1 WW |
1152 | ret = pci_enable_device(pcidev); |
1153 | if (ret) | |
1154 | return ret; | |
1155 | ||
1156 | ret = pci_request_regions(pcidev, DRV_NAME_RTSX_PCI); | |
1157 | if (ret) | |
1158 | goto disable; | |
1159 | ||
1160 | pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); | |
1161 | if (!pcr) { | |
1162 | ret = -ENOMEM; | |
1163 | goto release_pci; | |
1164 | } | |
1165 | ||
1166 | handle = kzalloc(sizeof(*handle), GFP_KERNEL); | |
1167 | if (!handle) { | |
1168 | ret = -ENOMEM; | |
1169 | goto free_pcr; | |
1170 | } | |
1171 | handle->pcr = pcr; | |
1172 | ||
9f12563d | 1173 | idr_preload(GFP_KERNEL); |
ada8a8a1 | 1174 | spin_lock(&rtsx_pci_lock); |
9f12563d TH |
1175 | ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT); |
1176 | if (ret >= 0) | |
1177 | pcr->id = ret; | |
ada8a8a1 | 1178 | spin_unlock(&rtsx_pci_lock); |
9f12563d TH |
1179 | idr_preload_end(); |
1180 | if (ret < 0) | |
ada8a8a1 WW |
1181 | goto free_handle; |
1182 | ||
1183 | pcr->pci = pcidev; | |
1184 | dev_set_drvdata(&pcidev->dev, handle); | |
1185 | ||
1186 | len = pci_resource_len(pcidev, 0); | |
1187 | base = pci_resource_start(pcidev, 0); | |
1188 | pcr->remap_addr = ioremap_nocache(base, len); | |
1189 | if (!pcr->remap_addr) { | |
1190 | ret = -ENOMEM; | |
af1192d7 | 1191 | goto free_handle; |
ada8a8a1 WW |
1192 | } |
1193 | ||
1194 | pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev), | |
1195 | RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr), | |
1196 | GFP_KERNEL); | |
1197 | if (pcr->rtsx_resv_buf == NULL) { | |
1198 | ret = -ENXIO; | |
1199 | goto unmap; | |
1200 | } | |
1201 | pcr->host_cmds_ptr = pcr->rtsx_resv_buf; | |
1202 | pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr; | |
1203 | pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN; | |
1204 | pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN; | |
1205 | ||
1206 | pcr->card_inserted = 0; | |
1207 | pcr->card_removed = 0; | |
1208 | INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect); | |
1209 | INIT_DELAYED_WORK(&pcr->idle_work, rtsx_pci_idle_work); | |
1210 | ||
1211 | pcr->msi_en = msi_en; | |
1212 | if (pcr->msi_en) { | |
1213 | ret = pci_enable_msi(pcidev); | |
51529705 | 1214 | if (ret) |
ada8a8a1 WW |
1215 | pcr->msi_en = false; |
1216 | } | |
1217 | ||
1218 | ret = rtsx_pci_acquire_irq(pcr); | |
1219 | if (ret < 0) | |
9d66b568 | 1220 | goto disable_msi; |
ada8a8a1 WW |
1221 | |
1222 | pci_set_master(pcidev); | |
1223 | synchronize_irq(pcr->irq); | |
1224 | ||
1225 | ret = rtsx_pci_init_chip(pcr); | |
1226 | if (ret < 0) | |
1227 | goto disable_irq; | |
1228 | ||
1229 | for (i = 0; i < ARRAY_SIZE(rtsx_pcr_cells); i++) { | |
1230 | rtsx_pcr_cells[i].platform_data = handle; | |
1231 | rtsx_pcr_cells[i].pdata_size = sizeof(*handle); | |
1232 | } | |
1233 | ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells, | |
1234 | ARRAY_SIZE(rtsx_pcr_cells), NULL, 0, NULL); | |
1235 | if (ret < 0) | |
1236 | goto disable_irq; | |
1237 | ||
1238 | schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); | |
1239 | ||
1240 | return 0; | |
1241 | ||
1242 | disable_irq: | |
1243 | free_irq(pcr->irq, (void *)pcr); | |
9d66b568 JS |
1244 | disable_msi: |
1245 | if (pcr->msi_en) | |
1246 | pci_disable_msi(pcr->pci); | |
ada8a8a1 WW |
1247 | dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, |
1248 | pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); | |
1249 | unmap: | |
1250 | iounmap(pcr->remap_addr); | |
ada8a8a1 WW |
1251 | free_handle: |
1252 | kfree(handle); | |
1253 | free_pcr: | |
1254 | kfree(pcr); | |
1255 | release_pci: | |
1256 | pci_release_regions(pcidev); | |
1257 | disable: | |
1258 | pci_disable_device(pcidev); | |
1259 | ||
1260 | return ret; | |
1261 | } | |
1262 | ||
612b95cd | 1263 | static void rtsx_pci_remove(struct pci_dev *pcidev) |
ada8a8a1 WW |
1264 | { |
1265 | struct pcr_handle *handle = pci_get_drvdata(pcidev); | |
1266 | struct rtsx_pcr *pcr = handle->pcr; | |
1267 | ||
1268 | pcr->remove_pci = true; | |
1269 | ||
73beb63d TG |
1270 | /* Disable interrupts at the pcr level */ |
1271 | spin_lock_irq(&pcr->lock); | |
1272 | rtsx_pci_writel(pcr, RTSX_BIER, 0); | |
1273 | pcr->bier = 0; | |
1274 | spin_unlock_irq(&pcr->lock); | |
1275 | ||
1276 | cancel_delayed_work_sync(&pcr->carddet_work); | |
1277 | cancel_delayed_work_sync(&pcr->idle_work); | |
ada8a8a1 WW |
1278 | |
1279 | mfd_remove_devices(&pcidev->dev); | |
1280 | ||
1281 | dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN, | |
1282 | pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr); | |
1283 | free_irq(pcr->irq, (void *)pcr); | |
1284 | if (pcr->msi_en) | |
1285 | pci_disable_msi(pcr->pci); | |
1286 | iounmap(pcr->remap_addr); | |
1287 | ||
ada8a8a1 WW |
1288 | pci_release_regions(pcidev); |
1289 | pci_disable_device(pcidev); | |
1290 | ||
1291 | spin_lock(&rtsx_pci_lock); | |
1292 | idr_remove(&rtsx_pci_idr, pcr->id); | |
1293 | spin_unlock(&rtsx_pci_lock); | |
1294 | ||
1295 | kfree(pcr->slots); | |
1296 | kfree(pcr); | |
1297 | kfree(handle); | |
1298 | ||
1299 | dev_dbg(&(pcidev->dev), | |
1300 | ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n", | |
1301 | pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); | |
1302 | } | |
1303 | ||
1304 | #ifdef CONFIG_PM | |
1305 | ||
1306 | static int rtsx_pci_suspend(struct pci_dev *pcidev, pm_message_t state) | |
1307 | { | |
1308 | struct pcr_handle *handle; | |
1309 | struct rtsx_pcr *pcr; | |
ada8a8a1 WW |
1310 | |
1311 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1312 | ||
1313 | handle = pci_get_drvdata(pcidev); | |
1314 | pcr = handle->pcr; | |
1315 | ||
1316 | cancel_delayed_work(&pcr->carddet_work); | |
1317 | cancel_delayed_work(&pcr->idle_work); | |
1318 | ||
1319 | mutex_lock(&pcr->pcr_mutex); | |
1320 | ||
5947c167 | 1321 | rtsx_pci_power_off(pcr, HOST_ENTER_S3); |
ada8a8a1 WW |
1322 | |
1323 | pci_save_state(pcidev); | |
1324 | pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); | |
1325 | pci_disable_device(pcidev); | |
1326 | pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); | |
1327 | ||
1328 | mutex_unlock(&pcr->pcr_mutex); | |
5947c167 | 1329 | return 0; |
ada8a8a1 WW |
1330 | } |
1331 | ||
1332 | static int rtsx_pci_resume(struct pci_dev *pcidev) | |
1333 | { | |
1334 | struct pcr_handle *handle; | |
1335 | struct rtsx_pcr *pcr; | |
1336 | int ret = 0; | |
1337 | ||
1338 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1339 | ||
1340 | handle = pci_get_drvdata(pcidev); | |
1341 | pcr = handle->pcr; | |
1342 | ||
1343 | mutex_lock(&pcr->pcr_mutex); | |
1344 | ||
1345 | pci_set_power_state(pcidev, PCI_D0); | |
1346 | pci_restore_state(pcidev); | |
1347 | ret = pci_enable_device(pcidev); | |
1348 | if (ret) | |
1349 | goto out; | |
1350 | pci_set_master(pcidev); | |
1351 | ||
1352 | ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00); | |
1353 | if (ret) | |
1354 | goto out; | |
1355 | ||
1356 | ret = rtsx_pci_init_hw(pcr); | |
1357 | if (ret) | |
1358 | goto out; | |
1359 | ||
1360 | schedule_delayed_work(&pcr->idle_work, msecs_to_jiffies(200)); | |
1361 | ||
1362 | out: | |
1363 | mutex_unlock(&pcr->pcr_mutex); | |
1364 | return ret; | |
1365 | } | |
1366 | ||
5947c167 WW |
1367 | static void rtsx_pci_shutdown(struct pci_dev *pcidev) |
1368 | { | |
1369 | struct pcr_handle *handle; | |
1370 | struct rtsx_pcr *pcr; | |
1371 | ||
1372 | dev_dbg(&(pcidev->dev), "--> %s\n", __func__); | |
1373 | ||
1374 | handle = pci_get_drvdata(pcidev); | |
1375 | pcr = handle->pcr; | |
1376 | rtsx_pci_power_off(pcr, HOST_ENTER_S1); | |
1377 | ||
1378 | pci_disable_device(pcidev); | |
1379 | } | |
1380 | ||
ada8a8a1 WW |
1381 | #else /* CONFIG_PM */ |
1382 | ||
1383 | #define rtsx_pci_suspend NULL | |
1384 | #define rtsx_pci_resume NULL | |
5947c167 | 1385 | #define rtsx_pci_shutdown NULL |
ada8a8a1 WW |
1386 | |
1387 | #endif /* CONFIG_PM */ | |
1388 | ||
1389 | static struct pci_driver rtsx_pci_driver = { | |
1390 | .name = DRV_NAME_RTSX_PCI, | |
1391 | .id_table = rtsx_pci_ids, | |
1392 | .probe = rtsx_pci_probe, | |
612b95cd | 1393 | .remove = rtsx_pci_remove, |
ada8a8a1 WW |
1394 | .suspend = rtsx_pci_suspend, |
1395 | .resume = rtsx_pci_resume, | |
5947c167 | 1396 | .shutdown = rtsx_pci_shutdown, |
ada8a8a1 WW |
1397 | }; |
1398 | module_pci_driver(rtsx_pci_driver); | |
1399 | ||
1400 | MODULE_LICENSE("GPL"); | |
1401 | MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); | |
1402 | MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver"); |