[linux-2.6-block.git] / drivers / mfd / rts5249.c

/* Driver for Realtek PCI-Express card reader
 *
 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Author:
 *   Wei WANG <wei_wang@realsil.com.cn>
 *   No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mfd/rtsx_pci.h>

#include "rtsx_pcr.h"

static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
{
	u8 val;

	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
	return val & 0x0F;
}

static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
{
	u8 driving_3v3[4][3] = {
		{0x11, 0x11, 0x11},
		{0x55, 0x55, 0x5C},
		{0x99, 0x99, 0x92},
		{0x99, 0x99, 0x92},
	};
	u8 driving_1v8[4][3] = {
		{0x3C, 0x3C, 0x3C},
		{0xB3, 0xB3, 0xB3},
		{0xFE, 0xFE, 0xFE},
		{0xC4, 0xC4, 0xC4},
	};
	u8 (*driving)[3], drive_sel;

	if (voltage == OUTPUT_3V3) {
		driving = driving_3v3;
		drive_sel = pcr->sd30_drive_sel_3v3;
	} else {
		driving = driving_1v8;
		drive_sel = pcr->sd30_drive_sel_1v8;
	}

	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
			0xFF, driving[drive_sel][0]);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
			0xFF, driving[drive_sel][1]);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
			0xFF, driving[drive_sel][2]);
}

static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
{
	u32 reg;

	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);

	if (!rtsx_vendor_setting_valid(reg))
		return;

	pcr->aspm_en = rtsx_reg_to_aspm(reg);
	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
	pcr->card_drive_sel &= 0x3F;
	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);

	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
	if (rtsx_reg_check_reverse_socket(reg))
		pcr->flags |= PCR_REVERSE_SOCKET;
}

static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
{
	rtsx_pci_init_cmd(pcr);

	/* Configure GPIO as output */
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
	/* Switch LDO3318 source from DV33 to card_3v3 */
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
	/* LED shine disabled, set initial shine cycle period */
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
	/* Configure driving */
	rts5249_fill_driving(pcr, OUTPUT_3V3);
	if (pcr->flags & PCR_REVERSE_SOCKET)
		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
				AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
	else
		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
				AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);

	return rtsx_pci_send_cmd(pcr, 100);
}

static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
{
	int err;

	err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
	if (err < 0)
		return err;

	msleep(1);

	return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
}

static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
{
	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
}

static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
{
	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
}

static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
{
	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
}

static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
{
	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
}

static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
{
	int err;

	rtsx_pci_init_cmd(pcr);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
			SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
			LDO3318_PWR_MASK, 0x02);
	err = rtsx_pci_send_cmd(pcr, 100);
	if (err < 0)
		return err;

	msleep(5);

	rtsx_pci_init_cmd(pcr);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
			SD_POWER_MASK, SD_VCC_POWER_ON);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
			LDO3318_PWR_MASK, 0x06);
	err = rtsx_pci_send_cmd(pcr, 100);
	if (err < 0)
		return err;

	return 0;
}

static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
{
	rtsx_pci_init_cmd(pcr);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
			SD_POWER_MASK, SD_POWER_OFF);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
			LDO3318_PWR_MASK, 0x00);
	return rtsx_pci_send_cmd(pcr, 100);
}

static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
{
	int err;

	if (voltage == OUTPUT_3V3) {
		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
		if (err < 0)
			return err;
	} else if (voltage == OUTPUT_1V8) {
		err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
		if (err < 0)
			return err;
		err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
		if (err < 0)
			return err;
	} else {
		return -EINVAL;
	}

	/* set pad drive */
	rtsx_pci_init_cmd(pcr);
	rts5249_fill_driving(pcr, voltage);
	return rtsx_pci_send_cmd(pcr, 100);
}

static const struct pcr_ops rts5249_pcr_ops = {
	.fetch_vendor_settings = rts5249_fetch_vendor_settings,
	.extra_init_hw = rts5249_extra_init_hw,
	.optimize_phy = rts5249_optimize_phy,
	.turn_on_led = rts5249_turn_on_led,
	.turn_off_led = rts5249_turn_off_led,
	.enable_auto_blink = rts5249_enable_auto_blink,
	.disable_auto_blink = rts5249_disable_auto_blink,
	.card_power_on = rts5249_card_power_on,
	.card_power_off = rts5249_card_power_off,
	.switch_output_voltage = rts5249_switch_output_voltage,
};

/* SD Pull Control Enable:
 *     SD_DAT[3:0] ==> pull up
 *     SD_CD       ==> pull up
 *     SD_WP       ==> pull up
 *     SD_CMD      ==> pull up
 *     SD_CLK      ==> pull down
 */
static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
	RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
	0,
};

/* SD Pull Control Disable:
 *     SD_DAT[3:0] ==> pull down
 *     SD_CD       ==> pull up
 *     SD_WP       ==> pull down
 *     SD_CMD      ==> pull down
 *     SD_CLK      ==> pull down
 */
static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
	0,
};

/* MS Pull Control Enable:
 *     MS CD       ==> pull up
 *     others      ==> pull down
 */
static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
	0,
};

/* MS Pull Control Disable:
 *     MS CD       ==> pull up
 *     others      ==> pull down
 */
static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
	0,
};

void rts5249_init_params(struct rtsx_pcr *pcr)
{
	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
	pcr->num_slots = 2;
	pcr->ops = &rts5249_pcr_ops;

	pcr->flags = 0;
	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
	pcr->aspm_en = ASPM_L1_EN;

	pcr->ic_version = rts5249_get_ic_version(pcr);
	pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
	pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
}
Commit	Line	Data
4c4b8c10 WW	1	/* Driver for Realtek PCI-Express card reader
	2	*
	3	* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2, or (at your option) any
	8	* later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	13	* General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, see <http://www.gnu.org/licenses/>.
	17	*
	18	* Author:
	19	* Wei WANG <wei_wang@realsil.com.cn>
	20	* No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/delay.h>
	25	#include <linux/mfd/rtsx_pci.h>
	26
	27	#include "rtsx_pcr.h"
	28
	29	static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
	30	{
	31	u8 val;
	32
	33	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
	34	return val & 0x0F;
	35	}
	36
773ccdfd WW	37	static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
	38	{
	39	u8 driving_3v3[4][3] = {
	40	{0x11, 0x11, 0x11},
	41	{0x55, 0x55, 0x5C},
	42	{0x99, 0x99, 0x92},
	43	{0x99, 0x99, 0x92},
	44	};
	45	u8 driving_1v8[4][3] = {
	46	{0x3C, 0x3C, 0x3C},
	47	{0xB3, 0xB3, 0xB3},
	48	{0xFE, 0xFE, 0xFE},
	49	{0xC4, 0xC4, 0xC4},
	50	};
	51	u8 (*driving)[3], drive_sel;
	52
	53	if (voltage == OUTPUT_3V3) {
	54	driving = driving_3v3;
	55	drive_sel = pcr->sd30_drive_sel_3v3;
	56	} else {
	57	driving = driving_1v8;
	58	drive_sel = pcr->sd30_drive_sel_1v8;
	59	}
	60
	61	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
	62	0xFF, driving[drive_sel][0]);
	63	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
	64	0xFF, driving[drive_sel][1]);
	65	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
	66	0xFF, driving[drive_sel][2]);
	67	}
	68
	69	static void rts5249_fetch_vendor_settings(struct rtsx_pcr *pcr)
	70	{
	71	u32 reg;
	72
	73	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
	74	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
	75
	76	if (!rtsx_vendor_setting_valid(reg))
	77	return;
	78
	79	pcr->aspm_en = rtsx_reg_to_aspm(reg);
	80	pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
	81	pcr->card_drive_sel &= 0x3F;
	82	pcr->card_drive_sel \|= rtsx_reg_to_card_drive_sel(reg);
	83
	84	rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
	85	dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
	86	pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
	87	if (rtsx_reg_check_reverse_socket(reg))
	88	pcr->flags \|= PCR_REVERSE_SOCKET;
	89	}
	90
4c4b8c10 WW	91	static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
	92	{
	93	rtsx_pci_init_cmd(pcr);
	94
	95	/* Configure GPIO as output */
	96	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
	97	/* Switch LDO3318 source from DV33 to card_3v3 */
	98	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
	99	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
	100	/* LED shine disabled, set initial shine cycle period */
	101	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
773ccdfd WW	102	/* Configure driving */
	103	rts5249_fill_driving(pcr, OUTPUT_3V3);
	104	if (pcr->flags & PCR_REVERSE_SOCKET)
	105	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
	106	AUTOLOAD_CFG_BASE + 3, 0xB0, 0xB0);
	107	else
	108	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
	109	AUTOLOAD_CFG_BASE + 3, 0xB0, 0x80);
4c4b8c10 WW	110
	111	return rtsx_pci_send_cmd(pcr, 100);
	112	}
	113
	114	static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
	115	{
	116	int err;
	117
	118	err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
	119	if (err < 0)
	120	return err;
	121
	122	msleep(1);
	123
	124	return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
	125	}
	126
	127	static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
	128	{
	129	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
	130	}
	131
	132	static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
	133	{
	134	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
	135	}
	136
	137	static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
	138	{
	139	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
	140	}
	141
	142	static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
	143	{
	144	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
	145	}
	146
	147	static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
	148	{
	149	int err;
	150
	151	rtsx_pci_init_cmd(pcr);
	152	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
	153	SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
	154	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
	155	LDO3318_PWR_MASK, 0x02);
	156	err = rtsx_pci_send_cmd(pcr, 100);
	157	if (err < 0)
	158	return err;
	159
	160	msleep(5);
	161
	162	rtsx_pci_init_cmd(pcr);
	163	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
	164	SD_POWER_MASK, SD_VCC_POWER_ON);
	165	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
	166	LDO3318_PWR_MASK, 0x06);
	167	err = rtsx_pci_send_cmd(pcr, 100);
	168	if (err < 0)
	169	return err;
	170
	171	return 0;
	172	}
	173
174	static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
175	{
176	rtsx_pci_init_cmd(pcr);
177	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
178	SD_POWER_MASK, SD_POWER_OFF);
179	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
180	LDO3318_PWR_MASK, 0x00);
181	return rtsx_pci_send_cmd(pcr, 100);
182	}
183
184	static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
185	{
186	int err;
4c4b8c10 WW	187
	188	if (voltage == OUTPUT_3V3) {
	189	err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 \| 0x24);
	190	if (err < 0)
	191	return err;
4c4b8c10 WW	192	} else if (voltage == OUTPUT_1V8) {
	193	err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
	194	if (err < 0)
	195	return err;
	196	err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 \| 0x24);
	197	if (err < 0)
	198	return err;
4c4b8c10 WW	199	} else {
	200	return -EINVAL;
	201	}
	202
	203	/* set pad drive */
	204	rtsx_pci_init_cmd(pcr);
773ccdfd	205	rts5249_fill_driving(pcr, voltage);
4c4b8c10 WW	206	return rtsx_pci_send_cmd(pcr, 100);
	207	}
	208
	209	static const struct pcr_ops rts5249_pcr_ops = {
773ccdfd	210	.fetch_vendor_settings = rts5249_fetch_vendor_settings,
4c4b8c10 WW	211	.extra_init_hw = rts5249_extra_init_hw,
	212	.optimize_phy = rts5249_optimize_phy,
	213	.turn_on_led = rts5249_turn_on_led,
	214	.turn_off_led = rts5249_turn_off_led,
	215	.enable_auto_blink = rts5249_enable_auto_blink,
	216	.disable_auto_blink = rts5249_disable_auto_blink,
	217	.card_power_on = rts5249_card_power_on,
	218	.card_power_off = rts5249_card_power_off,
	219	.switch_output_voltage = rts5249_switch_output_voltage,
	220	};
	221
	222	/* SD Pull Control Enable:
	223	* SD_DAT[3:0] ==> pull up
	224	* SD_CD ==> pull up
	225	* SD_WP ==> pull up
	226	* SD_CMD ==> pull up
	227	* SD_CLK ==> pull down
	228	*/
	229	static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
	230	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
	231	RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
	232	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
	233	RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
	234	0,
	235	};
	236
	237	/* SD Pull Control Disable:
	238	* SD_DAT[3:0] ==> pull down
	239	* SD_CD ==> pull up
	240	* SD_WP ==> pull down
	241	* SD_CMD ==> pull down
	242	* SD_CLK ==> pull down
	243	*/
	244	static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
	245	RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
	246	RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
	247	RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
	248	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
	249	0,
	250	};
	251
	252	/* MS Pull Control Enable:
	253	* MS CD ==> pull up
	254	* others ==> pull down
	255	*/
	256	static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
	257	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
	258	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
	259	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
	260	0,
	261	};
	262
	263	/* MS Pull Control Disable:
	264	* MS CD ==> pull up
	265	* others ==> pull down
	266	*/
	267	static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
	268	RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
	269	RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
	270	RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
	271	0,
	272	};
	273
	274	void rts5249_init_params(struct rtsx_pcr *pcr)
275	{
276	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 \| EXTRA_CAPS_SD_SDR104;
277	pcr->num_slots = 2;
278	pcr->ops = &rts5249_pcr_ops;
279
773ccdfd WW	280	pcr->flags = 0;
	281	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
	282	pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_C;
	283	pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
	284	pcr->aspm_en = ASPM_L1_EN;
	285
4c4b8c10 WW	286	pcr->ic_version = rts5249_get_ic_version(pcr);
	287	pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
	288	pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
	289	pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
	290	pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
	291	}