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e1237932 RT |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
09fd8678 | 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
e1237932 RT |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG <wei_wang@realsil.com.cn> | |
e1237932 | 20 | * Roger Tseng <rogerable@realtek.com> |
e1237932 RT |
21 | */ |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/mfd/rtsx_pci.h> | |
26 | ||
27 | #include "rtsx_pcr.h" | |
28 | ||
773ccdfd WW |
29 | static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage) |
30 | { | |
31 | u8 driving_3v3[4][3] = { | |
32 | {0x13, 0x13, 0x13}, | |
33 | {0x96, 0x96, 0x96}, | |
34 | {0x7F, 0x7F, 0x7F}, | |
35 | {0x96, 0x96, 0x96}, | |
36 | }; | |
37 | u8 driving_1v8[4][3] = { | |
38 | {0x99, 0x99, 0x99}, | |
39 | {0xAA, 0xAA, 0xAA}, | |
40 | {0xFE, 0xFE, 0xFE}, | |
41 | {0xB3, 0xB3, 0xB3}, | |
42 | }; | |
43 | u8 (*driving)[3], drive_sel; | |
44 | ||
45 | if (voltage == OUTPUT_3V3) { | |
46 | driving = driving_3v3; | |
47 | drive_sel = pcr->sd30_drive_sel_3v3; | |
48 | } else { | |
49 | driving = driving_1v8; | |
50 | drive_sel = pcr->sd30_drive_sel_1v8; | |
51 | } | |
52 | ||
53 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, | |
54 | 0xFF, driving[drive_sel][0]); | |
55 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, | |
56 | 0xFF, driving[drive_sel][1]); | |
57 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, | |
58 | 0xFF, driving[drive_sel][2]); | |
59 | } | |
60 | ||
61 | static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr) | |
62 | { | |
63 | u32 reg; | |
64 | ||
65 | rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); | |
66 | dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); | |
67 | ||
68 | if (!rtsx_vendor_setting_valid(reg)) | |
69 | return; | |
70 | ||
71 | pcr->aspm_en = rtsx_reg_to_aspm(reg); | |
72 | pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); | |
73 | pcr->card_drive_sel &= 0x3F; | |
74 | pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); | |
75 | ||
76 | rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); | |
77 | dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); | |
78 | pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); | |
79 | if (rtsx_reg_check_reverse_socket(reg)) | |
80 | pcr->flags |= PCR_REVERSE_SOCKET; | |
81 | } | |
82 | ||
eb891c65 | 83 | static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) |
5947c167 WW |
84 | { |
85 | /* Set relink_time to 0 */ | |
86 | rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0); | |
87 | rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0); | |
88 | rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0); | |
89 | ||
eb891c65 WW |
90 | if (pm_state == HOST_ENTER_S3) |
91 | rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10); | |
92 | ||
5947c167 WW |
93 | rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03); |
94 | } | |
95 | ||
e1237932 RT |
96 | static int rts5227_extra_init_hw(struct rtsx_pcr *pcr) |
97 | { | |
98 | u16 cap; | |
99 | ||
100 | rtsx_pci_init_cmd(pcr); | |
101 | ||
102 | /* Configure GPIO as output */ | |
103 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); | |
7140812c WW |
104 | /* Reset ASPM state to default value */ |
105 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); | |
e1237932 RT |
106 | /* Switch LDO3318 source from DV33 to card_3v3 */ |
107 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); | |
108 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); | |
109 | /* LED shine disabled, set initial shine cycle period */ | |
110 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); | |
111 | /* Configure LTR */ | |
112 | pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap); | |
d2ab1fa6 | 113 | if (cap & PCI_EXP_DEVCTL2_LTR_EN) |
e1237932 RT |
114 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3); |
115 | /* Configure OBFF */ | |
116 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03); | |
773ccdfd WW |
117 | /* Configure driving */ |
118 | rts5227_fill_driving(pcr, OUTPUT_3V3); | |
119 | /* Configure force_clock_req */ | |
120 | if (pcr->flags & PCR_REVERSE_SOCKET) | |
121 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
122 | AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8); | |
123 | else | |
124 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, | |
125 | AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88); | |
eb891c65 | 126 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00); |
e1237932 RT |
127 | |
128 | return rtsx_pci_send_cmd(pcr, 100); | |
129 | } | |
130 | ||
131 | static int rts5227_optimize_phy(struct rtsx_pcr *pcr) | |
132 | { | |
5cb5d961 MC |
133 | int err; |
134 | ||
135 | err = rtsx_gops_pm_reset(pcr); | |
136 | if (err < 0) | |
137 | return err; | |
138 | ||
e1237932 RT |
139 | /* Optimize RX sensitivity */ |
140 | return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42); | |
141 | } | |
142 | ||
143 | static int rts5227_turn_on_led(struct rtsx_pcr *pcr) | |
144 | { | |
145 | return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); | |
146 | } | |
147 | ||
148 | static int rts5227_turn_off_led(struct rtsx_pcr *pcr) | |
149 | { | |
150 | return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); | |
151 | } | |
152 | ||
153 | static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr) | |
154 | { | |
155 | return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); | |
156 | } | |
157 | ||
158 | static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr) | |
159 | { | |
160 | return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); | |
161 | } | |
162 | ||
163 | static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card) | |
164 | { | |
165 | int err; | |
166 | ||
167 | rtsx_pci_init_cmd(pcr); | |
168 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, | |
169 | SD_POWER_MASK, SD_PARTIAL_POWER_ON); | |
170 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, | |
171 | LDO3318_PWR_MASK, 0x02); | |
172 | err = rtsx_pci_send_cmd(pcr, 100); | |
173 | if (err < 0) | |
174 | return err; | |
175 | ||
176 | /* To avoid too large in-rush current */ | |
177 | udelay(150); | |
178 | ||
179 | rtsx_pci_init_cmd(pcr); | |
180 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, | |
181 | SD_POWER_MASK, SD_POWER_ON); | |
182 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, | |
183 | LDO3318_PWR_MASK, 0x06); | |
184 | err = rtsx_pci_send_cmd(pcr, 100); | |
185 | if (err < 0) | |
186 | return err; | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card) | |
192 | { | |
193 | rtsx_pci_init_cmd(pcr); | |
194 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, | |
195 | SD_POWER_MASK | PMOS_STRG_MASK, | |
196 | SD_POWER_OFF | PMOS_STRG_400mA); | |
197 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, | |
198 | LDO3318_PWR_MASK, 0X00); | |
199 | return rtsx_pci_send_cmd(pcr, 100); | |
200 | } | |
201 | ||
202 | static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) | |
203 | { | |
204 | int err; | |
e1237932 RT |
205 | |
206 | if (voltage == OUTPUT_3V3) { | |
207 | err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24); | |
208 | if (err < 0) | |
209 | return err; | |
e1237932 RT |
210 | } else if (voltage == OUTPUT_1V8) { |
211 | err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02); | |
212 | if (err < 0) | |
213 | return err; | |
214 | err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24); | |
215 | if (err < 0) | |
216 | return err; | |
e1237932 RT |
217 | } else { |
218 | return -EINVAL; | |
219 | } | |
220 | ||
221 | /* set pad drive */ | |
222 | rtsx_pci_init_cmd(pcr); | |
773ccdfd | 223 | rts5227_fill_driving(pcr, voltage); |
e1237932 RT |
224 | return rtsx_pci_send_cmd(pcr, 100); |
225 | } | |
226 | ||
227 | static const struct pcr_ops rts5227_pcr_ops = { | |
773ccdfd | 228 | .fetch_vendor_settings = rts5227_fetch_vendor_settings, |
e1237932 RT |
229 | .extra_init_hw = rts5227_extra_init_hw, |
230 | .optimize_phy = rts5227_optimize_phy, | |
231 | .turn_on_led = rts5227_turn_on_led, | |
232 | .turn_off_led = rts5227_turn_off_led, | |
233 | .enable_auto_blink = rts5227_enable_auto_blink, | |
234 | .disable_auto_blink = rts5227_disable_auto_blink, | |
235 | .card_power_on = rts5227_card_power_on, | |
236 | .card_power_off = rts5227_card_power_off, | |
237 | .switch_output_voltage = rts5227_switch_output_voltage, | |
238 | .cd_deglitch = NULL, | |
239 | .conv_clk_and_div_n = NULL, | |
5947c167 | 240 | .force_power_down = rts5227_force_power_down, |
e1237932 RT |
241 | }; |
242 | ||
243 | /* SD Pull Control Enable: | |
244 | * SD_DAT[3:0] ==> pull up | |
245 | * SD_CD ==> pull up | |
246 | * SD_WP ==> pull up | |
247 | * SD_CMD ==> pull up | |
248 | * SD_CLK ==> pull down | |
249 | */ | |
250 | static const u32 rts5227_sd_pull_ctl_enable_tbl[] = { | |
251 | RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), | |
252 | RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), | |
253 | 0, | |
254 | }; | |
255 | ||
256 | /* SD Pull Control Disable: | |
257 | * SD_DAT[3:0] ==> pull down | |
258 | * SD_CD ==> pull up | |
259 | * SD_WP ==> pull down | |
260 | * SD_CMD ==> pull down | |
261 | * SD_CLK ==> pull down | |
262 | */ | |
263 | static const u32 rts5227_sd_pull_ctl_disable_tbl[] = { | |
264 | RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), | |
265 | RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), | |
266 | 0, | |
267 | }; | |
268 | ||
269 | /* MS Pull Control Enable: | |
270 | * MS CD ==> pull up | |
271 | * others ==> pull down | |
272 | */ | |
273 | static const u32 rts5227_ms_pull_ctl_enable_tbl[] = { | |
274 | RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), | |
275 | RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), | |
276 | 0, | |
277 | }; | |
278 | ||
279 | /* MS Pull Control Disable: | |
280 | * MS CD ==> pull up | |
281 | * others ==> pull down | |
282 | */ | |
283 | static const u32 rts5227_ms_pull_ctl_disable_tbl[] = { | |
284 | RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), | |
285 | RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), | |
286 | 0, | |
287 | }; | |
288 | ||
289 | void rts5227_init_params(struct rtsx_pcr *pcr) | |
290 | { | |
291 | pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; | |
292 | pcr->num_slots = 2; | |
293 | pcr->ops = &rts5227_pcr_ops; | |
294 | ||
773ccdfd WW |
295 | pcr->flags = 0; |
296 | pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; | |
297 | pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; | |
298 | pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; | |
299 | pcr->aspm_en = ASPM_L1_EN; | |
84d72f9c WW |
300 | pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); |
301 | pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7); | |
773ccdfd | 302 | |
e1237932 RT |
303 | pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl; |
304 | pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl; | |
305 | pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl; | |
306 | pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl; | |
307 | } |