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21b7c58f MV |
1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | // | |
3 | // Copyright (C) 2019 ROHM Semiconductors | |
4 | // | |
5 | // ROHM BD70528 PMIC driver | |
6 | ||
7 | #include <linux/i2c.h> | |
8 | #include <linux/interrupt.h> | |
9 | #include <linux/ioport.h> | |
10 | #include <linux/irq.h> | |
11 | #include <linux/mfd/core.h> | |
12 | #include <linux/mfd/rohm-bd70528.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/of_device.h> | |
15 | #include <linux/regmap.h> | |
16 | #include <linux/types.h> | |
17 | ||
18 | #define BD70528_NUM_OF_GPIOS 4 | |
19 | ||
20 | static const struct resource rtc_irqs[] = { | |
21 | DEFINE_RES_IRQ_NAMED(BD70528_INT_RTC_ALARM, "bd70528-rtc-alm"), | |
22 | DEFINE_RES_IRQ_NAMED(BD70528_INT_ELPS_TIM, "bd70528-elapsed-timer"), | |
23 | }; | |
24 | ||
25 | static const struct resource charger_irqs[] = { | |
26 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_RES, "bd70528-bat-ov-res"), | |
27 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_DET, "bd70528-bat-ov-det"), | |
28 | DEFINE_RES_IRQ_NAMED(BD70528_INT_DBAT_DET, "bd70528-bat-dead"), | |
29 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_RES, "bd70528-bat-warmed"), | |
30 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_DET, "bd70528-bat-cold"), | |
31 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_RES, "bd70528-bat-cooled"), | |
32 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_DET, "bd70528-bat-hot"), | |
33 | DEFINE_RES_IRQ_NAMED(BD70528_INT_CHG_TSD, "bd70528-chg-tshd"), | |
34 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_RMV, "bd70528-bat-removed"), | |
35 | DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_DET, "bd70528-bat-detected"), | |
36 | DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_RES, "bd70528-dcin2-ov-res"), | |
37 | DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_DET, "bd70528-dcin2-ov-det"), | |
38 | DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_RMV, "bd70528-dcin2-removed"), | |
39 | DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_DET, "bd70528-dcin2-detected"), | |
40 | DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_RMV, "bd70528-dcin1-removed"), | |
41 | DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_DET, "bd70528-dcin1-detected"), | |
42 | }; | |
43 | ||
44 | static struct mfd_cell bd70528_mfd_cells[] = { | |
45 | { .name = "bd70528-pmic", }, | |
46 | { .name = "bd70528-gpio", }, | |
47 | /* | |
48 | * We use BD71837 driver to drive the clock block. Only differences to | |
49 | * BD70528 clock gate are the register address and mask. | |
50 | */ | |
1b1c26b2 | 51 | { .name = "bd70528-clk", }, |
21b7c58f MV |
52 | { .name = "bd70528-wdt", }, |
53 | { | |
54 | .name = "bd70528-power", | |
55 | .resources = charger_irqs, | |
56 | .num_resources = ARRAY_SIZE(charger_irqs), | |
57 | }, { | |
58 | .name = "bd70528-rtc", | |
59 | .resources = rtc_irqs, | |
60 | .num_resources = ARRAY_SIZE(rtc_irqs), | |
61 | }, | |
62 | }; | |
63 | ||
64 | static const struct regmap_range volatile_ranges[] = { | |
65 | { | |
66 | .range_min = BD70528_REG_INT_MAIN, | |
67 | .range_max = BD70528_REG_INT_OP_FAIL, | |
68 | }, { | |
69 | .range_min = BD70528_REG_RTC_COUNT_H, | |
70 | .range_max = BD70528_REG_RTC_ALM_REPEAT, | |
71 | }, { | |
72 | /* | |
73 | * WDT control reg is special. Magic values must be written to | |
74 | * it in order to change the control. Should not be cached. | |
75 | */ | |
76 | .range_min = BD70528_REG_WDT_CTRL, | |
77 | .range_max = BD70528_REG_WDT_CTRL, | |
78 | }, { | |
79 | /* | |
80 | * BD70528 also contains a few other registers which require | |
81 | * magic sequences to be written in order to update the value. | |
82 | * At least SHIPMODE, HWRESET, WARMRESET,and STANDBY | |
83 | */ | |
84 | .range_min = BD70528_REG_SHIPMODE, | |
85 | .range_max = BD70528_REG_STANDBY, | |
86 | }, | |
87 | }; | |
88 | ||
89 | static const struct regmap_access_table volatile_regs = { | |
90 | .yes_ranges = &volatile_ranges[0], | |
91 | .n_yes_ranges = ARRAY_SIZE(volatile_ranges), | |
92 | }; | |
93 | ||
94 | static struct regmap_config bd70528_regmap = { | |
95 | .reg_bits = 8, | |
96 | .val_bits = 8, | |
97 | .volatile_table = &volatile_regs, | |
98 | .max_register = BD70528_MAX_REGISTER, | |
99 | .cache_type = REGCACHE_RBTREE, | |
100 | }; | |
101 | ||
102 | /* | |
103 | * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can | |
104 | * access corect sub-IRQ registers based on bits that are set in main IRQ | |
105 | * register. | |
106 | */ | |
107 | ||
cfca8bb2 MV |
108 | static unsigned int bit0_offsets[] = {0}; /* Shutdown */ |
109 | static unsigned int bit1_offsets[] = {1}; /* Power failure */ | |
110 | static unsigned int bit2_offsets[] = {2}; /* VR FAULT */ | |
111 | static unsigned int bit3_offsets[] = {3}; /* PMU interrupts */ | |
112 | static unsigned int bit4_offsets[] = {4, 5}; /* Charger 1 and Charger 2 */ | |
113 | static unsigned int bit5_offsets[] = {6}; /* RTC */ | |
114 | static unsigned int bit6_offsets[] = {7}; /* GPIO */ | |
115 | static unsigned int bit7_offsets[] = {8}; /* Invalid operation */ | |
21b7c58f MV |
116 | |
117 | static struct regmap_irq_sub_irq_map bd70528_sub_irq_offsets[] = { | |
118 | REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), | |
119 | REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), | |
120 | REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), | |
121 | REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), | |
122 | REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), | |
123 | REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), | |
124 | REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), | |
125 | REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), | |
126 | }; | |
127 | ||
128 | static struct regmap_irq bd70528_irqs[] = { | |
129 | REGMAP_IRQ_REG(BD70528_INT_LONGPUSH, 0, BD70528_INT_LONGPUSH_MASK), | |
130 | REGMAP_IRQ_REG(BD70528_INT_WDT, 0, BD70528_INT_WDT_MASK), | |
131 | REGMAP_IRQ_REG(BD70528_INT_HWRESET, 0, BD70528_INT_HWRESET_MASK), | |
132 | REGMAP_IRQ_REG(BD70528_INT_RSTB_FAULT, 0, BD70528_INT_RSTB_FAULT_MASK), | |
133 | REGMAP_IRQ_REG(BD70528_INT_VBAT_UVLO, 0, BD70528_INT_VBAT_UVLO_MASK), | |
134 | REGMAP_IRQ_REG(BD70528_INT_TSD, 0, BD70528_INT_TSD_MASK), | |
135 | REGMAP_IRQ_REG(BD70528_INT_RSTIN, 0, BD70528_INT_RSTIN_MASK), | |
136 | REGMAP_IRQ_REG(BD70528_INT_BUCK1_FAULT, 1, | |
137 | BD70528_INT_BUCK1_FAULT_MASK), | |
138 | REGMAP_IRQ_REG(BD70528_INT_BUCK2_FAULT, 1, | |
139 | BD70528_INT_BUCK2_FAULT_MASK), | |
140 | REGMAP_IRQ_REG(BD70528_INT_BUCK3_FAULT, 1, | |
141 | BD70528_INT_BUCK3_FAULT_MASK), | |
142 | REGMAP_IRQ_REG(BD70528_INT_LDO1_FAULT, 1, BD70528_INT_LDO1_FAULT_MASK), | |
143 | REGMAP_IRQ_REG(BD70528_INT_LDO2_FAULT, 1, BD70528_INT_LDO2_FAULT_MASK), | |
144 | REGMAP_IRQ_REG(BD70528_INT_LDO3_FAULT, 1, BD70528_INT_LDO3_FAULT_MASK), | |
145 | REGMAP_IRQ_REG(BD70528_INT_LED1_FAULT, 1, BD70528_INT_LED1_FAULT_MASK), | |
146 | REGMAP_IRQ_REG(BD70528_INT_LED2_FAULT, 1, BD70528_INT_LED2_FAULT_MASK), | |
147 | REGMAP_IRQ_REG(BD70528_INT_BUCK1_OCP, 2, BD70528_INT_BUCK1_OCP_MASK), | |
148 | REGMAP_IRQ_REG(BD70528_INT_BUCK2_OCP, 2, BD70528_INT_BUCK2_OCP_MASK), | |
149 | REGMAP_IRQ_REG(BD70528_INT_BUCK3_OCP, 2, BD70528_INT_BUCK3_OCP_MASK), | |
150 | REGMAP_IRQ_REG(BD70528_INT_LED1_OCP, 2, BD70528_INT_LED1_OCP_MASK), | |
151 | REGMAP_IRQ_REG(BD70528_INT_LED2_OCP, 2, BD70528_INT_LED2_OCP_MASK), | |
152 | REGMAP_IRQ_REG(BD70528_INT_BUCK1_FULLON, 2, | |
153 | BD70528_INT_BUCK1_FULLON_MASK), | |
154 | REGMAP_IRQ_REG(BD70528_INT_BUCK2_FULLON, 2, | |
155 | BD70528_INT_BUCK2_FULLON_MASK), | |
156 | REGMAP_IRQ_REG(BD70528_INT_SHORTPUSH, 3, BD70528_INT_SHORTPUSH_MASK), | |
157 | REGMAP_IRQ_REG(BD70528_INT_AUTO_WAKEUP, 3, | |
158 | BD70528_INT_AUTO_WAKEUP_MASK), | |
159 | REGMAP_IRQ_REG(BD70528_INT_STATE_CHANGE, 3, | |
160 | BD70528_INT_STATE_CHANGE_MASK), | |
161 | REGMAP_IRQ_REG(BD70528_INT_BAT_OV_RES, 4, BD70528_INT_BAT_OV_RES_MASK), | |
162 | REGMAP_IRQ_REG(BD70528_INT_BAT_OV_DET, 4, BD70528_INT_BAT_OV_DET_MASK), | |
163 | REGMAP_IRQ_REG(BD70528_INT_DBAT_DET, 4, BD70528_INT_DBAT_DET_MASK), | |
164 | REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_RES, 4, | |
165 | BD70528_INT_BATTSD_COLD_RES_MASK), | |
166 | REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_DET, 4, | |
167 | BD70528_INT_BATTSD_COLD_DET_MASK), | |
168 | REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_RES, 4, | |
169 | BD70528_INT_BATTSD_HOT_RES_MASK), | |
170 | REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_DET, 4, | |
171 | BD70528_INT_BATTSD_HOT_DET_MASK), | |
172 | REGMAP_IRQ_REG(BD70528_INT_CHG_TSD, 4, BD70528_INT_CHG_TSD_MASK), | |
173 | REGMAP_IRQ_REG(BD70528_INT_BAT_RMV, 5, BD70528_INT_BAT_RMV_MASK), | |
174 | REGMAP_IRQ_REG(BD70528_INT_BAT_DET, 5, BD70528_INT_BAT_DET_MASK), | |
175 | REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_RES, 5, | |
176 | BD70528_INT_DCIN2_OV_RES_MASK), | |
177 | REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_DET, 5, | |
178 | BD70528_INT_DCIN2_OV_DET_MASK), | |
179 | REGMAP_IRQ_REG(BD70528_INT_DCIN2_RMV, 5, BD70528_INT_DCIN2_RMV_MASK), | |
180 | REGMAP_IRQ_REG(BD70528_INT_DCIN2_DET, 5, BD70528_INT_DCIN2_DET_MASK), | |
181 | REGMAP_IRQ_REG(BD70528_INT_DCIN1_RMV, 5, BD70528_INT_DCIN1_RMV_MASK), | |
182 | REGMAP_IRQ_REG(BD70528_INT_DCIN1_DET, 5, BD70528_INT_DCIN1_DET_MASK), | |
183 | REGMAP_IRQ_REG(BD70528_INT_RTC_ALARM, 6, BD70528_INT_RTC_ALARM_MASK), | |
184 | REGMAP_IRQ_REG(BD70528_INT_ELPS_TIM, 6, BD70528_INT_ELPS_TIM_MASK), | |
185 | REGMAP_IRQ_REG(BD70528_INT_GPIO0, 7, BD70528_INT_GPIO0_MASK), | |
186 | REGMAP_IRQ_REG(BD70528_INT_GPIO1, 7, BD70528_INT_GPIO1_MASK), | |
187 | REGMAP_IRQ_REG(BD70528_INT_GPIO2, 7, BD70528_INT_GPIO2_MASK), | |
188 | REGMAP_IRQ_REG(BD70528_INT_GPIO3, 7, BD70528_INT_GPIO3_MASK), | |
189 | REGMAP_IRQ_REG(BD70528_INT_BUCK1_DVS_OPFAIL, 8, | |
190 | BD70528_INT_BUCK1_DVS_OPFAIL_MASK), | |
191 | REGMAP_IRQ_REG(BD70528_INT_BUCK2_DVS_OPFAIL, 8, | |
192 | BD70528_INT_BUCK2_DVS_OPFAIL_MASK), | |
193 | REGMAP_IRQ_REG(BD70528_INT_BUCK3_DVS_OPFAIL, 8, | |
194 | BD70528_INT_BUCK3_DVS_OPFAIL_MASK), | |
195 | REGMAP_IRQ_REG(BD70528_INT_LED1_VOLT_OPFAIL, 8, | |
196 | BD70528_INT_LED1_VOLT_OPFAIL_MASK), | |
197 | REGMAP_IRQ_REG(BD70528_INT_LED2_VOLT_OPFAIL, 8, | |
198 | BD70528_INT_LED2_VOLT_OPFAIL_MASK), | |
199 | }; | |
200 | ||
201 | static struct regmap_irq_chip bd70528_irq_chip = { | |
202 | .name = "bd70528_irq", | |
203 | .main_status = BD70528_REG_INT_MAIN, | |
204 | .irqs = &bd70528_irqs[0], | |
205 | .num_irqs = ARRAY_SIZE(bd70528_irqs), | |
206 | .status_base = BD70528_REG_INT_SHDN, | |
207 | .mask_base = BD70528_REG_INT_SHDN_MASK, | |
208 | .ack_base = BD70528_REG_INT_SHDN, | |
209 | .type_base = BD70528_REG_GPIO1_IN, | |
210 | .init_ack_masked = true, | |
211 | .num_regs = 9, | |
212 | .num_main_regs = 1, | |
213 | .num_type_reg = 4, | |
214 | .sub_reg_offsets = &bd70528_sub_irq_offsets[0], | |
215 | .num_main_status_bits = 8, | |
216 | .irq_reg_stride = 1, | |
217 | }; | |
218 | ||
219 | static int bd70528_i2c_probe(struct i2c_client *i2c, | |
220 | const struct i2c_device_id *id) | |
221 | { | |
222 | struct bd70528_data *bd70528; | |
223 | struct regmap_irq_chip_data *irq_data; | |
224 | int ret, i; | |
225 | ||
226 | if (!i2c->irq) { | |
227 | dev_err(&i2c->dev, "No IRQ configured\n"); | |
228 | return -EINVAL; | |
229 | } | |
230 | ||
231 | bd70528 = devm_kzalloc(&i2c->dev, sizeof(*bd70528), GFP_KERNEL); | |
232 | if (!bd70528) | |
233 | return -ENOMEM; | |
234 | ||
235 | mutex_init(&bd70528->rtc_timer_lock); | |
236 | ||
237 | dev_set_drvdata(&i2c->dev, &bd70528->chip); | |
238 | ||
21b7c58f MV |
239 | bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap); |
240 | if (IS_ERR(bd70528->chip.regmap)) { | |
241 | dev_err(&i2c->dev, "Failed to initialize Regmap\n"); | |
242 | return PTR_ERR(bd70528->chip.regmap); | |
243 | } | |
244 | ||
245 | /* | |
246 | * Disallow type setting for all IRQs by default as most of them do not | |
247 | * support setting type. | |
248 | */ | |
249 | for (i = 0; i < ARRAY_SIZE(bd70528_irqs); i++) | |
250 | bd70528_irqs[i].type.types_supported = 0; | |
251 | ||
252 | /* Set IRQ typesetting information for GPIO pins 0 - 3 */ | |
253 | for (i = 0; i < BD70528_NUM_OF_GPIOS; i++) { | |
254 | struct regmap_irq_type *type; | |
255 | ||
256 | type = &bd70528_irqs[BD70528_INT_GPIO0 + i].type; | |
257 | type->type_reg_offset = 2 * i; | |
258 | type->type_rising_val = 0x20; | |
259 | type->type_falling_val = 0x10; | |
260 | type->type_level_high_val = 0x40; | |
261 | type->type_level_low_val = 0x50; | |
262 | type->types_supported = (IRQ_TYPE_EDGE_BOTH | | |
263 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW); | |
264 | } | |
265 | ||
266 | ret = devm_regmap_add_irq_chip(&i2c->dev, bd70528->chip.regmap, | |
267 | i2c->irq, IRQF_ONESHOT, 0, | |
268 | &bd70528_irq_chip, &irq_data); | |
269 | if (ret) { | |
270 | dev_err(&i2c->dev, "Failed to add IRQ chip\n"); | |
271 | return ret; | |
272 | } | |
273 | dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", | |
274 | bd70528_irq_chip.num_irqs); | |
275 | ||
276 | /* | |
277 | * BD70528 IRQ controller is not touching the main mask register. | |
278 | * So enable the GPIO block interrupts at main level. We can just leave | |
279 | * them enabled as the IRQ controller should disable IRQs from | |
280 | * sub-registers when IRQ is disabled or freed. | |
281 | */ | |
282 | ret = regmap_update_bits(bd70528->chip.regmap, | |
283 | BD70528_REG_INT_MAIN_MASK, | |
284 | BD70528_INT_GPIO_MASK, 0); | |
285 | ||
286 | ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, | |
287 | bd70528_mfd_cells, | |
288 | ARRAY_SIZE(bd70528_mfd_cells), NULL, 0, | |
289 | regmap_irq_get_domain(irq_data)); | |
290 | if (ret) | |
291 | dev_err(&i2c->dev, "Failed to create subdevices\n"); | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
296 | static const struct of_device_id bd70528_of_match[] = { | |
297 | { .compatible = "rohm,bd70528", }, | |
298 | { }, | |
299 | }; | |
300 | MODULE_DEVICE_TABLE(of, bd70528_of_match); | |
301 | ||
302 | static struct i2c_driver bd70528_drv = { | |
303 | .driver = { | |
304 | .name = "rohm-bd70528", | |
305 | .of_match_table = bd70528_of_match, | |
306 | }, | |
307 | .probe = &bd70528_i2c_probe, | |
308 | }; | |
309 | ||
310 | module_i2c_driver(bd70528_drv); | |
311 | ||
312 | MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); | |
313 | MODULE_DESCRIPTION("ROHM BD70528 Power Management IC driver"); | |
314 | MODULE_LICENSE("GPL"); |