[linux-2.6-block.git] / drivers / mfd / qcom-pm8xxx.c

/*
 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#define pr_fmt(fmt) "%s: " fmt, __func__

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/ssbi.h>
#include <linux/regmap.h>
#include <linux/of_platform.h>
#include <linux/mfd/core.h>

#define	SSBI_REG_ADDR_IRQ_BASE		0x1BB

#define	SSBI_REG_ADDR_IRQ_ROOT		(SSBI_REG_ADDR_IRQ_BASE + 0)
#define	SSBI_REG_ADDR_IRQ_M_STATUS1	(SSBI_REG_ADDR_IRQ_BASE + 1)
#define	SSBI_REG_ADDR_IRQ_M_STATUS2	(SSBI_REG_ADDR_IRQ_BASE + 2)
#define	SSBI_REG_ADDR_IRQ_M_STATUS3	(SSBI_REG_ADDR_IRQ_BASE + 3)
#define	SSBI_REG_ADDR_IRQ_M_STATUS4	(SSBI_REG_ADDR_IRQ_BASE + 4)
#define	SSBI_REG_ADDR_IRQ_BLK_SEL	(SSBI_REG_ADDR_IRQ_BASE + 5)
#define	SSBI_REG_ADDR_IRQ_IT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 6)
#define	SSBI_REG_ADDR_IRQ_CONFIG	(SSBI_REG_ADDR_IRQ_BASE + 7)
#define	SSBI_REG_ADDR_IRQ_RT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 8)

#define	PM8821_SSBI_REG_ADDR_IRQ_BASE	0x100
#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
#define	PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
#define	PM8821_SSBI_REG(m, b, offset) \
			((m == 0) ? \
			(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
			(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
#define	PM8821_SSBI_ADDR_IRQ_ROOT(m, b)		PM8821_SSBI_REG(m, b, 0x0)
#define	PM8821_SSBI_ADDR_IRQ_CLEAR(m, b)	PM8821_SSBI_REG(m, b, 0x01)
#define	PM8821_SSBI_ADDR_IRQ_MASK(m, b)		PM8821_SSBI_REG(m, b, 0x08)
#define	PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b)	PM8821_SSBI_REG(m, b, 0x0f)

#define	PM8821_BLOCKS_PER_MASTER	7

#define	PM_IRQF_LVL_SEL			0x01	/* level select */
#define	PM_IRQF_MASK_FE			0x02	/* mask falling edge */
#define	PM_IRQF_MASK_RE			0x04	/* mask rising edge */
#define	PM_IRQF_CLR			0x08	/* clear interrupt */
#define	PM_IRQF_BITS_MASK		0x70
#define	PM_IRQF_BITS_SHIFT		4
#define	PM_IRQF_WRITE			0x80

#define	PM_IRQF_MASK_ALL		(PM_IRQF_MASK_FE | \
					PM_IRQF_MASK_RE)

#define REG_HWREV		0x002  /* PMIC4 revision */
#define REG_HWREV_2		0x0E8  /* PMIC4 revision 2 */

#define PM8XXX_NR_IRQS		256
#define PM8821_NR_IRQS		112

struct pm_irq_data {
	int num_irqs;
	struct irq_chip *irq_chip;
	void (*irq_handler)(struct irq_desc *desc);
};

struct pm_irq_chip {
	struct regmap		*regmap;
	spinlock_t		pm_irq_lock;
	struct irq_domain	*irqdomain;
	unsigned int		num_blocks;
	unsigned int		num_masters;
	const struct pm_irq_data *pm_irq_data;
	/* MUST BE AT THE END OF THIS STRUCT */
	u8			config[0];
};

static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
				 unsigned int *ip)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
	if (rc)
		pr_err("Failed Reading Status rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int
pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
{
	int	rc;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
		goto bail;
	}

	cp |= PM_IRQF_WRITE;
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
	if (rc)
		pr_err("Failed Configuring IRQ rc=%d\n", rc);
bail:
	spin_unlock(&chip->pm_irq_lock);
	return rc;
}

static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
{
	int pmirq, irq, i, ret = 0;
	unsigned int bits;

	ret = pm8xxx_read_block_irq(chip, block, &bits);
	if (ret) {
		pr_err("Failed reading %d block ret=%d", block, ret);
		return ret;
	}
	if (!bits) {
		pr_err("block bit set in master but no irqs: %d", block);
		return 0;
	}

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & (1 << i)) {
			pmirq = block * 8 + i;
			irq = irq_find_mapping(chip->irqdomain, pmirq);
			generic_handle_irq(irq);
		}
	}
	return 0;
}

static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
{
	unsigned int blockbits;
	int block_number, i, ret = 0;

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
			  &blockbits);
	if (ret) {
		pr_err("Failed to read master %d ret=%d\n", master, ret);
		return ret;
	}
	if (!blockbits) {
		pr_err("master bit set in root but no blocks: %d", master);
		return 0;
	}

	for (i = 0; i < 8; i++)
		if (blockbits & (1 << i)) {
			block_number = master * 8 + i;	/* block # */
			ret |= pm8xxx_irq_block_handler(chip, block_number);
		}
	return ret;
}

static void pm8xxx_irq_handler(struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	unsigned int root;
	int	i, ret, masters = 0;

	chained_irq_enter(irq_chip, desc);

	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
	if (ret) {
		pr_err("Can't read root status ret=%d\n", ret);
		return;
	}

	/* on pm8xxx series masters start from bit 1 of the root */
	masters = root >> 1;

	/* Read allowed masters for blocks. */
	for (i = 0; i < chip->num_masters; i++)
		if (masters & (1 << i))
			pm8xxx_irq_master_handler(chip, i);

	chained_irq_exit(irq_chip, desc);
}

static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
				     int master, int block)
{
	int pmirq, irq, i, ret;
	unsigned int bits;

	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
	if (ret) {
		pr_err("Reading block %d failed ret=%d", block, ret);
		return;
	}

	/* Convert block offset to global block number */
	block += (master * PM8821_BLOCKS_PER_MASTER) - 1;

	/* Check IRQ bits */
	for (i = 0; i < 8; i++) {
		if (bits & BIT(i)) {
			pmirq = block * 8 + i;
			irq = irq_find_mapping(chip->irqdomain, pmirq);
			generic_handle_irq(irq);
		}
	}
}

static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
					     int master, u8 master_val)
{
	int block;

	for (block = 1; block < 8; block++)
		if (master_val & BIT(block))
			pm8821_irq_block_handler(chip, master, block);
}

static void pm8821_irq_handler(struct irq_desc *desc)
{
	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	unsigned int master;
	int ret;

	chained_irq_enter(irq_chip, desc);
	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
	if (ret) {
		pr_err("Failed to read master 0 ret=%d\n", ret);
		goto done;
	}

	/* bits 1 through 7 marks the first 7 blocks in master 0 */
	if (master & GENMASK(7, 1))
		pm8821_irq_master_handler(chip, 0, master);

	/* bit 0 marks if master 1 contains any bits */
	if (!(master & BIT(0)))
		goto done;

	ret = regmap_read(chip->regmap,
			  PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
	if (ret) {
		pr_err("Failed to read master 1 ret=%d\n", ret);
		goto done;
	}

	pm8821_irq_master_handler(chip, 1, master);

done:
	chained_irq_exit(irq_chip, desc);
}

static void pm8xxx_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
	pm8xxx_config_irq(chip, block, config);
}

static void pm8xxx_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8	block, config;

	block = pmirq / 8;

	config = chip->config[pmirq];
	pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit;
	u8 block, config;

	block = pmirq / 8;
	irq_bit  = pmirq % 8;

	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
							| PM_IRQF_MASK_ALL;
	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
		if (flow_type & IRQF_TRIGGER_RISING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		if (flow_type & IRQF_TRIGGER_FALLING)
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	} else {
		chip->config[pmirq] |= PM_IRQF_LVL_SEL;

		if (flow_type & IRQF_TRIGGER_HIGH)
			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
		else
			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	}

	config = chip->config[pmirq] | PM_IRQF_CLR;
	return pm8xxx_config_irq(chip, block, config);
}

static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
					enum irqchip_irq_state which,
					bool *state)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	unsigned int bits;
	int irq_bit;
	u8 block;
	int rc;

	if (which != IRQCHIP_STATE_LINE_LEVEL)
		return -EINVAL;

	block = pmirq / 8;
	irq_bit = pmirq % 8;

	spin_lock(&chip->pm_irq_lock);
	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	if (rc) {
		pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
		goto bail;
	}

	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	if (rc) {
		pr_err("Failed Reading Status rc=%d\n", rc);
		goto bail;
	}

	*state = !!(bits & BIT(irq_bit));
bail:
	spin_unlock(&chip->pm_irq_lock);

	return rc;
}

static struct irq_chip pm8xxx_irq_chip = {
	.name		= "pm8xxx",
	.irq_mask_ack	= pm8xxx_irq_mask_ack,
	.irq_unmask	= pm8xxx_irq_unmask,
	.irq_set_type	= pm8xxx_irq_set_type,
	.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};

static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
				  struct irq_domain *domain, unsigned int irq,
				  irq_hw_number_t hwirq, unsigned int type)
{
	irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
			    chip, handle_level_irq, NULL, NULL);
	irq_set_noprobe(irq);
}

static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				   unsigned int nr_irqs, void *data)
{
	struct pm_irq_chip *chip = domain->host_data;
	struct irq_fwspec *fwspec = data;
	irq_hw_number_t hwirq;
	unsigned int type;
	int ret, i;

	ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	for (i = 0; i < nr_irqs; i++)
		pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);

	return 0;
}

static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
	.alloc = pm8xxx_irq_domain_alloc,
	.free = irq_domain_free_irqs_common,
	.translate = irq_domain_translate_twocell,
};

static void pm8821_irq_mask_ack(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	u8 block, master;
	int irq_bit, rc;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
				BIT(irq_bit), BIT(irq_bit));
	if (rc) {
		pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
		return;
	}

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
				BIT(irq_bit), BIT(irq_bit));
	if (rc)
		pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
}

static void pm8821_irq_unmask(struct irq_data *d)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	unsigned int pmirq = irqd_to_hwirq(d);
	int irq_bit, rc;
	u8 block, master;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_update_bits(chip->regmap,
				PM8821_SSBI_ADDR_IRQ_MASK(master, block),
				BIT(irq_bit), ~BIT(irq_bit));
	if (rc)
		pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);

}

static int pm8821_irq_get_irqchip_state(struct irq_data *d,
					enum irqchip_irq_state which,
					bool *state)
{
	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	int rc, pmirq = irqd_to_hwirq(d);
	u8 block, irq_bit, master;
	unsigned int bits;

	block = pmirq / 8;
	master = block / PM8821_BLOCKS_PER_MASTER;
	irq_bit = pmirq % 8;
	block %= PM8821_BLOCKS_PER_MASTER;

	rc = regmap_read(chip->regmap,
		PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
	if (rc) {
		pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
		return rc;
	}

	*state = !!(bits & BIT(irq_bit));

	return rc;
}

static struct irq_chip pm8821_irq_chip = {
	.name		= "pm8821",
	.irq_mask_ack	= pm8821_irq_mask_ack,
	.irq_unmask	= pm8821_irq_unmask,
	.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};

static const struct regmap_config ssbi_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.max_register = 0x3ff,
	.fast_io = true,
	.reg_read = ssbi_reg_read,
	.reg_write = ssbi_reg_write
};

static const struct pm_irq_data pm8xxx_data = {
	.num_irqs = PM8XXX_NR_IRQS,
	.irq_chip = &pm8xxx_irq_chip,
	.irq_handler = pm8xxx_irq_handler,
};

static const struct pm_irq_data pm8821_data = {
	.num_irqs = PM8821_NR_IRQS,
	.irq_chip = &pm8821_irq_chip,
	.irq_handler = pm8821_irq_handler,
};

static const struct of_device_id pm8xxx_id_table[] = {
	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
	{ }
};
MODULE_DEVICE_TABLE(of, pm8xxx_id_table);

static int pm8xxx_probe(struct platform_device *pdev)
{
	const struct pm_irq_data *data;
	struct regmap *regmap;
	int irq, rc;
	unsigned int val;
	u32 rev;
	struct pm_irq_chip *chip;

	data = of_device_get_match_data(&pdev->dev);
	if (!data) {
		dev_err(&pdev->dev, "No matching driver data found\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
				  &ssbi_regmap_config);
	if (IS_ERR(regmap))
		return PTR_ERR(regmap);

	/* Read PMIC chip revision */
	rc = regmap_read(regmap, REG_HWREV, &val);
	if (rc) {
		pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
		return rc;
	}
	pr_info("PMIC revision 1: %02X\n", val);
	rev = val;

	/* Read PMIC chip revision 2 */
	rc = regmap_read(regmap, REG_HWREV_2, &val);
	if (rc) {
		pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
			REG_HWREV_2, rc);
		return rc;
	}
	pr_info("PMIC revision 2: %02X\n", val);
	rev |= val << BITS_PER_BYTE;

	chip = devm_kzalloc(&pdev->dev,
			    struct_size(chip, config, data->num_irqs),
			    GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	platform_set_drvdata(pdev, chip);
	chip->regmap = regmap;
	chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
	chip->pm_irq_data = data;
	spin_lock_init(&chip->pm_irq_lock);

	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
						data->num_irqs,
						&pm8xxx_irq_domain_ops,
						chip);
	if (!chip->irqdomain)
		return -ENODEV;

	irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
	irq_set_irq_wake(irq, 1);

	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
	if (rc) {
		irq_set_chained_handler_and_data(irq, NULL, NULL);
		irq_domain_remove(chip->irqdomain);
	}

	return rc;
}

static int pm8xxx_remove_child(struct device *dev, void *unused)
{
	platform_device_unregister(to_platform_device(dev));
	return 0;
}

static int pm8xxx_remove(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct pm_irq_chip *chip = platform_get_drvdata(pdev);

	device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
	irq_set_chained_handler_and_data(irq, NULL, NULL);
	irq_domain_remove(chip->irqdomain);

	return 0;
}

static struct platform_driver pm8xxx_driver = {
	.probe		= pm8xxx_probe,
	.remove		= pm8xxx_remove,
	.driver		= {
		.name	= "pm8xxx-core",
		.of_match_table = pm8xxx_id_table,
	},
};

static int __init pm8xxx_init(void)
{
	return platform_driver_register(&pm8xxx_driver);
}
subsys_initcall(pm8xxx_init);

static void __exit pm8xxx_exit(void)
{
	platform_driver_unregister(&pm8xxx_driver);
}
module_exit(pm8xxx_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("PMIC 8xxx core driver");
MODULE_VERSION("1.0");
MODULE_ALIAS("platform:pm8xxx-core");
Commit	Line	Data
cbdb53e1 AD	1	/*
	2	* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#define pr_fmt(fmt) "%s: " fmt, __func__
	15
	16	#include <linux/kernel.h>
bc866fc7	17	#include <linux/interrupt.h>
cced3548	18	#include <linux/irqchip/chained_irq.h>
bc866fc7	19	#include <linux/irq.h>
dc1a95cc	20	#include <linux/irqdomain.h>
ef310f4b	21	#include <linux/module.h>
cbdb53e1 AD	22	#include <linux/platform_device.h>
cbdb53e1 AD	23	#include <linux/slab.h>
c013f0a5	24	#include <linux/err.h>
ce44bf5b	25	#include <linux/ssbi.h>
e7b81fca	26	#include <linux/regmap.h>
dc1a95cc	27	#include <linux/of_platform.h>
cbdb53e1	28	#include <linux/mfd/core.h>
bc866fc7 SB	29
	30	#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
	31
	32	#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
	33	#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
	34	#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
	35	#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
	36	#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
	37	#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
	38	#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
	39	#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
	40	#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
	41
953f432b SK	42	#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
	43	#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
	44	#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
	45	#define PM8821_SSBI_REG(m, b, offset) \
	46	((m == 0) ? \
	47	(PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
	48	(PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
	49	#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
	50	#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
	51	#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
	52	#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
	53
	54	#define PM8821_BLOCKS_PER_MASTER 7
	55
bc866fc7 SB	56	#define PM_IRQF_LVL_SEL 0x01 /* level select */
	57	#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
	58	#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
	59	#define PM_IRQF_CLR 0x08 /* clear interrupt */
	60	#define PM_IRQF_BITS_MASK 0x70
	61	#define PM_IRQF_BITS_SHIFT 4
	62	#define PM_IRQF_WRITE 0x80
	63
	64	#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE \| \
	65	PM_IRQF_MASK_RE)
cbdb53e1 AD	66
	67	#define REG_HWREV 0x002 /* PMIC4 revision */
	68	#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
	69
40a3a0f2	70	#define PM8XXX_NR_IRQS 256
953f432b	71	#define PM8821_NR_IRQS 112
dc1a95cc	72
3324a7c1 BM	73	struct pm_irq_data {
	74	int num_irqs;
	75	struct irq_chip *irq_chip;
	76	void (irq_handler)(struct irq_desc desc);
	77	};
	78
bc866fc7	79	struct pm_irq_chip {
e7b81fca	80	struct regmap *regmap;
bc866fc7	81	spinlock_t pm_irq_lock;
dc1a95cc	82	struct irq_domain *irqdomain;
bc866fc7 SB	83	unsigned int num_blocks;
bc866fc7 SB	84	unsigned int num_masters;
3324a7c1 BM	85	const struct pm_irq_data *pm_irq_data;
3324a7c1 BM	86	/* MUST BE AT THE END OF THIS STRUCT */
bc866fc7 SB	87	u8 config[0];
	88	};
	89
e7b81fca SB	90	static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
e7b81fca SB	91	unsigned int *ip)
bc866fc7 SB	92	{
	93	int rc;
	94
	95	spin_lock(&chip->pm_irq_lock);
e7b81fca	96	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	97	if (rc) {
	98	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	99	goto bail;
	100	}
	101
e7b81fca	102	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
bc866fc7 SB	103	if (rc)
	104	pr_err("Failed Reading Status rc=%d\n", rc);
	105	bail:
	106	spin_unlock(&chip->pm_irq_lock);
	107	return rc;
	108	}
	109
e7b81fca SB	110	static int
e7b81fca SB	111	pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
bc866fc7 SB	112	{
	113	int rc;
	114
	115	spin_lock(&chip->pm_irq_lock);
e7b81fca	116	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
bc866fc7 SB	117	if (rc) {
	118	pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
	119	goto bail;
	120	}
	121
	122	cp \|= PM_IRQF_WRITE;
e7b81fca	123	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
bc866fc7 SB	124	if (rc)
	125	pr_err("Failed Configuring IRQ rc=%d\n", rc);
	126	bail:
	127	spin_unlock(&chip->pm_irq_lock);
	128	return rc;
	129	}
	130
	131	static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
	132	{
	133	int pmirq, irq, i, ret = 0;
e7b81fca	134	unsigned int bits;
bc866fc7 SB	135
	136	ret = pm8xxx_read_block_irq(chip, block, &bits);
	137	if (ret) {
	138	pr_err("Failed reading %d block ret=%d", block, ret);
	139	return ret;
	140	}
	141	if (!bits) {
	142	pr_err("block bit set in master but no irqs: %d", block);
	143	return 0;
	144	}
	145
	146	/* Check IRQ bits */
	147	for (i = 0; i < 8; i++) {
	148	if (bits & (1 << i)) {
	149	pmirq = block * 8 + i;
dc1a95cc	150	irq = irq_find_mapping(chip->irqdomain, pmirq);
bc866fc7 SB	151	generic_handle_irq(irq);
	152	}
	153	}
	154	return 0;
	155	}
	156
	157	static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
	158	{
e7b81fca	159	unsigned int blockbits;
bc866fc7 SB	160	int block_number, i, ret = 0;
bc866fc7 SB	161
e7b81fca SB	162	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
e7b81fca SB	163	&blockbits);
bc866fc7 SB	164	if (ret) {
	165	pr_err("Failed to read master %d ret=%d\n", master, ret);
	166	return ret;
	167	}
	168	if (!blockbits) {
	169	pr_err("master bit set in root but no blocks: %d", master);
	170	return 0;
	171	}
	172
	173	for (i = 0; i < 8; i++)
	174	if (blockbits & (1 << i)) {
	175	block_number = master * 8 + i; /* block # */
	176	ret \|= pm8xxx_irq_block_handler(chip, block_number);
	177	}
	178	return ret;
	179	}
	180
bd0b9ac4	181	static void pm8xxx_irq_handler(struct irq_desc *desc)
bc866fc7 SB	182	{
	183	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	184	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
e7b81fca	185	unsigned int root;
bc866fc7 SB	186	int i, ret, masters = 0;
bc866fc7 SB	187
cced3548 SB	188	chained_irq_enter(irq_chip, desc);
cced3548 SB	189
e7b81fca	190	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
bc866fc7 SB	191	if (ret) {
	192	pr_err("Can't read root status ret=%d\n", ret);
	193	return;
	194	}
	195
	196	/* on pm8xxx series masters start from bit 1 of the root */
	197	masters = root >> 1;
	198
	199	/* Read allowed masters for blocks. */
	200	for (i = 0; i < chip->num_masters; i++)
	201	if (masters & (1 << i))
	202	pm8xxx_irq_master_handler(chip, i);
	203
cced3548	204	chained_irq_exit(irq_chip, desc);
bc866fc7 SB	205	}
bc866fc7 SB	206
953f432b SK	207	static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
	208	int master, int block)
	209	{
	210	int pmirq, irq, i, ret;
	211	unsigned int bits;
	212
	213	ret = regmap_read(chip->regmap,
	214	PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
	215	if (ret) {
	216	pr_err("Reading block %d failed ret=%d", block, ret);
	217	return;
	218	}
	219
	220	/* Convert block offset to global block number */
	221	block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
	222
	223	/* Check IRQ bits */
	224	for (i = 0; i < 8; i++) {
	225	if (bits & BIT(i)) {
	226	pmirq = block * 8 + i;
	227	irq = irq_find_mapping(chip->irqdomain, pmirq);
	228	generic_handle_irq(irq);
	229	}
	230	}
	231	}
	232
	233	static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
	234	int master, u8 master_val)
	235	{
	236	int block;
	237
	238	for (block = 1; block < 8; block++)
	239	if (master_val & BIT(block))
	240	pm8821_irq_block_handler(chip, master, block);
	241	}
	242
	243	static void pm8821_irq_handler(struct irq_desc *desc)
	244	{
	245	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
	246	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
	247	unsigned int master;
	248	int ret;
	249
	250	chained_irq_enter(irq_chip, desc);
	251	ret = regmap_read(chip->regmap,
	252	PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
	253	if (ret) {
	254	pr_err("Failed to read master 0 ret=%d\n", ret);
	255	goto done;
	256	}
	257
	258	/* bits 1 through 7 marks the first 7 blocks in master 0 */
	259	if (master & GENMASK(7, 1))
	260	pm8821_irq_master_handler(chip, 0, master);
	261
	262	/* bit 0 marks if master 1 contains any bits */
	263	if (!(master & BIT(0)))
	264	goto done;
	265
	266	ret = regmap_read(chip->regmap,
	267	PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
	268	if (ret) {
	269	pr_err("Failed to read master 1 ret=%d\n", ret);
	270	goto done;
271	}
272
273	pm8821_irq_master_handler(chip, 1, master);
274
275	done:
276	chained_irq_exit(irq_chip, desc);
277	}
278
bc866fc7 SB	279	static void pm8xxx_irq_mask_ack(struct irq_data *d)
	280	{
	281	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	282	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	283	u8 block, config;
	284
	285	block = pmirq / 8;
bc866fc7 SB	286
	287	config = chip->config[pmirq] \| PM_IRQF_MASK_ALL \| PM_IRQF_CLR;
	288	pm8xxx_config_irq(chip, block, config);
	289	}
	290
	291	static void pm8xxx_irq_unmask(struct irq_data *d)
	292	{
	293	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc	294	unsigned int pmirq = irqd_to_hwirq(d);
bc866fc7 SB	295	u8 block, config;
	296
	297	block = pmirq / 8;
bc866fc7 SB	298
	299	config = chip->config[pmirq];
	300	pm8xxx_config_irq(chip, block, config);
	301	}
	302
	303	static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
	304	{
	305	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
dc1a95cc SB	306	unsigned int pmirq = irqd_to_hwirq(d);
dc1a95cc SB	307	int irq_bit;
bc866fc7 SB	308	u8 block, config;
	309
	310	block = pmirq / 8;
bc866fc7 SB	311	irq_bit = pmirq % 8;
	312
	313	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
	314	\| PM_IRQF_MASK_ALL;
	315	if (flow_type & (IRQF_TRIGGER_RISING \| IRQF_TRIGGER_FALLING)) {
	316	if (flow_type & IRQF_TRIGGER_RISING)
	317	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	318	if (flow_type & IRQF_TRIGGER_FALLING)
	319	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	320	} else {
	321	chip->config[pmirq] \|= PM_IRQF_LVL_SEL;
	322
	323	if (flow_type & IRQF_TRIGGER_HIGH)
	324	chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
	325	else
	326	chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
	327	}
	328
	329	config = chip->config[pmirq] \| PM_IRQF_CLR;
	330	return pm8xxx_config_irq(chip, block, config);
	331	}
	332
f1837e4a BA	333	static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
	334	enum irqchip_irq_state which,
	335	bool *state)
	336	{
	337	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	338	unsigned int pmirq = irqd_to_hwirq(d);
	339	unsigned int bits;
	340	int irq_bit;
	341	u8 block;
	342	int rc;
	343
	344	if (which != IRQCHIP_STATE_LINE_LEVEL)
	345	return -EINVAL;
	346
	347	block = pmirq / 8;
	348	irq_bit = pmirq % 8;
	349
	350	spin_lock(&chip->pm_irq_lock);
	351	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
	352	if (rc) {
	353	pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
	354	goto bail;
	355	}
	356
	357	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
	358	if (rc) {
	359	pr_err("Failed Reading Status rc=%d\n", rc);
	360	goto bail;
	361	}
	362
	363	*state = !!(bits & BIT(irq_bit));
	364	bail:
	365	spin_unlock(&chip->pm_irq_lock);
	366
	367	return rc;
	368	}
	369
bc866fc7 SB	370	static struct irq_chip pm8xxx_irq_chip = {
	371	.name = "pm8xxx",
	372	.irq_mask_ack = pm8xxx_irq_mask_ack,
	373	.irq_unmask = pm8xxx_irq_unmask,
	374	.irq_set_type = pm8xxx_irq_set_type,
f1837e4a	375	.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
d2d24ad1	376	.flags = IRQCHIP_MASK_ON_SUSPEND \| IRQCHIP_SKIP_SET_WAKE,
bc866fc7 SB	377	};
bc866fc7 SB	378
3324a7c1 BM	379	static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
	380	struct irq_domain *domain, unsigned int irq,
	381	irq_hw_number_t hwirq, unsigned int type)
dc1a95cc	382	{
3324a7c1 BM	383	irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
3324a7c1 BM	384	chip, handle_level_irq, NULL, NULL);
dc1a95cc	385	irq_set_noprobe(irq);
3324a7c1 BM	386	}
	387
	388	static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
	389	unsigned int nr_irqs, void *data)
	390	{
	391	struct pm_irq_chip *chip = domain->host_data;
	392	struct irq_fwspec *fwspec = data;
	393	irq_hw_number_t hwirq;
	394	unsigned int type;
	395	int ret, i;
	396
	397	ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
	398	if (ret)
	399	return ret;
	400
	401	for (i = 0; i < nr_irqs; i++)
	402	pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
9bd09f34	403
bc866fc7 SB	404	return 0;
	405	}
	406
dc1a95cc	407	static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
3324a7c1 BM	408	.alloc = pm8xxx_irq_domain_alloc,
	409	.free = irq_domain_free_irqs_common,
	410	.translate = irq_domain_translate_twocell,
dc1a95cc SB	411	};
dc1a95cc SB	412
953f432b SK	413	static void pm8821_irq_mask_ack(struct irq_data *d)
	414	{
	415	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	416	unsigned int pmirq = irqd_to_hwirq(d);
	417	u8 block, master;
	418	int irq_bit, rc;
	419
	420	block = pmirq / 8;
	421	master = block / PM8821_BLOCKS_PER_MASTER;
	422	irq_bit = pmirq % 8;
	423	block %= PM8821_BLOCKS_PER_MASTER;
	424
	425	rc = regmap_update_bits(chip->regmap,
	426	PM8821_SSBI_ADDR_IRQ_MASK(master, block),
	427	BIT(irq_bit), BIT(irq_bit));
	428	if (rc) {
	429	pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
	430	return;
	431	}
	432
	433	rc = regmap_update_bits(chip->regmap,
	434	PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
	435	BIT(irq_bit), BIT(irq_bit));
	436	if (rc)
	437	pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
	438	}
	439
	440	static void pm8821_irq_unmask(struct irq_data *d)
	441	{
	442	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	443	unsigned int pmirq = irqd_to_hwirq(d);
	444	int irq_bit, rc;
	445	u8 block, master;
	446
	447	block = pmirq / 8;
	448	master = block / PM8821_BLOCKS_PER_MASTER;
	449	irq_bit = pmirq % 8;
	450	block %= PM8821_BLOCKS_PER_MASTER;
	451
	452	rc = regmap_update_bits(chip->regmap,
	453	PM8821_SSBI_ADDR_IRQ_MASK(master, block),
	454	BIT(irq_bit), ~BIT(irq_bit));
	455	if (rc)
	456	pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
	457
	458	}
	459
	460	static int pm8821_irq_get_irqchip_state(struct irq_data *d,
	461	enum irqchip_irq_state which,
	462	bool *state)
	463	{
	464	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
	465	int rc, pmirq = irqd_to_hwirq(d);
	466	u8 block, irq_bit, master;
	467	unsigned int bits;
	468
	469	block = pmirq / 8;
	470	master = block / PM8821_BLOCKS_PER_MASTER;
	471	irq_bit = pmirq % 8;
	472	block %= PM8821_BLOCKS_PER_MASTER;
	473
	474	rc = regmap_read(chip->regmap,
	475	PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
	476	if (rc) {
477	pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
478	return rc;
479	}
480
481	*state = !!(bits & BIT(irq_bit));
482
483	return rc;
484	}
485
486	static struct irq_chip pm8821_irq_chip = {
487	.name = "pm8821",
488	.irq_mask_ack = pm8821_irq_mask_ack,
489	.irq_unmask = pm8821_irq_unmask,
490	.irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
491	.flags = IRQCHIP_MASK_ON_SUSPEND \| IRQCHIP_SKIP_SET_WAKE,
492	};
493
e7b81fca SB	494	static const struct regmap_config ssbi_regmap_config = {
	495	.reg_bits = 16,
	496	.val_bits = 8,
	497	.max_register = 0x3ff,
	498	.fast_io = true,
	499	.reg_read = ssbi_reg_read,
	500	.reg_write = ssbi_reg_write
	501	};
	502
953f432b SK	503	static const struct pm_irq_data pm8xxx_data = {
953f432b SK	504	.num_irqs = PM8XXX_NR_IRQS,
3324a7c1	505	.irq_chip = &pm8xxx_irq_chip,
953f432b SK	506	.irq_handler = pm8xxx_irq_handler,
	507	};
	508
	509	static const struct pm_irq_data pm8821_data = {
	510	.num_irqs = PM8821_NR_IRQS,
3324a7c1	511	.irq_chip = &pm8821_irq_chip,
953f432b SK	512	.irq_handler = pm8821_irq_handler,
	513	};
	514
40a3a0f2	515	static const struct of_device_id pm8xxx_id_table[] = {
953f432b SK	516	{ .compatible = "qcom,pm8018", .data = &pm8xxx_data},
	517	{ .compatible = "qcom,pm8058", .data = &pm8xxx_data},
	518	{ .compatible = "qcom,pm8821", .data = &pm8821_data},
	519	{ .compatible = "qcom,pm8921", .data = &pm8xxx_data},
c5865a53 SB	520	{ }
c5865a53 SB	521	};
40a3a0f2	522	MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
c5865a53	523
40a3a0f2	524	static int pm8xxx_probe(struct platform_device *pdev)
cbdb53e1	525	{
953f432b	526	const struct pm_irq_data *data;
e7b81fca	527	struct regmap *regmap;
202f7680	528	int irq, rc;
e7b81fca	529	unsigned int val;
c013f0a5	530	u32 rev;
dc1a95cc	531	struct pm_irq_chip *chip;
953f432b SK	532
	533	data = of_device_get_match_data(&pdev->dev);
	534	if (!data) {
	535	dev_err(&pdev->dev, "No matching driver data found\n");
	536	return -EINVAL;
	537	}
cbdb53e1	538
dc1a95cc SB	539	irq = platform_get_irq(pdev, 0);
	540	if (irq < 0)
	541	return irq;
cbdb53e1	542
e7b81fca SB	543	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
	544	&ssbi_regmap_config);
	545	if (IS_ERR(regmap))
	546	return PTR_ERR(regmap);
	547
cbdb53e1	548	/* Read PMIC chip revision */
e7b81fca	549	rc = regmap_read(regmap, REG_HWREV, &val);
cbdb53e1 AD	550	if (rc) {
cbdb53e1 AD	551	pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
b2cdcfac	552	return rc;
cbdb53e1 AD	553	}
cbdb53e1 AD	554	pr_info("PMIC revision 1: %02X\n", val);
c013f0a5	555	rev = val;
cbdb53e1 AD	556
cbdb53e1 AD	557	/* Read PMIC chip revision 2 */
e7b81fca	558	rc = regmap_read(regmap, REG_HWREV_2, &val);
cbdb53e1 AD	559	if (rc) {
	560	pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
	561	REG_HWREV_2, rc);
b2cdcfac	562	return rc;
cbdb53e1 AD	563	}
cbdb53e1 AD	564	pr_info("PMIC revision 2: %02X\n", val);
c013f0a5	565	rev \|= val << BITS_PER_BYTE;
cbdb53e1	566
0ed2dd03 KC	567	chip = devm_kzalloc(&pdev->dev,
0ed2dd03 KC	568	struct_size(chip, config, data->num_irqs),
953f432b	569	GFP_KERNEL);
dc1a95cc SB	570	if (!chip)
	571	return -ENOMEM;
	572
3e87933a	573	platform_set_drvdata(pdev, chip);
e7b81fca	574	chip->regmap = regmap;
3324a7c1	575	chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
dc1a95cc	576	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
3324a7c1	577	chip->pm_irq_data = data;
dc1a95cc SB	578	spin_lock_init(&chip->pm_irq_lock);
dc1a95cc SB	579
953f432b SK	580	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
953f432b SK	581	data->num_irqs,
3324a7c1	582	&pm8xxx_irq_domain_ops,
dc1a95cc SB	583	chip);
	584	if (!chip->irqdomain)
	585	return -ENODEV;
	586
953f432b	587	irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
dc1a95cc SB	588	irq_set_irq_wake(irq, 1);
	589
	590	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
c013f0a5	591	if (rc) {
b79f0438	592	irq_set_chained_handler_and_data(irq, NULL, NULL);
dc1a95cc	593	irq_domain_remove(chip->irqdomain);
c013f0a5 AD	594	}
c013f0a5 AD	595
dc1a95cc SB	596	return rc;
dc1a95cc SB	597	}
c013f0a5	598
40a3a0f2	599	static int pm8xxx_remove_child(struct device dev, void unused)
dc1a95cc SB	600	{
dc1a95cc SB	601	platform_device_unregister(to_platform_device(dev));
cbdb53e1	602	return 0;
cbdb53e1 AD	603	}
cbdb53e1 AD	604
40a3a0f2	605	static int pm8xxx_remove(struct platform_device *pdev)
cbdb53e1	606	{
dc1a95cc	607	int irq = platform_get_irq(pdev, 0);
3e87933a	608	struct pm_irq_chip *chip = platform_get_drvdata(pdev);
dc1a95cc	609
40a3a0f2	610	device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
b79f0438	611	irq_set_chained_handler_and_data(irq, NULL, NULL);
dc1a95cc	612	irq_domain_remove(chip->irqdomain);
cbdb53e1 AD	613
	614	return 0;
	615	}
	616
40a3a0f2 LW	617	static struct platform_driver pm8xxx_driver = {
	618	.probe = pm8xxx_probe,
	619	.remove = pm8xxx_remove,
cbdb53e1	620	.driver = {
40a3a0f2 LW	621	.name = "pm8xxx-core",
40a3a0f2 LW	622	.of_match_table = pm8xxx_id_table,
cbdb53e1 AD	623	},
	624	};
	625
40a3a0f2	626	static int __init pm8xxx_init(void)
cbdb53e1	627	{
40a3a0f2	628	return platform_driver_register(&pm8xxx_driver);
cbdb53e1	629	}
40a3a0f2	630	subsys_initcall(pm8xxx_init);
cbdb53e1	631
40a3a0f2	632	static void __exit pm8xxx_exit(void)
cbdb53e1	633	{
40a3a0f2	634	platform_driver_unregister(&pm8xxx_driver);
cbdb53e1	635	}
40a3a0f2	636	module_exit(pm8xxx_exit);
cbdb53e1 AD	637
cbdb53e1 AD	638	MODULE_LICENSE("GPL v2");
40a3a0f2	639	MODULE_DESCRIPTION("PMIC 8xxx core driver");
cbdb53e1	640	MODULE_VERSION("1.0");
40a3a0f2	641	MODULE_ALIAS("platform:pm8xxx-core");