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f52046b1 BR |
1 | /* NXP PCF50633 Power Management Unit (PMU) driver |
2 | * | |
3 | * (C) 2006-2008 by Openmoko, Inc. | |
4 | * Author: Harald Welte <laforge@openmoko.org> | |
5 | * Balaji Rao <balajirrao@openmoko.org> | |
6 | * All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/device.h> | |
17 | #include <linux/sysfs.h> | |
f52046b1 BR |
18 | #include <linux/module.h> |
19 | #include <linux/types.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/workqueue.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/i2c.h> | |
24 | #include <linux/irq.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
f52046b1 BR |
26 | |
27 | #include <linux/mfd/pcf50633/core.h> | |
28 | ||
29 | /* Two MBCS registers used during cold start */ | |
30 | #define PCF50633_REG_MBCS1 0x4b | |
31 | #define PCF50633_REG_MBCS2 0x4c | |
32 | #define PCF50633_MBCS1_USBPRES 0x01 | |
33 | #define PCF50633_MBCS1_ADAPTPRES 0x01 | |
34 | ||
35 | static int __pcf50633_read(struct pcf50633 *pcf, u8 reg, int num, u8 *data) | |
36 | { | |
37 | int ret; | |
38 | ||
39 | ret = i2c_smbus_read_i2c_block_data(pcf->i2c_client, reg, | |
40 | num, data); | |
41 | if (ret < 0) | |
42 | dev_err(pcf->dev, "Error reading %d regs at %d\n", num, reg); | |
43 | ||
44 | return ret; | |
45 | } | |
46 | ||
47 | static int __pcf50633_write(struct pcf50633 *pcf, u8 reg, int num, u8 *data) | |
48 | { | |
49 | int ret; | |
50 | ||
51 | ret = i2c_smbus_write_i2c_block_data(pcf->i2c_client, reg, | |
52 | num, data); | |
53 | if (ret < 0) | |
54 | dev_err(pcf->dev, "Error writing %d regs at %d\n", num, reg); | |
55 | ||
56 | return ret; | |
57 | ||
58 | } | |
59 | ||
60 | /* Read a block of upto 32 regs */ | |
61 | int pcf50633_read_block(struct pcf50633 *pcf, u8 reg, | |
62 | int nr_regs, u8 *data) | |
63 | { | |
64 | int ret; | |
65 | ||
66 | mutex_lock(&pcf->lock); | |
67 | ret = __pcf50633_read(pcf, reg, nr_regs, data); | |
68 | mutex_unlock(&pcf->lock); | |
69 | ||
70 | return ret; | |
71 | } | |
72 | EXPORT_SYMBOL_GPL(pcf50633_read_block); | |
73 | ||
74 | /* Write a block of upto 32 regs */ | |
75 | int pcf50633_write_block(struct pcf50633 *pcf , u8 reg, | |
76 | int nr_regs, u8 *data) | |
77 | { | |
78 | int ret; | |
79 | ||
80 | mutex_lock(&pcf->lock); | |
81 | ret = __pcf50633_write(pcf, reg, nr_regs, data); | |
82 | mutex_unlock(&pcf->lock); | |
83 | ||
84 | return ret; | |
85 | } | |
86 | EXPORT_SYMBOL_GPL(pcf50633_write_block); | |
87 | ||
88 | u8 pcf50633_reg_read(struct pcf50633 *pcf, u8 reg) | |
89 | { | |
90 | u8 val; | |
91 | ||
92 | mutex_lock(&pcf->lock); | |
93 | __pcf50633_read(pcf, reg, 1, &val); | |
94 | mutex_unlock(&pcf->lock); | |
95 | ||
96 | return val; | |
97 | } | |
98 | EXPORT_SYMBOL_GPL(pcf50633_reg_read); | |
99 | ||
100 | int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val) | |
101 | { | |
102 | int ret; | |
103 | ||
104 | mutex_lock(&pcf->lock); | |
105 | ret = __pcf50633_write(pcf, reg, 1, &val); | |
106 | mutex_unlock(&pcf->lock); | |
107 | ||
108 | return ret; | |
109 | } | |
110 | EXPORT_SYMBOL_GPL(pcf50633_reg_write); | |
111 | ||
112 | int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val) | |
113 | { | |
114 | int ret; | |
115 | u8 tmp; | |
116 | ||
117 | val &= mask; | |
118 | ||
119 | mutex_lock(&pcf->lock); | |
120 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | |
121 | if (ret < 0) | |
122 | goto out; | |
123 | ||
124 | tmp &= ~mask; | |
125 | tmp |= val; | |
126 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | |
127 | ||
128 | out: | |
129 | mutex_unlock(&pcf->lock); | |
130 | ||
131 | return ret; | |
132 | } | |
133 | EXPORT_SYMBOL_GPL(pcf50633_reg_set_bit_mask); | |
134 | ||
135 | int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 val) | |
136 | { | |
137 | int ret; | |
138 | u8 tmp; | |
139 | ||
140 | mutex_lock(&pcf->lock); | |
141 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | |
142 | if (ret < 0) | |
143 | goto out; | |
144 | ||
145 | tmp &= ~val; | |
146 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | |
147 | ||
148 | out: | |
149 | mutex_unlock(&pcf->lock); | |
150 | ||
151 | return ret; | |
152 | } | |
153 | EXPORT_SYMBOL_GPL(pcf50633_reg_clear_bits); | |
154 | ||
155 | /* sysfs attributes */ | |
156 | static ssize_t show_dump_regs(struct device *dev, struct device_attribute *attr, | |
157 | char *buf) | |
158 | { | |
159 | struct pcf50633 *pcf = dev_get_drvdata(dev); | |
160 | u8 dump[16]; | |
161 | int n, n1, idx = 0; | |
162 | char *buf1 = buf; | |
163 | static u8 address_no_read[] = { /* must be ascending */ | |
164 | PCF50633_REG_INT1, | |
165 | PCF50633_REG_INT2, | |
166 | PCF50633_REG_INT3, | |
167 | PCF50633_REG_INT4, | |
168 | PCF50633_REG_INT5, | |
169 | 0 /* terminator */ | |
170 | }; | |
171 | ||
172 | for (n = 0; n < 256; n += sizeof(dump)) { | |
173 | for (n1 = 0; n1 < sizeof(dump); n1++) | |
174 | if (n == address_no_read[idx]) { | |
175 | idx++; | |
176 | dump[n1] = 0x00; | |
177 | } else | |
178 | dump[n1] = pcf50633_reg_read(pcf, n + n1); | |
179 | ||
180 | hex_dump_to_buffer(dump, sizeof(dump), 16, 1, buf1, 128, 0); | |
181 | buf1 += strlen(buf1); | |
182 | *buf1++ = '\n'; | |
183 | *buf1 = '\0'; | |
184 | } | |
185 | ||
186 | return buf1 - buf; | |
187 | } | |
188 | static DEVICE_ATTR(dump_regs, 0400, show_dump_regs, NULL); | |
189 | ||
190 | static ssize_t show_resume_reason(struct device *dev, | |
191 | struct device_attribute *attr, char *buf) | |
192 | { | |
193 | struct pcf50633 *pcf = dev_get_drvdata(dev); | |
194 | int n; | |
195 | ||
196 | n = sprintf(buf, "%02x%02x%02x%02x%02x\n", | |
197 | pcf->resume_reason[0], | |
198 | pcf->resume_reason[1], | |
199 | pcf->resume_reason[2], | |
200 | pcf->resume_reason[3], | |
201 | pcf->resume_reason[4]); | |
202 | ||
203 | return n; | |
204 | } | |
205 | static DEVICE_ATTR(resume_reason, 0400, show_resume_reason, NULL); | |
206 | ||
207 | static struct attribute *pcf_sysfs_entries[] = { | |
208 | &dev_attr_dump_regs.attr, | |
209 | &dev_attr_resume_reason.attr, | |
210 | NULL, | |
211 | }; | |
212 | ||
213 | static struct attribute_group pcf_attr_group = { | |
214 | .name = NULL, /* put in device directory */ | |
215 | .attrs = pcf_sysfs_entries, | |
216 | }; | |
217 | ||
218 | int pcf50633_register_irq(struct pcf50633 *pcf, int irq, | |
219 | void (*handler) (int, void *), void *data) | |
220 | { | |
165bce97 | 221 | if (irq < 0 || irq >= PCF50633_NUM_IRQ || !handler) |
f52046b1 BR |
222 | return -EINVAL; |
223 | ||
224 | if (WARN_ON(pcf->irq_handler[irq].handler)) | |
225 | return -EBUSY; | |
226 | ||
227 | mutex_lock(&pcf->lock); | |
228 | pcf->irq_handler[irq].handler = handler; | |
229 | pcf->irq_handler[irq].data = data; | |
230 | mutex_unlock(&pcf->lock); | |
231 | ||
232 | return 0; | |
233 | } | |
234 | EXPORT_SYMBOL_GPL(pcf50633_register_irq); | |
235 | ||
236 | int pcf50633_free_irq(struct pcf50633 *pcf, int irq) | |
237 | { | |
165bce97 | 238 | if (irq < 0 || irq >= PCF50633_NUM_IRQ) |
f52046b1 BR |
239 | return -EINVAL; |
240 | ||
241 | mutex_lock(&pcf->lock); | |
242 | pcf->irq_handler[irq].handler = NULL; | |
243 | mutex_unlock(&pcf->lock); | |
244 | ||
245 | return 0; | |
246 | } | |
247 | EXPORT_SYMBOL_GPL(pcf50633_free_irq); | |
248 | ||
249 | static int __pcf50633_irq_mask_set(struct pcf50633 *pcf, int irq, u8 mask) | |
250 | { | |
251 | u8 reg, bits, tmp; | |
252 | int ret = 0, idx; | |
253 | ||
254 | idx = irq >> 3; | |
255 | reg = PCF50633_REG_INT1M + idx; | |
256 | bits = 1 << (irq & 0x07); | |
257 | ||
258 | mutex_lock(&pcf->lock); | |
259 | ||
260 | if (mask) { | |
261 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | |
262 | if (ret < 0) | |
263 | goto out; | |
264 | ||
265 | tmp |= bits; | |
266 | ||
267 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | |
268 | if (ret < 0) | |
269 | goto out; | |
270 | ||
271 | pcf->mask_regs[idx] &= ~bits; | |
272 | pcf->mask_regs[idx] |= bits; | |
273 | } else { | |
274 | ret = __pcf50633_read(pcf, reg, 1, &tmp); | |
275 | if (ret < 0) | |
276 | goto out; | |
277 | ||
278 | tmp &= ~bits; | |
279 | ||
280 | ret = __pcf50633_write(pcf, reg, 1, &tmp); | |
281 | if (ret < 0) | |
282 | goto out; | |
283 | ||
284 | pcf->mask_regs[idx] &= ~bits; | |
285 | } | |
286 | out: | |
287 | mutex_unlock(&pcf->lock); | |
288 | ||
289 | return ret; | |
290 | } | |
291 | ||
292 | int pcf50633_irq_mask(struct pcf50633 *pcf, int irq) | |
293 | { | |
b18fdc4b | 294 | dev_dbg(pcf->dev, "Masking IRQ %d\n", irq); |
f52046b1 BR |
295 | |
296 | return __pcf50633_irq_mask_set(pcf, irq, 1); | |
297 | } | |
298 | EXPORT_SYMBOL_GPL(pcf50633_irq_mask); | |
299 | ||
300 | int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq) | |
301 | { | |
b18fdc4b | 302 | dev_dbg(pcf->dev, "Unmasking IRQ %d\n", irq); |
f52046b1 BR |
303 | |
304 | return __pcf50633_irq_mask_set(pcf, irq, 0); | |
305 | } | |
306 | EXPORT_SYMBOL_GPL(pcf50633_irq_unmask); | |
307 | ||
308 | int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq) | |
309 | { | |
310 | u8 reg, bits; | |
311 | ||
312 | reg = irq >> 3; | |
313 | bits = 1 << (irq & 0x07); | |
314 | ||
315 | return pcf->mask_regs[reg] & bits; | |
316 | } | |
317 | EXPORT_SYMBOL_GPL(pcf50633_irq_mask_get); | |
318 | ||
319 | static void pcf50633_irq_call_handler(struct pcf50633 *pcf, int irq) | |
320 | { | |
321 | if (pcf->irq_handler[irq].handler) | |
322 | pcf->irq_handler[irq].handler(irq, pcf->irq_handler[irq].data); | |
323 | } | |
324 | ||
325 | /* Maximum amount of time ONKEY is held before emergency action is taken */ | |
326 | #define PCF50633_ONKEY1S_TIMEOUT 8 | |
327 | ||
f7b2a77f | 328 | static irqreturn_t pcf50633_irq(int irq, void *data) |
f52046b1 | 329 | { |
f7b2a77f | 330 | struct pcf50633 *pcf = data; |
f52046b1 BR |
331 | int ret, i, j; |
332 | u8 pcf_int[5], chgstat; | |
333 | ||
f52046b1 BR |
334 | /* Read the 5 INT regs in one transaction */ |
335 | ret = pcf50633_read_block(pcf, PCF50633_REG_INT1, | |
336 | ARRAY_SIZE(pcf_int), pcf_int); | |
337 | if (ret != ARRAY_SIZE(pcf_int)) { | |
338 | dev_err(pcf->dev, "Error reading INT registers\n"); | |
339 | ||
340 | /* | |
341 | * If this doesn't ACK the interrupt to the chip, we'll be | |
342 | * called once again as we're level triggered. | |
343 | */ | |
344 | goto out; | |
345 | } | |
346 | ||
06b1cc9c PF |
347 | /* defeat 8s death from lowsys on A5 */ |
348 | pcf50633_reg_write(pcf, PCF50633_REG_OOCSHDWN, 0x04); | |
349 | ||
f52046b1 BR |
350 | /* We immediately read the usb and adapter status. We thus make sure |
351 | * only of USBINS/USBREM IRQ handlers are called */ | |
352 | if (pcf_int[0] & (PCF50633_INT1_USBINS | PCF50633_INT1_USBREM)) { | |
353 | chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | |
354 | if (chgstat & (0x3 << 4)) | |
0aeee5d4 | 355 | pcf_int[0] &= ~PCF50633_INT1_USBREM; |
f52046b1 | 356 | else |
0aeee5d4 | 357 | pcf_int[0] &= ~PCF50633_INT1_USBINS; |
f52046b1 BR |
358 | } |
359 | ||
360 | /* Make sure only one of ADPINS or ADPREM is set */ | |
361 | if (pcf_int[0] & (PCF50633_INT1_ADPINS | PCF50633_INT1_ADPREM)) { | |
362 | chgstat = pcf50633_reg_read(pcf, PCF50633_REG_MBCS2); | |
363 | if (chgstat & (0x3 << 4)) | |
0aeee5d4 | 364 | pcf_int[0] &= ~PCF50633_INT1_ADPREM; |
f52046b1 | 365 | else |
0aeee5d4 | 366 | pcf_int[0] &= ~PCF50633_INT1_ADPINS; |
f52046b1 BR |
367 | } |
368 | ||
369 | dev_dbg(pcf->dev, "INT1=0x%02x INT2=0x%02x INT3=0x%02x " | |
370 | "INT4=0x%02x INT5=0x%02x\n", pcf_int[0], | |
371 | pcf_int[1], pcf_int[2], pcf_int[3], pcf_int[4]); | |
372 | ||
373 | /* Some revisions of the chip don't have a 8s standby mode on | |
374 | * ONKEY1S press. We try to manually do it in such cases. */ | |
375 | if ((pcf_int[0] & PCF50633_INT1_SECOND) && pcf->onkey1s_held) { | |
376 | dev_info(pcf->dev, "ONKEY1S held for %d secs\n", | |
377 | pcf->onkey1s_held); | |
378 | if (pcf->onkey1s_held++ == PCF50633_ONKEY1S_TIMEOUT) | |
379 | if (pcf->pdata->force_shutdown) | |
380 | pcf->pdata->force_shutdown(pcf); | |
381 | } | |
382 | ||
383 | if (pcf_int[2] & PCF50633_INT3_ONKEY1S) { | |
384 | dev_info(pcf->dev, "ONKEY1S held\n"); | |
385 | pcf->onkey1s_held = 1 ; | |
386 | ||
387 | /* Unmask IRQ_SECOND */ | |
388 | pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT1M, | |
389 | PCF50633_INT1_SECOND); | |
390 | ||
391 | /* Unmask IRQ_ONKEYR */ | |
392 | pcf50633_reg_clear_bits(pcf, PCF50633_REG_INT2M, | |
393 | PCF50633_INT2_ONKEYR); | |
394 | } | |
395 | ||
396 | if ((pcf_int[1] & PCF50633_INT2_ONKEYR) && pcf->onkey1s_held) { | |
397 | pcf->onkey1s_held = 0; | |
398 | ||
399 | /* Mask SECOND and ONKEYR interrupts */ | |
400 | if (pcf->mask_regs[0] & PCF50633_INT1_SECOND) | |
401 | pcf50633_reg_set_bit_mask(pcf, | |
402 | PCF50633_REG_INT1M, | |
403 | PCF50633_INT1_SECOND, | |
404 | PCF50633_INT1_SECOND); | |
405 | ||
406 | if (pcf->mask_regs[1] & PCF50633_INT2_ONKEYR) | |
407 | pcf50633_reg_set_bit_mask(pcf, | |
408 | PCF50633_REG_INT2M, | |
409 | PCF50633_INT2_ONKEYR, | |
410 | PCF50633_INT2_ONKEYR); | |
411 | } | |
412 | ||
413 | /* Have we just resumed ? */ | |
414 | if (pcf->is_suspended) { | |
415 | pcf->is_suspended = 0; | |
416 | ||
417 | /* Set the resume reason filtering out non resumers */ | |
418 | for (i = 0; i < ARRAY_SIZE(pcf_int); i++) | |
419 | pcf->resume_reason[i] = pcf_int[i] & | |
420 | pcf->pdata->resumers[i]; | |
421 | ||
422 | /* Make sure we don't pass on any ONKEY events to | |
423 | * userspace now */ | |
424 | pcf_int[1] &= ~(PCF50633_INT2_ONKEYR | PCF50633_INT2_ONKEYF); | |
425 | } | |
426 | ||
427 | for (i = 0; i < ARRAY_SIZE(pcf_int); i++) { | |
428 | /* Unset masked interrupts */ | |
429 | pcf_int[i] &= ~pcf->mask_regs[i]; | |
430 | ||
431 | for (j = 0; j < 8 ; j++) | |
432 | if (pcf_int[i] & (1 << j)) | |
433 | pcf50633_irq_call_handler(pcf, (i * 8) + j); | |
434 | } | |
435 | ||
436 | out: | |
f7b2a77f | 437 | return IRQ_HANDLED |
f52046b1 BR |
438 | } |
439 | ||
440 | static void | |
441 | pcf50633_client_dev_register(struct pcf50633 *pcf, const char *name, | |
442 | struct platform_device **pdev) | |
443 | { | |
f52046b1 BR |
444 | int ret; |
445 | ||
446 | *pdev = platform_device_alloc(name, -1); | |
447 | if (!*pdev) { | |
448 | dev_err(pcf->dev, "Falied to allocate %s\n", name); | |
449 | return; | |
450 | } | |
451 | ||
f52046b1 BR |
452 | (*pdev)->dev.parent = pcf->dev; |
453 | ||
454 | ret = platform_device_add(*pdev); | |
455 | if (ret) { | |
456 | dev_err(pcf->dev, "Failed to register %s: %d\n", name, ret); | |
457 | platform_device_put(*pdev); | |
458 | *pdev = NULL; | |
459 | } | |
460 | } | |
461 | ||
462 | #ifdef CONFIG_PM | |
25993e4e | 463 | static int pcf50633_suspend(struct i2c_client *client, pm_message_t state) |
f52046b1 BR |
464 | { |
465 | struct pcf50633 *pcf; | |
466 | int ret = 0, i; | |
467 | u8 res[5]; | |
468 | ||
25993e4e | 469 | pcf = i2c_get_clientdata(client); |
f52046b1 BR |
470 | |
471 | /* Make sure our interrupt handlers are not called | |
472 | * henceforth */ | |
473 | disable_irq(pcf->irq); | |
474 | ||
f52046b1 BR |
475 | /* Save the masks */ |
476 | ret = pcf50633_read_block(pcf, PCF50633_REG_INT1M, | |
477 | ARRAY_SIZE(pcf->suspend_irq_masks), | |
478 | pcf->suspend_irq_masks); | |
479 | if (ret < 0) { | |
480 | dev_err(pcf->dev, "error saving irq masks\n"); | |
481 | goto out; | |
482 | } | |
483 | ||
484 | /* Write wakeup irq masks */ | |
485 | for (i = 0; i < ARRAY_SIZE(res); i++) | |
486 | res[i] = ~pcf->pdata->resumers[i]; | |
487 | ||
488 | ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | |
489 | ARRAY_SIZE(res), &res[0]); | |
490 | if (ret < 0) { | |
491 | dev_err(pcf->dev, "error writing wakeup irq masks\n"); | |
492 | goto out; | |
493 | } | |
494 | ||
495 | pcf->is_suspended = 1; | |
496 | ||
497 | out: | |
498 | return ret; | |
499 | } | |
500 | ||
25993e4e | 501 | static int pcf50633_resume(struct i2c_client *client) |
f52046b1 BR |
502 | { |
503 | struct pcf50633 *pcf; | |
504 | int ret; | |
505 | ||
25993e4e | 506 | pcf = i2c_get_clientdata(client); |
f52046b1 BR |
507 | |
508 | /* Write the saved mask registers */ | |
509 | ret = pcf50633_write_block(pcf, PCF50633_REG_INT1M, | |
510 | ARRAY_SIZE(pcf->suspend_irq_masks), | |
511 | pcf->suspend_irq_masks); | |
512 | if (ret < 0) | |
513 | dev_err(pcf->dev, "Error restoring saved suspend masks\n"); | |
514 | ||
f7b2a77f | 515 | enable_irq(pcf->irq); |
f52046b1 BR |
516 | |
517 | return 0; | |
518 | } | |
519 | #else | |
520 | #define pcf50633_suspend NULL | |
521 | #define pcf50633_resume NULL | |
522 | #endif | |
523 | ||
524 | static int __devinit pcf50633_probe(struct i2c_client *client, | |
525 | const struct i2c_device_id *ids) | |
526 | { | |
527 | struct pcf50633 *pcf; | |
528 | struct pcf50633_platform_data *pdata = client->dev.platform_data; | |
24213ae1 | 529 | int i, ret; |
f52046b1 BR |
530 | int version, variant; |
531 | ||
24213ae1 LPC |
532 | if (!client->irq) { |
533 | dev_err(&client->dev, "Missing IRQ\n"); | |
534 | return -ENOENT; | |
535 | } | |
536 | ||
f52046b1 BR |
537 | pcf = kzalloc(sizeof(*pcf), GFP_KERNEL); |
538 | if (!pcf) | |
539 | return -ENOMEM; | |
540 | ||
541 | pcf->pdata = pdata; | |
542 | ||
543 | mutex_init(&pcf->lock); | |
544 | ||
545 | i2c_set_clientdata(client, pcf); | |
546 | pcf->dev = &client->dev; | |
547 | pcf->i2c_client = client; | |
548 | pcf->irq = client->irq; | |
f52046b1 BR |
549 | |
550 | version = pcf50633_reg_read(pcf, 0); | |
551 | variant = pcf50633_reg_read(pcf, 1); | |
552 | if (version < 0 || variant < 0) { | |
553 | dev_err(pcf->dev, "Unable to probe pcf50633\n"); | |
554 | ret = -ENODEV; | |
f7b2a77f | 555 | goto err_free; |
f52046b1 BR |
556 | } |
557 | ||
558 | dev_info(pcf->dev, "Probed device version %d variant %d\n", | |
559 | version, variant); | |
560 | ||
561 | /* Enable all interrupts except RTC SECOND */ | |
562 | pcf->mask_regs[0] = 0x80; | |
563 | pcf50633_reg_write(pcf, PCF50633_REG_INT1M, pcf->mask_regs[0]); | |
564 | pcf50633_reg_write(pcf, PCF50633_REG_INT2M, 0x00); | |
565 | pcf50633_reg_write(pcf, PCF50633_REG_INT3M, 0x00); | |
566 | pcf50633_reg_write(pcf, PCF50633_REG_INT4M, 0x00); | |
567 | pcf50633_reg_write(pcf, PCF50633_REG_INT5M, 0x00); | |
568 | ||
f7b2a77f LPC |
569 | ret = request_threaded_irq(client->irq, NULL, pcf50633_irq, |
570 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
571 | "pcf50633", pcf); | |
24213ae1 LPC |
572 | |
573 | if (ret) { | |
574 | dev_err(pcf->dev, "Failed to request IRQ %d\n", ret); | |
f7b2a77f | 575 | goto err_free; |
24213ae1 LPC |
576 | } |
577 | ||
f52046b1 BR |
578 | /* Create sub devices */ |
579 | pcf50633_client_dev_register(pcf, "pcf50633-input", | |
580 | &pcf->input_pdev); | |
581 | pcf50633_client_dev_register(pcf, "pcf50633-rtc", | |
582 | &pcf->rtc_pdev); | |
583 | pcf50633_client_dev_register(pcf, "pcf50633-mbc", | |
584 | &pcf->mbc_pdev); | |
585 | pcf50633_client_dev_register(pcf, "pcf50633-adc", | |
586 | &pcf->adc_pdev); | |
f5bf403a LPC |
587 | pcf50633_client_dev_register(pcf, "pcf50633-backlight", |
588 | &pcf->bl_pdev); | |
589 | ||
f52046b1 BR |
590 | |
591 | for (i = 0; i < PCF50633_NUM_REGULATORS; i++) { | |
592 | struct platform_device *pdev; | |
593 | ||
594 | pdev = platform_device_alloc("pcf50633-regltr", i); | |
595 | if (!pdev) { | |
24213ae1 | 596 | dev_err(pcf->dev, "Cannot create regulator %d\n", i); |
f52046b1 BR |
597 | continue; |
598 | } | |
599 | ||
600 | pdev->dev.parent = pcf->dev; | |
bbb2e496 LPC |
601 | platform_device_add_data(pdev, &pdata->reg_init_data[i], |
602 | sizeof(pdata->reg_init_data[i])); | |
f52046b1 BR |
603 | pcf->regulator_pdev[i] = pdev; |
604 | ||
605 | platform_device_add(pdev); | |
606 | } | |
607 | ||
f52046b1 BR |
608 | if (enable_irq_wake(client->irq) < 0) |
609 | dev_err(pcf->dev, "IRQ %u cannot be enabled as wake-up source" | |
610 | "in this hardware revision", client->irq); | |
611 | ||
612 | ret = sysfs_create_group(&client->dev.kobj, &pcf_attr_group); | |
613 | if (ret) | |
614 | dev_err(pcf->dev, "error creating sysfs entries\n"); | |
615 | ||
616 | if (pdata->probe_done) | |
617 | pdata->probe_done(pcf); | |
618 | ||
619 | return 0; | |
620 | ||
24213ae1 LPC |
621 | err_free: |
622 | i2c_set_clientdata(client, NULL); | |
f52046b1 | 623 | kfree(pcf); |
24213ae1 | 624 | |
f52046b1 BR |
625 | return ret; |
626 | } | |
627 | ||
628 | static int __devexit pcf50633_remove(struct i2c_client *client) | |
629 | { | |
630 | struct pcf50633 *pcf = i2c_get_clientdata(client); | |
631 | int i; | |
632 | ||
633 | free_irq(pcf->irq, pcf); | |
634 | ||
635 | platform_device_unregister(pcf->input_pdev); | |
636 | platform_device_unregister(pcf->rtc_pdev); | |
637 | platform_device_unregister(pcf->mbc_pdev); | |
638 | platform_device_unregister(pcf->adc_pdev); | |
639 | ||
640 | for (i = 0; i < PCF50633_NUM_REGULATORS; i++) | |
641 | platform_device_unregister(pcf->regulator_pdev[i]); | |
642 | ||
f322d5f0 | 643 | i2c_set_clientdata(client, NULL); |
f52046b1 BR |
644 | kfree(pcf); |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | static struct i2c_device_id pcf50633_id_table[] = { | |
650 | {"pcf50633", 0x73}, | |
8915e540 | 651 | {/* end of list */} |
f52046b1 BR |
652 | }; |
653 | ||
654 | static struct i2c_driver pcf50633_driver = { | |
655 | .driver = { | |
656 | .name = "pcf50633", | |
f52046b1 BR |
657 | }, |
658 | .id_table = pcf50633_id_table, | |
659 | .probe = pcf50633_probe, | |
660 | .remove = __devexit_p(pcf50633_remove), | |
25993e4e LPC |
661 | .suspend = pcf50633_suspend, |
662 | .resume = pcf50633_resume, | |
f52046b1 BR |
663 | }; |
664 | ||
665 | static int __init pcf50633_init(void) | |
666 | { | |
667 | return i2c_add_driver(&pcf50633_driver); | |
668 | } | |
669 | ||
670 | static void __exit pcf50633_exit(void) | |
671 | { | |
672 | i2c_del_driver(&pcf50633_driver); | |
673 | } | |
674 | ||
675 | MODULE_DESCRIPTION("I2C chip driver for NXP PCF50633 PMU"); | |
676 | MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>"); | |
677 | MODULE_LICENSE("GPL"); | |
678 | ||
2021de87 | 679 | subsys_initcall(pcf50633_init); |
f52046b1 | 680 | module_exit(pcf50633_exit); |